Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4626,8 +4626,8 @@
            "type is vector!");
     if (Operand.getValueType() == VT) return Operand;   // noop extension
     assert((!VT.isVector() ||
-            VT.getVectorNumElements() ==
-            Operand.getValueType().getVectorNumElements()) &&
+            VT.getVectorElementCount() ==
+            Operand.getValueType().getVectorElementCount()) &&
            "Vector element count mismatch!");
     assert(Operand.getValueType().bitsLT(VT) &&
            "Invalid sext node, dst < src!");
@@ -4645,8 +4645,8 @@
            "type is vector!");
     if (Operand.getValueType() == VT) return Operand;   // noop extension
     assert((!VT.isVector() ||
-            VT.getVectorNumElements() ==
-            Operand.getValueType().getVectorNumElements()) &&
+            VT.getVectorElementCount() ==
+            Operand.getValueType().getVectorElementCount()) &&
            "Vector element count mismatch!");
     assert(Operand.getValueType().bitsLT(VT) &&
            "Invalid zext node, dst < src!");
@@ -4664,8 +4664,8 @@
            "type is vector!");
     if (Operand.getValueType() == VT) return Operand;   // noop extension
     assert((!VT.isVector() ||
-            VT.getVectorNumElements() ==
-            Operand.getValueType().getVectorNumElements()) &&
+            VT.getVectorElementCount() ==
+            Operand.getValueType().getVectorElementCount()) &&
            "Vector element count mismatch!");
     assert(Operand.getValueType().bitsLT(VT) &&
            "Invalid anyext node, dst < src!");
@@ -4694,8 +4694,8 @@
            "type is vector!");
     if (Operand.getValueType() == VT) return Operand;   // noop truncate
     assert((!VT.isVector() ||
-            VT.getVectorNumElements() ==
-            Operand.getValueType().getVectorNumElements()) &&
+            VT.getVectorElementCount() ==
+            Operand.getValueType().getVectorElementCount()) &&
            "Vector element count mismatch!");
     assert(Operand.getValueType().bitsGT(VT) &&
            "Invalid truncate node, src < dst!");
@@ -5337,7 +5337,7 @@
            "SIGN_EXTEND_INREG type should be vector iff the operand "
            "type is vector!");
     assert((!EVT.isVector() ||
-            EVT.getVectorNumElements() == VT.getVectorNumElements()) &&
+            EVT.getVectorElementCount() == VT.getVectorElementCount()) &&
            "Vector element counts must match in SIGN_EXTEND_INREG");
     assert(EVT.bitsLE(VT) && "Not extending!");
     if (EVT == VT) return N1;  // Not actually extending
@@ -5626,7 +5626,8 @@
     assert(VT.isVector() == N1.getValueType().isVector() &&
            "SETCC type should be vector iff the operand type is vector!");
     assert((!VT.isVector() ||
-            VT.getVectorNumElements() == N1.getValueType().getVectorNumElements()) &&
+            VT.getVectorElementCount() ==
+            N1.getValueType().getVectorElementCount()) &&
            "SETCC vector element counts must match!");
     // Use FoldSetCC to simplify SETCC's.
     if (SDValue V = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL))
Index: llvm/test/CodeGen/AArch64/sve-ext-trunc.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-ext-trunc.ll
@@ -0,0 +1,142 @@
+; REQUIRES: asserts
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+define <vscale x 8 x i16> @sext_i8toi16(<vscale x 8 x i8> %in) {
+; CHECK-LABEL: sext_i8toi16
+; CHECK:       sxtb z0.h, p{{[0-7]}}/m, z0.h
+entry:
+  %out = sext <vscale x 8 x i8> %in to <vscale x 8 x i16>
+  ret <vscale x 8 x i16> %out
+}
+
+define <vscale x 4 x i32> @sext_i8toi32(<vscale x 4 x i8> %in) {
+; CHECK-LABEL: sext_i8toi32
+; CHECK:       sxtb z0.s, p{{[0-7]}}/m, z0.s
+entry:
+  %out = sext <vscale x 4 x i8> %in to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %out
+}
+
+define <vscale x 4 x i32> @sext_i16toi32(<vscale x 4 x i16> %in) {
+; CHECK-LABEL: sext_i16toi32
+; CHECK:       sxth z0.s, p{{[0-7]}}/m, z0.s
+entry:
+  %out = sext <vscale x 4 x i16> %in to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %out
+}
+
+define <vscale x 2 x i64> @sext_i8toi64(<vscale x 2 x i8> %in) {
+; CHECK-LABEL: sext_i8toi64
+; CHECK:       sxtb z0.d, p{{[0-7]}}/m, z0.d
+entry:
+  %out = sext <vscale x 2 x i8> %in to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 2 x i64> @sext_i16toi64(<vscale x 2 x i16> %in) {
+; CHECK-LABEL: sext_i16toi64
+; CHECK:       sxth z0.d, p{{[0-7]}}/m, z0.d
+entry:
+  %out = sext <vscale x 2 x i16> %in to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 2 x i64> @sext_i32toi64(<vscale x 2 x i32> %in) {
+; CHECK-LABEL: sext_i32toi64
+; CHECK:       sxtw z0.d, p{{[0-7]}}/m, z0.d
+entry:
+  %out = sext <vscale x 2 x i32> %in to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 8 x i16> @zext_i8toi16(<vscale x 8 x i8> %in) {
+; CHECK-LABEL: zext_i8toi16
+; CHECK:       and z0.h, z0.h, #0xff
+entry:
+  %out = zext <vscale x 8 x i8> %in to <vscale x 8 x i16>
+  ret <vscale x 8 x i16> %out
+}
+
+define <vscale x 4 x i32> @zext_i8toi32(<vscale x 4 x i8> %in) {
+; CHECK-LABEL: zext_i8toi32
+; CHECK:       and z0.s, z0.s, #0xff
+entry:
+  %out = zext <vscale x 4 x i8> %in to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %out
+}
+
+define <vscale x 4 x i32> @zext_i16toi32(<vscale x 4 x i16> %in) {
+; CHECK-LABEL: zext_i16toi32
+; CHECK:       and z0.s, z0.s, #0xffff
+entry:
+  %out = zext <vscale x 4 x i16> %in to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %out
+}
+
+define <vscale x 2 x i64> @zext_i8toi64(<vscale x 2 x i8> %in) {
+; CHECK-LABEL: zext_i8toi64
+; CHECK:       and z0.d, z0.d, #0xff
+entry:
+  %out = zext <vscale x 2 x i8> %in to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 2 x i64> @zext_i16toi64(<vscale x 2 x i16> %in) {
+; CHECK-LABEL: zext_i16toi64
+; CHECK:       and z0.d, z0.d, #0xffff
+entry:
+  %out = zext <vscale x 2 x i16> %in to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 2 x i64> @zext_i32toi64(<vscale x 2 x i32> %in) {
+; CHECK-LABEL: zext_i32toi64
+; CHECK:       and z0.d, z0.d, #0xffffffff
+entry:
+  %out = zext <vscale x 2 x i32> %in to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %out
+}
+
+; For all the functions below should the operation is a nop
+define <vscale x 8 x i8> @trunc_i16toi8(<vscale x 8 x i16> %in) {
+; CHECK-LABEL: trunc_i16toi8
+entry:
+  %out = trunc <vscale x 8 x i16> %in to <vscale x 8 x i8>
+  ret <vscale x 8 x i8> %out
+}
+
+define <vscale x 4 x i8> @trunc_i32toi8(<vscale x 4 x i32> %in) {
+; CHECK-LABEL: trunc_i32toi8
+entry:
+  %out = trunc <vscale x 4 x i32> %in to <vscale x 4 x i8>
+  ret <vscale x 4 x i8> %out
+}
+
+define <vscale x 2 x i8> @trunc_i64toi8(<vscale x 2 x i64> %in) {
+; CHECK-LABEL: trunc_i64toi8
+entry:
+  %out = trunc <vscale x 2 x i64> %in to <vscale x 2 x i8>
+  ret <vscale x 2 x i8> %out
+}
+
+define <vscale x 4 x i16> @trunc_i32toi16(<vscale x 4 x i32> %in) {
+; CHECK-LABEL: trunc_i32toi16
+entry:
+  %out = trunc <vscale x 4 x i32> %in to <vscale x 4 x i16>
+  ret <vscale x 4 x i16> %out
+}
+
+define <vscale x 2 x i16> @trunc_i64toi16(<vscale x 2 x i64> %in) {
+; CHECK-LABEL: trunc_i64toi16
+entry:
+  %out = trunc <vscale x 2 x i64> %in to <vscale x 2 x i16>
+  ret <vscale x 2 x i16> %out
+}
+
+define <vscale x 2 x i32> @trunc_i64toi32(<vscale x 2 x i64> %in) {
+; CHECK-LABEL: trunc_i64toi32
+entry:
+  %out = trunc <vscale x 2 x i64> %in to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %out
+}
+