Index: llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp
+++ llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp
@@ -79,14 +79,19 @@
   if (GlobalBaseReg)
     return GlobalBaseReg;
 
+  MipsSubtarget const &STI =
+      static_cast<const MipsSubtarget &>(MF.getSubtarget());
+
   const TargetRegisterClass *RC =
-      static_cast<const MipsSubtarget &>(MF.getSubtarget()).inMips16Mode()
+      STI.inMips16Mode()
           ? &Mips::CPU16RegsRegClass
-          : static_cast<const MipsTargetMachine &>(MF.getTarget())
-                    .getABI()
-                    .IsN64()
-                ? &Mips::GPR64RegClass
-                : &Mips::GPR32RegClass;
+          : STI.inMicroMipsMode()
+                ? &Mips::GPRMM16RegClass
+                : static_cast<const MipsTargetMachine &>(MF.getTarget())
+                          .getABI()
+                          .IsN64()
+                      ? &Mips::GPR64RegClass
+                      : &Mips::GPR32RegClass;
   return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
 }
 
Index: llvm/trunk/test/CodeGen/Mips/micromips-gp-rc.ll
===================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-gp-rc.ll
+++ llvm/trunk/test/CodeGen/Mips/micromips-gp-rc.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+
+@g = external global i32
+
+; Function Attrs: noreturn nounwind
+define void @foo() #0 {
+entry:
+  %0 = load i32* @g, align 4
+  tail call void @exit(i32 signext %0)
+  unreachable
+}
+
+; Function Attrs: noreturn
+declare void @exit(i32 signext)
+
+; CHECK: move $gp, ${{[0-9]+}}
+