[llvm-objdump] -d: delete spaces among raw instruction bytes

[MaskRay]

Summary

On a disassembly line, the raw bytes are relatively less important.
--no-show-raw-insn can hide them but the option is not the default.
Delete spaces to leave columns to most useful stuff (for example, I plan
to implement visual arrows similar to --visual-jumps added in GNU
objdump 2.34, but I'd take more inspirations from radare2's pd command).

Also move the instruction left by 8 columns. This is especially helpful
for targets with x86, which has potentially long instructions.
Before:

2015c4: ff 15 be 12 00 00             callq   *4798(%rip)  # 202888 <crtstuff.c+0x202888>
2015ca: f4                            hlt
2015cb: 0f 1f 44 00 00                nopl    (%rax,%rax)

After (8 columns narrower):

2015c4: ff15be120000          callq   *4798(%rip)  # 202888 <crtstuff.c+0x202888>
2015ca: f4                    hlt
2015cb: 0f1f440000            nopl    (%rax,%rax)

Spaces are not deleted for non-x86 because otherwise the patch would
have to touch ~700 more tests. I may update them based on feedback.
This diff just includes some representative test changes. 40+ test
changes are omitted.

AArch64 instructions are encoded in little-endian and GNU objdump prints
04030201 for byte sequence 01 02 03 04. Personally I find the
hexpair order annoying because I prefer the way bytes are presented in a
hex editor.

[joerg]

I'm not sure about this change. It might make sense on x86, but many RISC architectures love to put data into the instruction stream and being able to pick them out is quite important for understanding the disassembly.

[MaskRay]

In D79309#2016924, @joerg wrote:

I'm not sure about this change. It might make sense on x86, but many RISC architectures love to put data into the instruction stream and being able to pick them out is quite important for understanding the disassembly.

I don't understand your comment. This patch delete spaces to make the output compacter, how does that make RISC architectures unhappy?

[joerg]

The more compact output is a lot harder to read when you have to find embedded data. I wouldn't mind dropping half the spaces to have columns of 4 hex digits, but anything more is really hard to read.

[MaskRay]

In D79309#2016929, @joerg wrote:

The more compact output is a lot harder to read when you have to find embedded data. I wouldn't mind dropping half the spaces to have columns of 4 hex digits, but anything more is really hard to read.

Embedded data is like the following:

// llvm/test/tools/llvm-objdump/ELF/ARM/disassemble-code-data-mix.s (also see D79284)
// ARM .byte/.short/.word
00000020 <$d.1>:
      20:       00 00 00 00     .word   0x00000000

// STT_OBJECT/STT_COMMON symbols
00000024 <myStr>:
      24: 74 65 73 74 20 73 74 72         test str
      2c: 69 6e 67 00                     ing.

If we extend this patch to affect non-x86 *instructions* as well:

      18: 04b09de4              ldr     r11, [sp], #4
      1c: 1eff2fe1              <unknown>

## For consistency, we should delete spaces here as well.
00000020 <$d.1>:
      20:       00 00 00 00     .word   0x00000000

## dumpELFData, unaffected.
00000024 <myStr>:
      24: 74 65 73 74 20 73 74 72         test str
      2c: 69 6e 67 00                     ing.

Note that dumpELFData is not affected.

[joerg]

ARM's data detection only works for unstripped binaries. Other architectures often don't even have such markers at all.

[psmith]

I don't have a strong opinion here, the spaced bytes more closely match the output of the llvm-mc which can make disassembler tests easier to write. On the other hand it can be useful to see the structure of the disassembly of instructions when the mapping symbols exist.
Arm GNU objdump does the following:

address: 12345678 <spaces> <disassembly of arm instruction
address: 1234 5678 <spaces> for 32-bit Thumb instruction made up of two half words
address: 1234 <spaces> for 16-bit Thumb instruction made up a half word
address: 12345678 <spaces> for .word 0x12345678

I don't have a lot of experience of non Arm RISC architectures though so I don't know what looks reasonable for them.

[mtrent]

In D79309#2016936, @joerg wrote:

ARM's data detection only works for unstripped binaries. Other architectures often don't even have such markers at all.

I agree that ideal disassembly format differs from architecture to architecture.

I also agree that this particular change is fine for x86_64.

[mtrent]

llvm/lib/MC/MCInstPrinter.cpp

37

Isn't this just llvm::dumpBytes with an optional 3rd parameter to suppress the First if/else test? I guess it's only a small amount of copy-pasted code...

[jhenderson]

Hmm... I'm not convinced that this is the right thing to do. Believe it or not, there will be people out there with scripts who parse the instruction bytes in their scripts for whatever reason. I can think of some reasons where this might be slightly useful. Changing this behaviour will break things for them. I also feel like it's less readable to me, as it takes more effort to identify the individual bytes, but I acknowledge that's a personal opinion.

You said the motivation is because you want more columns to do another feature. If people want to use that feature and need narrower output, why can't they choose to opt-in (which they'd be doing for the new option) by disabling the raw instruction bytes?

Also, what about another option to control the spacing? Something like --compact, or maybe even something crazy that allows you to format individual bytes using something like a printf format specifier. A good example of this is the od tool which provides different options for width per byte.

[MaskRay]

Abandoning.

Will do D81590 (decrease instruction indentation for non-x86)

llvm/include/llvm/MC/MCInstPrinter.h

 class MCInstrInfo;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class raw_ostream;
 class StringRef;
 
 /// Convert `Bytes' to a hex string and output to `OS'
 void dumpBytes(ArrayRef<uint8_t> Bytes, raw_ostream &OS);
+void dumpBytesNoSpace(ArrayRef<uint8_t> Bytes, raw_ostream &OS);
 
 namespace HexStyle {
 
 enum Style {
   C,  ///< 0xff
   Asm ///< 0ffh
 };
 

llvm/lib/MC/MCInstPrinter.cpp

if (First)
       First = false;
     else
       OS << ' ';
     OS << hex_rep[(i & 0xF0) >> 4];
     OS << hex_rep[i & 0xF];
   }
 }
 
+void llvm::dumpBytesNoSpace(ArrayRef<uint8_t> bytes, raw_ostream &OS) {
+  static const char hex_rep[] = "0123456789abcdef";
+  for (char i : bytes) {
+    OS << hex_rep[(i & 0xF0) >> 4];
+    OS << hex_rep[i & 0xF];
+  }
+}
+
 MCInstPrinter::~MCInstPrinter() = default;
 
 /// getOpcodeName - Return the name of the specified opcode enum (e.g.
 /// "MOV32ri") or empty if we can't resolve it.
 StringRef MCInstPrinter::getOpcodeName(unsigned Opcode) const {
   return MII.getName(Opcode);
 }
 

llvm/test/MC/AArch64/inst-directive-other.s

 
 // CHECK-ASM:        .p2align  2
 // CHECK-ASM:        .globl  _func
 // CHECK-ASM: _func:
 // CHECK-ASM:        nop
 // CHECK-ASM:        .{{long|word}}   3573751839
 // CHECK-ASM:        .inst   0xd503201f
 
-// CHECK-OBJ:        0:       1f 20 03 d5     nop
-// CHECK-OBJ-CODE:   4:       1f 20 03 d5     nop
-// CHECK-OBJ-DATA:   4:       1f 20 03 d5     .word 0xd503201f
-// CHECK-OBJ-BE:     4:       d5 03 20 1f     .word 0xd503201f
-// CHECK-OBJ:        8:       1f 20 03 d5     nop
+// CHECK-OBJ:        0:       1f2003d5     nop
+// CHECK-OBJ-CODE:   4:       1f2003d5     nop
+// CHECK-OBJ-DATA:   4:       1f2003d5     .word 0xd503201f
+// CHECK-OBJ-BE:     4:       d503201f     .word 0xd503201f
+// CHECK-OBJ:        8:       1f2003d5     nop

llvm/test/MC/ARM/inst-directive-other.s

 // CHECK-ASM:        bx      lr
 // CHECK-ASM:        .short  18288
 // CHECK-ASM:        .inst.n 0x4770
 // CHECK-ASM:        mov.w   r0, #42
 // CHECK-ASM:        .short  61519
 // CHECK-ASM:        .short  42
 // CHECK-ASM:        .inst.w 0xf04f002a
 
-// CHECK-OBJ:        0:       70 47           bx lr
-// CHECK-OBJ-CODE:   2:       70 47           bx lr
-// CHECK-OBJ-DATA:   2:       70 47           .short 0x4770
-// CHECK-OBJ:        4:       70 47           bx lr
-// CHECK-OBJ:        6:       4f f0 2a 00     mov.w   r0, #42
-// CHECK-OBJ-CODE:   a:       4f f0 2a 00     mov.w   r0, #42
-// CHECK-OBJ-DATA:   a:       4f f0 2a 00     .word 0x002af04f
-// CHECK-OBJ:        e:       4f f0 2a 00     mov.w   r0, #42
+// CHECK-OBJ:        0:       7047         bx lr
+// CHECK-OBJ-CODE:   2:       7047         bx lr
+// CHECK-OBJ-DATA:   2:       7047         .short 0x4770
+// CHECK-OBJ:        4:       7047         bx lr
+// CHECK-OBJ:        6:       4ff02a00     mov.w   r0, #42
+// CHECK-OBJ-CODE:   a:       4ff02a00     mov.w   r0, #42
+// CHECK-OBJ-DATA:   a:       4ff02a00     .word 0x002af04f
+// CHECK-OBJ:        e:       4ff02a00     mov.w   r0, #42

llvm/test/MC/ELF/relax-arith.s

 // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-objdump -d - | FileCheck  %s
 
 // Test that we correctly relax these instructions into versions that use
 // 16 or 32 bit immediate values.
 
 bar:
 // CHECK:      Disassembly of section imul:
 // CHECK-EMPTY:
 // CHECK-NEXT: <imul>:
-// CHECK-NEXT:   0: 66 69 db 00 00                       imulw $0, %bx, %bx
-// CHECK-NEXT:   5: 66 69 1c 25 00 00 00 00 00 00        imulw $0, 0, %bx
-// CHECK-NEXT:   f: 69 db 00 00 00 00                    imull $0, %ebx, %ebx
-// CHECK-NEXT:  15: 69 1c 25 00 00 00 00 00 00 00 00     imull $0, 0, %ebx
-// CHECK-NEXT:  20: 48 69 db 00 00 00 00                 imulq $0, %rbx, %rbx
-// CHECK-NEXT:  27: 48 69 1c 25 00 00 00 00 00 00 00 00  imulq $0, 0, %rbx
+// CHECK-NEXT:   0: 6669db0000               imulw $0, %bx, %bx
+// CHECK-NEXT:   5: 66691c25000000000000     imulw $0, 0, %bx
+// CHECK-NEXT:   f: 69db00000000             imull $0, %ebx, %ebx
+// CHECK-NEXT:  15: 691c250000000000000000   imull $0, 0, %ebx
+// CHECK-NEXT:  20: 4869db00000000           imulq $0, %rbx, %rbx
+// CHECK-NEXT:  27: 48691c250000000000000000 imulq $0, 0, %rbx
         .section imul,"x"
         imul $foo, %bx,  %bx
         imul $foo, bar,  %bx
         imul $foo, %ebx, %ebx
         imul $foo, bar,  %ebx
         imul $foo, %rbx, %rbx
         imul $foo, bar,  %rbx
 
 // CHECK:      Disassembly of section and:
 // CHECK-EMPTY:
 // CHECK-NEXT: <and>:
-// CHECK-NEXT:   0: 66 81 e3 00 00                       andw $0, %bx
-// CHECK-NEXT:   5: 66 81 24 25 00 00 00 00 00 00        andw $0, 0
-// CHECK-NEXT:   f: 81 e3 00 00 00 00                    andl $0, %ebx
-// CHECK-NEXT:  15: 81 24 25 00 00 00 00 00 00 00 00     andl $0, 0
-// CHECK-NEXT:  20: 48 81 e3 00 00 00 00                 andq $0, %rbx
-// CHECK-NEXT:  27: 48 81 24 25 00 00 00 00 00 00 00 00  andq $0, 0
+// CHECK-NEXT:   0: 6681e30000               andw $0, %bx
+// CHECK-NEXT:   5: 66812425000000000000     andw $0, 0
+// CHECK-NEXT:   f: 81e300000000             andl $0, %ebx
+// CHECK-NEXT:  15: 8124250000000000000000   andl $0, 0
+// CHECK-NEXT:  20: 4881e300000000           andq $0, %rbx
+// CHECK-NEXT:  27: 488124250000000000000000 andq $0, 0
         .section and,"x"
         and  $foo, %bx
         andw $foo, bar
         and  $foo, %ebx
         andl $foo, bar
         and  $foo, %rbx
         andq $foo, bar
 
 // CHECK:      <or>:
-// CHECK-NEXT:   0: 66 81 cb 00 00                       orw $0, %bx
-// CHECK-NEXT:   5: 66 81 0c 25 00 00 00 00 00 00        orw $0, 0
-// CHECK-NEXT:   f: 81 cb 00 00 00 00                    orl $0, %ebx
-// CHECK-NEXT:  15: 81 0c 25 00 00 00 00 00 00 00 00     orl $0, 0
-// CHECK-NEXT:  20: 48 81 cb 00 00 00 00                 orq $0, %rbx
-// CHECK-NEXT:  27: 48 81 0c 25 00 00 00 00 00 00 00 00  orq $0, 0
+// CHECK-NEXT:   0: 6681cb0000               orw $0, %bx
+// CHECK-NEXT:   5: 66810c25000000000000     orw $0, 0
+// CHECK-NEXT:   f: 81cb00000000             orl $0, %ebx
+// CHECK-NEXT:  15: 810c250000000000000000   orl $0, 0
+// CHECK-NEXT:  20: 4881cb00000000           orq $0, %rbx
+// CHECK-NEXT:  27: 48810c250000000000000000 orq $0, 0
         .section or,"x"
         or  $foo, %bx
         orw $foo, bar
         or  $foo, %ebx
         orl $foo, bar
         or  $foo, %rbx
         orq $foo, bar
 
 // CHECK:      Disassembly of section xor:
 // CHECK-EMPTY:
 // CHECK-NEXT: <xor>:
-// CHECK-NEXT:   0: 66 81 f3 00 00                       xorw $0, %bx
-// CHECK-NEXT:   5: 66 81 34 25 00 00 00 00 00 00        xorw $0, 0
-// CHECK-NEXT:   f: 81 f3 00 00 00 00                    xorl $0, %ebx
-// CHECK-NEXT:  15: 81 34 25 00 00 00 00 00 00 00 00     xorl $0, 0
-// CHECK-NEXT:  20: 48 81 f3 00 00 00 00                 xorq $0, %rbx
-// CHECK-NEXT:  27: 48 81 34 25 00 00 00 00 00 00 00 00  xorq $0, 0
+// CHECK-NEXT:   0: 6681f30000               xorw $0, %bx
+// CHECK-NEXT:   5: 66813425000000000000     xorw $0, 0
+// CHECK-NEXT:   f: 81f300000000             xorl $0, %ebx
+// CHECK-NEXT:  15: 8134250000000000000000   xorl $0, 0
+// CHECK-NEXT:  20: 4881f300000000           xorq $0, %rbx
+// CHECK-NEXT:  27: 488134250000000000000000 xorq $0, 0
         .section xor,"x"
         xor  $foo, %bx
         xorw $foo, bar
         xor  $foo, %ebx
         xorl $foo, bar
         xor  $foo, %rbx
         xorq $foo, bar
 
 // CHECK:      Disassembly of section add:
 // CHECK-EMPTY:
 // CHECK-NEXT: <add>:
-// CHECK-NEXT:   0: 66 81 c3 00 00                       addw $0, %bx
-// CHECK-NEXT:   5: 66 81 04 25 00 00 00 00 00 00        addw $0, 0
-// CHECK-NEXT:   f: 81 c3 00 00 00 00                    addl $0, %ebx
-// CHECK-NEXT:  15: 81 04 25 00 00 00 00 00 00 00 00     addl $0, 0
-// CHECK-NEXT:  20: 48 81 c3 00 00 00 00                 addq $0, %rbx
-// CHECK-NEXT:  27: 48 81 04 25 00 00 00 00 00 00 00 00  addq $0, 0
+// CHECK-NEXT:   0: 6681c30000               addw $0, %bx
+// CHECK-NEXT:   5: 66810425000000000000     addw $0, 0
+// CHECK-NEXT:   f: 81c300000000             addl $0, %ebx
+// CHECK-NEXT:  15: 8104250000000000000000   addl $0, 0
+// CHECK-NEXT:  20: 4881c300000000           addq $0, %rbx
+// CHECK-NEXT:  27: 488104250000000000000000 addq $0, 0
         .section add,"x"
-        add  $foo, %bx
+        add $foo, %bx
         addw $foo, bar
-        add  $foo, %ebx
+        add $foo, %ebx
         addl $foo, bar
-        add  $foo, %rbx
+        add $foo, %rbx
         addq $foo, bar
 
 // CHECK:      Disassembly of section sub:
 // CHECK-EMPTY:
 // CHECK-NEXT: <sub>:
-// CHECK-NEXT:   0: 66 81 eb 00 00                       subw $0, %bx
-// CHECK-NEXT:   5: 66 81 2c 25 00 00 00 00 00 00        subw $0, 0
-// CHECK-NEXT:   f: 81 eb 00 00 00 00                    subl $0, %ebx
-// CHECK-NEXT:  15: 81 2c 25 00 00 00 00 00 00 00 00     subl $0, 0
-// CHECK-NEXT:  20: 48 81 eb 00 00 00 00                 subq $0, %rbx
-// CHECK-NEXT:  27: 48 81 2c 25 00 00 00 00 00 00 00 00  subq $0, 0
+// CHECK-NEXT:   0: 6681eb0000               subw $0, %bx
+// CHECK-NEXT:   5: 66812c25000000000000     subw $0, 0
+// CHECK-NEXT:   f: 81eb00000000             subl $0, %ebx
+// CHECK-NEXT:  15: 812c250000000000000000   subl $0, 0
+// CHECK-NEXT:  20: 4881eb00000000           subq $0, %rbx
+// CHECK-NEXT:  27: 48812c250000000000000000 subq $0, 0
         .section sub,"x"
         sub  $foo, %bx
         subw $foo, bar
         sub  $foo, %ebx
         subl $foo, bar
         sub  $foo, %rbx
         subq $foo, bar
 
 // CHECK:      Disassembly of section cmp:
 // CHECK-EMPTY:
 // CHECK-NEXT: <cmp>:
-// CHECK-NEXT:   0: 66 81 fb 00 00                       cmpw $0, %bx
-// CHECK-NEXT:   5: 66 81 3c 25 00 00 00 00 00 00        cmpw $0, 0
-// CHECK-NEXT:   f: 81 fb 00 00 00 00                    cmpl $0, %ebx
-// CHECK-NEXT:  15: 81 3c 25 00 00 00 00 00 00 00 00     cmpl $0, 0
-// CHECK-NEXT:  20: 48 81 fb 00 00 00 00                 cmpq $0, %rbx
-// CHECK-NEXT:  27: 48 81 3c 25 00 00 00 00 00 00 00 00  cmpq $0, 0
+// CHECK-NEXT:   0: 6681fb0000               cmpw $0, %bx
+// CHECK-NEXT:   5: 66813c25000000000000     cmpw $0, 0
+// CHECK-NEXT:   f: 81fb00000000             cmpl $0, %ebx
+// CHECK-NEXT:  15: 813c250000000000000000   cmpl $0, 0
+// CHECK-NEXT:  20: 4881fb00000000           cmpq $0, %rbx
+// CHECK-NEXT:  27: 48813c250000000000000000 cmpq $0, 0
         .section cmp,"x"
         cmp  $foo, %bx
         cmpw $foo, bar
         cmp  $foo, %ebx
         cmpl $foo, bar
         cmp  $foo, %rbx
         cmpq $foo, bar
 
 // CHECK:      Disassembly of section push:
 // CHECK-EMPTY:
 // CHECK-NEXT: <push>:
-// CHECK-NEXT:   0: 66 68 00 00                          pushw $0
-// CHECK-NEXT:   4: 68 00 00 00 00                       pushq $0
+// CHECK-NEXT:   0: 66680000                 pushw $0
+// CHECK-NEXT:   4: 6800000000               pushq $0
         .section push,"x"
         pushw $foo
         push  $foo
 
 // CHECK:      Disassembly of section adc:
 // CHECK-EMPTY:
 // CHECK-NEXT: <adc>:
-// CHECK-NEXT:   0: 66 81 d3 00 00                       adcw $0, %bx
-// CHECK-NEXT:   5: 66 81 14 25 00 00 00 00 00 00        adcw $0, 0
-// CHECK-NEXT:   f: 81 d3 00 00 00 00                    adcl $0, %ebx
-// CHECK-NEXT:  15: 81 14 25 00 00 00 00 00 00 00 00     adcl $0, 0
-// CHECK-NEXT:  20: 48 81 d3 00 00 00 00                 adcq $0, %rbx
-// CHECK-NEXT:  27: 48 81 14 25 00 00 00 00 00 00 00 00  adcq $0, 0
+// CHECK-NEXT:   0: 6681d30000               adcw $0, %bx
+// CHECK-NEXT:   5: 66811425000000000000     adcw $0, 0
+// CHECK-NEXT:   f: 81d300000000             adcl $0, %ebx
+// CHECK-NEXT:  15: 8114250000000000000000   adcl $0, 0
+// CHECK-NEXT:  20: 4881d300000000           adcq $0, %rbx
+// CHECK-NEXT:  27: 488114250000000000000000 adcq $0, 0
         .section adc,"x"
-        adc  $foo, %bx
+        adc $foo, %bx
         adcw $foo, bar
-        adc  $foo, %ebx
+        adc $foo, %ebx
         adcl $foo, bar
-        adc  $foo, %rbx
+        adc $foo, %rbx
         adcq $foo, bar
 
 // CHECK:      Disassembly of section sbb:
 // CHECK-EMPTY:
 // CHECK-NEXT: <sbb>:
-// CHECK-NEXT:   0: 66 81 db 00 00                       sbbw $0, %bx
-// CHECK-NEXT:   5: 66 81 1c 25 00 00 00 00 00 00        sbbw $0, 0
-// CHECK-NEXT:   f: 81 db 00 00 00 00                    sbbl $0, %ebx
-// CHECK-NEXT:  15: 81 1c 25 00 00 00 00 00 00 00 00     sbbl $0, 0
-// CHECK-NEXT:  20: 48 81 db 00 00 00 00                 sbbq $0, %rbx
-// CHECK-NEXT:  27: 48 81 1c 25 00 00 00 00 00 00 00 00  sbbq $0, 0
+// CHECK-NEXT:   0: 6681db0000               sbbw $0, %bx
+// CHECK-NEXT:   5: 66811c25000000000000     sbbw $0, 0
+// CHECK-NEXT:   f: 81db00000000             sbbl $0, %ebx
+// CHECK-NEXT:  15: 811c250000000000000000   sbbl $0, 0
+// CHECK-NEXT:  20: 4881db00000000           sbbq $0, %rbx
+// CHECK-NEXT:  27: 48811c250000000000000000 sbbq $0, 0
         .section sbb,"x"
-        sbb  $foo, %bx
+        sbb $foo, %bx
         sbbw $foo, bar
-        sbb  $foo, %ebx
+        sbb $foo, %ebx
         sbbl $foo, bar
-        sbb  $foo, %rbx
+        sbb $foo, %rbx
         sbbq $foo, bar

llvm/test/tools/llvm-objdump/ELF/ARM/v5t-subarch.s

 @ RUN: llvm-mc < %s -triple armv5t-elf -filetype=obj | llvm-objdump --triple=arm -d - | FileCheck %s
 
 .arch armv5t
 
 clz:
 clz r0, r1
 
 @ CHECK-LABEL: clz
-@ CHECK: 11 0f 6f e1
+@ CHECK: 110f6fe1
 

llvm/test/tools/llvm-objdump/X86/disassemble-align.s

 # RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t
 
 # Use '|' to show where the tabs line up.
 # RUN: llvm-objdump -d --print-imm-hex %t | tr '\t' '|' | FileCheck --strict-whitespace %s
 
 # RUN: llvm-objdump -d --print-imm-hex --no-show-raw-insn %t | tr '\t' '|' | \
 # RUN:   FileCheck -check-prefix=NORAW -strict-whitespace %s
 
 # Instructions are expected to be aligned if the instruction in hex is not too long.
 
 # CHECK:       0: c3                           |retq
-# CHECK-NEXT:  1: 48 8b 05 56 34 12 00         |movq|0x123456(%rip), %rax
-# CHECK-NEXT:  8: 48 b8 54 55 55 55 55 55 55 55|movabsq|$0x5555555555555554, %rax
-# CHECK-NEXT: 12: 8f ea 00 12 4c 02 40 00 00 00 00     |lwpval|$0x0, 0x40(%rdx,%rax), %r15d
-# CHECK-NEXT: 1d: 8f ea 00 12 04 25 f0 1c f0 1c 00 00 00 00    |lwpins|$0x0, 0x1cf01cf0, %r15d
-# CHECK-NEXT: 2b: ff ff                        |<unknown>
+# CHECK-NEXT:  1: 488b0556341200               |movq|0x123456(%rip), %rax
+# CHECK-NEXT:  8: 48b85455555555555555         |movabsq|$0x5555555555555554, %rax
+# CHECK-NEXT: 12: 8fea00124c024000000000       |lwpval|$0x0, 0x40(%rdx,%rax), %r15d
+# CHECK-NEXT: 1d: 8fea00120425f01cf01c00000000 |lwpins|$0x0, 0x1cf01cf0, %r15d
+# CHECK-NEXT: 2b: ffff                         |<unknown>
 
 # NORAW:       0:      |retq
 # NORAW-NEXT:  1:      |movq|0x123456(%rip), %rax
 # NORAW-NEXT:  8:      |movabsq|$0x5555555555555554, %rax
 # NORAW-NEXT: 12:      |lwpval|$0x0, 0x40(%rdx,%rax), %r15d
 # NORAW-NEXT: 1d:      |lwpins|$0x0, 0x1cf01cf0, %r15d
 # NORAW-NEXT: 2b:      |<unknown>
 
 .text
   retq
   movq 0x123456(%rip),%rax
   movabs $0x5555555555555554,%rax
   lwpval $0x0, 0x40(%rdx,%rax), %r15d
   lwpins $0x0, 0x1cf01cf0, %r15d
   .word 0xffff

llvm/test/tools/llvm-objdump/X86/elf-disassemble.test

 # ALL-NEXT:    Disassembly of section .writable:
 # ALL-EMPTY:
 # ALL-NEXT:    0000000000002000 <.writable>:
 # ALL-NEXT:           0: c3                            retq
 # ALL-EMPTY:
 # ALL-NEXT:    Disassembly of section .readonly:
 # ALL-EMPTY:
 # ALL-NEXT:    0000000000003000 <.readonly>:
-# ALL-NEXT:           0: 01 00                         addl    %eax, (%rax)
+# ALL-NEXT:           0: 0100                          addl    %eax, (%rax)
 # ALL-EMPTY:
 # ALL-NEXT:    Disassembly of section .nobits:
 # ALL-EMPTY:
 # ALL-NEXT:    0000000000004000 <.nobits>:
 # ALL-NEXT:    ...
 
 --- !ELF
 FileHeader:

llvm/tools/llvm-objdump/llvm-objdump.cpp

virtual void printInst(MCInstPrinter &IP, const MCInst *MI,
     if (SP && (PrintSource || PrintLines))
       SP->printSourceLine(OS, Address, ObjectFilename);
 
     size_t Start = OS.tell();
     if (!NoLeadingAddr)
       OS << format("%8" PRIx64 ":", Address.Address);
     if (!NoShowRawInsn) {
       OS << ' ';
+      if (STI.getTargetTriple().isX86())
+        dumpBytesNoSpace(Bytes, OS);
+      else
         dumpBytes(Bytes, OS);
     }
 
     // The output of printInst starts with a tab. Print some spaces so that
     // the tab has 1 column and advances to the target tab stop.
-    unsigned TabStop = NoShowRawInsn ? 16 : 40;
+    unsigned TabStop = NoShowRawInsn ? 16 : 32;
     unsigned Column = OS.tell() - Start;
     OS.indent(Column < TabStop - 1 ? TabStop - 1 - Column : 7 - Column % 8);
 
     if (MI) {
       // See MCInstPrinter::printInst. On targets where a PC relative immediate
       // is relative to the next instruction and the length of a MCInst is
       // difficult to measure (x86), this is the address of the next
       // instruction.