diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -236,6 +236,12 @@
 
   // Effectively disable jump table generation.
   setMinimumJumpTableEntries(INT_MAX);
+
+  // Jumps are expensive, compared to logic
+  setJumpIsExpensive();
+
+  // We can use any register for comparisons
+  setHasMultipleConditionRegisters();
 }
 
 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
--- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll
+++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
@@ -25,19 +25,19 @@
 ; RV32IFD-NEXT:    fld ft0, 0(sp)
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_0)
 ; RV32IFD-NEXT:    fld ft1, %lo(.LCPI1_0)(a0)
-; RV32IFD-NEXT:    flt.d a0, ft0, ft1
-; RV32IFD-NEXT:    bnez a0, .LBB1_3
-; RV32IFD-NEXT:  # %bb.1: # %entry
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_1)
-; RV32IFD-NEXT:    fld ft1, %lo(.LCPI1_1)(a0)
-; RV32IFD-NEXT:    flt.d a0, ft1, ft0
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    beqz a0, .LBB1_3
-; RV32IFD-NEXT:  # %bb.2: # %if.end
+; RV32IFD-NEXT:    fld ft2, %lo(.LCPI1_1)(a0)
+; RV32IFD-NEXT:    flt.d a0, ft0, ft1
+; RV32IFD-NEXT:    not a0, a0
+; RV32IFD-NEXT:    flt.d a1, ft2, ft0
+; RV32IFD-NEXT:    xori a1, a1, 1
+; RV32IFD-NEXT:    and a0, a0, a1
+; RV32IFD-NEXT:    bnez a0, .LBB1_2
+; RV32IFD-NEXT:  # %bb.1: # %if.then
+; RV32IFD-NEXT:    call abort
+; RV32IFD-NEXT:  .LBB1_2: # %if.end
 ; RV32IFD-NEXT:    mv a0, zero
 ; RV32IFD-NEXT:    call exit
-; RV32IFD-NEXT:  .LBB1_3: # %if.then
-; RV32IFD-NEXT:    call abort
 entry:
   %call = call double @test(double 2.000000e+00)
   %cmp = fcmp olt double %call, 2.400000e-01
diff --git a/llvm/test/CodeGen/RISCV/select-and.ll b/llvm/test/CodeGen/RISCV/select-and.ll
--- a/llvm/test/CodeGen/RISCV/select-and.ll
+++ b/llvm/test/CodeGen/RISCV/select-and.ll
@@ -10,34 +10,22 @@
 define signext i32 @select_of_and(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i32 signext %d) nounwind {
 ; RV32I-LABEL: select_of_and:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beqz a1, .LBB0_3
+; RV32I-NEXT:    and a1, a0, a1
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:    bnez a1, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    beqz a0, .LBB0_4
+; RV32I-NEXT:    mv a0, a3
 ; RV32I-NEXT:  .LBB0_2:
-; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB0_3:
-; RV32I-NEXT:    mv a2, a3
-; RV32I-NEXT:    bnez a0, .LBB0_2
-; RV32I-NEXT:  .LBB0_4:
-; RV32I-NEXT:    mv a2, a3
-; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: select_of_and:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    beqz a1, .LBB0_3
+; RV64I-NEXT:    and a1, a0, a1
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    bnez a1, .LBB0_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    beqz a0, .LBB0_4
+; RV64I-NEXT:    mv a0, a3
 ; RV64I-NEXT:  .LBB0_2:
-; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ret
-; RV64I-NEXT:  .LBB0_3:
-; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:    bnez a0, .LBB0_2
-; RV64I-NEXT:  .LBB0_4:
-; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
   %1 = and i1 %a, %b
   %2 = select i1 %1, i32 %c, i32 %d
@@ -52,15 +40,15 @@
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    beqz a0, .LBB1_3
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    beqz a1, .LBB1_3
-; RV32I-NEXT:  # %bb.2: # %if.then
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    addi a1, zero, 1
+; RV32I-NEXT:    bne a0, a1, .LBB1_2
+; RV32I-NEXT:  # %bb.1: # %if.then
 ; RV32I-NEXT:    call both
-; RV32I-NEXT:    j .LBB1_4
-; RV32I-NEXT:  .LBB1_3: # %if.else
+; RV32I-NEXT:    j .LBB1_3
+; RV32I-NEXT:  .LBB1_2: # %if.else
 ; RV32I-NEXT:    call neither
-; RV32I-NEXT:  .LBB1_4: # %if.end
+; RV32I-NEXT:  .LBB1_3: # %if.end
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
@@ -69,15 +57,15 @@
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
-; RV64I-NEXT:    beqz a0, .LBB1_3
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    beqz a1, .LBB1_3
-; RV64I-NEXT:  # %bb.2: # %if.then
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    addi a1, zero, 1
+; RV64I-NEXT:    bne a0, a1, .LBB1_2
+; RV64I-NEXT:  # %bb.1: # %if.then
 ; RV64I-NEXT:    call both
-; RV64I-NEXT:    j .LBB1_4
-; RV64I-NEXT:  .LBB1_3: # %if.else
+; RV64I-NEXT:    j .LBB1_3
+; RV64I-NEXT:  .LBB1_2: # %if.else
 ; RV64I-NEXT:    call neither
-; RV64I-NEXT:  .LBB1_4: # %if.end
+; RV64I-NEXT:  .LBB1_3: # %if.end
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/select-or.ll b/llvm/test/CodeGen/RISCV/select-or.ll
--- a/llvm/test/CodeGen/RISCV/select-or.ll
+++ b/llvm/test/CodeGen/RISCV/select-or.ll
@@ -10,36 +10,22 @@
 define signext i32 @select_of_or(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i32 signext %d) nounwind {
 ; RV32I-LABEL: select_of_or:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    mv a4, a2
-; RV32I-NEXT:    beqz a1, .LBB0_3
+; RV32I-NEXT:    or a1, a0, a1
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:    bnez a1, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    beqz a0, .LBB0_4
+; RV32I-NEXT:    mv a0, a3
 ; RV32I-NEXT:  .LBB0_2:
-; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB0_3:
-; RV32I-NEXT:    mv a4, a3
-; RV32I-NEXT:    bnez a0, .LBB0_2
-; RV32I-NEXT:  .LBB0_4:
-; RV32I-NEXT:    mv a2, a4
-; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: select_of_or:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    mv a4, a2
-; RV64I-NEXT:    beqz a1, .LBB0_3
+; RV64I-NEXT:    or a1, a0, a1
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    bnez a1, .LBB0_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    beqz a0, .LBB0_4
+; RV64I-NEXT:    mv a0, a3
 ; RV64I-NEXT:  .LBB0_2:
-; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:    ret
-; RV64I-NEXT:  .LBB0_3:
-; RV64I-NEXT:    mv a4, a3
-; RV64I-NEXT:    bnez a0, .LBB0_2
-; RV64I-NEXT:  .LBB0_4:
-; RV64I-NEXT:    mv a2, a4
-; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
   %1 = or i1 %a, %b
   %2 = select i1 %1, i32 %c, i32 %d
@@ -54,15 +40,15 @@
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    bnez a0, .LBB1_3
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    bnez a1, .LBB1_3
-; RV32I-NEXT:  # %bb.2: # %if.else
-; RV32I-NEXT:    call neither
-; RV32I-NEXT:    j .LBB1_4
-; RV32I-NEXT:  .LBB1_3: # %if.then
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    addi a1, zero, 1
+; RV32I-NEXT:    bne a0, a1, .LBB1_2
+; RV32I-NEXT:  # %bb.1: # %if.then
 ; RV32I-NEXT:    call either
-; RV32I-NEXT:  .LBB1_4: # %if.end
+; RV32I-NEXT:    j .LBB1_3
+; RV32I-NEXT:  .LBB1_2: # %if.else
+; RV32I-NEXT:    call neither
+; RV32I-NEXT:  .LBB1_3: # %if.end
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
@@ -71,15 +57,15 @@
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
-; RV64I-NEXT:    bnez a0, .LBB1_3
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    bnez a1, .LBB1_3
-; RV64I-NEXT:  # %bb.2: # %if.else
-; RV64I-NEXT:    call neither
-; RV64I-NEXT:    j .LBB1_4
-; RV64I-NEXT:  .LBB1_3: # %if.then
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    addi a1, zero, 1
+; RV64I-NEXT:    bne a0, a1, .LBB1_2
+; RV64I-NEXT:  # %bb.1: # %if.then
 ; RV64I-NEXT:    call either
-; RV64I-NEXT:  .LBB1_4: # %if.end
+; RV64I-NEXT:    j .LBB1_3
+; RV64I-NEXT:  .LBB1_2: # %if.else
+; RV64I-NEXT:    call neither
+; RV64I-NEXT:  .LBB1_3: # %if.end
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll b/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
--- a/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
+++ b/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
@@ -11,17 +11,16 @@
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a0, %hi(bytes)
 ; RV32I-NEXT:    lbu a1, %lo(bytes)(a0)
-; RV32I-NEXT:    addi a2, zero, 136
-; RV32I-NEXT:    bne a1, a2, .LBB0_3
-; RV32I-NEXT:  # %bb.1: # %entry
 ; RV32I-NEXT:    addi a0, a0, %lo(bytes)
 ; RV32I-NEXT:    lbu a0, 1(a0)
-; RV32I-NEXT:    addi a1, zero, 7
-; RV32I-NEXT:    bne a0, a1, .LBB0_3
-; RV32I-NEXT:  # %bb.2: # %if.end
+; RV32I-NEXT:    xori a1, a1, 136
+; RV32I-NEXT:    xori a0, a0, 7
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB0_2
+; RV32I-NEXT:  # %bb.1: # %if.end
 ; RV32I-NEXT:    mv a0, zero
 ; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB0_3: # %if.then
+; RV32I-NEXT:  .LBB0_2: # %if.then
 ; RV32I-NEXT:    addi a0, zero, 1
 ; RV32I-NEXT:    ret
 entry:
@@ -46,18 +45,18 @@
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a0, %hi(shorts)
 ; RV32I-NEXT:    lhu a1, %lo(shorts)(a0)
-; RV32I-NEXT:    lui a2, 16
-; RV32I-NEXT:    addi a2, a2, -120
-; RV32I-NEXT:    bne a1, a2, .LBB1_3
-; RV32I-NEXT:  # %bb.1: # %entry
 ; RV32I-NEXT:    addi a0, a0, %lo(shorts)
 ; RV32I-NEXT:    lhu a0, 2(a0)
-; RV32I-NEXT:    addi a1, zero, 7
-; RV32I-NEXT:    bne a0, a1, .LBB1_3
-; RV32I-NEXT:  # %bb.2: # %if.end
+; RV32I-NEXT:    lui a2, 16
+; RV32I-NEXT:    addi a2, a2, -120
+; RV32I-NEXT:    xor a1, a1, a2
+; RV32I-NEXT:    xori a0, a0, 7
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB1_2
+; RV32I-NEXT:  # %bb.1: # %if.end
 ; RV32I-NEXT:    mv a0, zero
 ; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB1_3: # %if.then
+; RV32I-NEXT:  .LBB1_2: # %if.then
 ; RV32I-NEXT:    addi a0, zero, 1
 ; RV32I-NEXT:    ret
 entry: