diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -116,6 +116,10 @@
   bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
     return VT.isScalarInteger();
   }
+  bool shouldNormalizeToSelectSequence(LLVMContext &Ctx,
+                                       EVT VT) const override {
+    return false;
+  }
 
   bool shouldInsertFencesForAtomic(const Instruction *I) const override {
     return isa<LoadInst>(I) || isa<StoreInst>(I);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -228,6 +228,9 @@
 
   // Effectively disable jump table generation.
   setMinimumJumpTableEntries(INT_MAX);
+
+  // Jumps are expensive, compared to logic
+  setJumpIsExpensive();
 }
 
 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
--- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll
+++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
@@ -26,20 +26,20 @@
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_0)
 ; RV32IFD-NEXT:    addi a0, a0, %lo(.LCPI1_0)
 ; RV32IFD-NEXT:    fld ft1, 0(a0)
-; RV32IFD-NEXT:    flt.d a0, ft0, ft1
-; RV32IFD-NEXT:    bnez a0, .LBB1_3
-; RV32IFD-NEXT:  # %bb.1: # %entry
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_1)
 ; RV32IFD-NEXT:    addi a0, a0, %lo(.LCPI1_1)
-; RV32IFD-NEXT:    fld ft1, 0(a0)
-; RV32IFD-NEXT:    flt.d a0, ft1, ft0
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    beqz a0, .LBB1_3
-; RV32IFD-NEXT:  # %bb.2: # %if.end
+; RV32IFD-NEXT:    fld ft2, 0(a0)
+; RV32IFD-NEXT:    flt.d a0, ft0, ft1
+; RV32IFD-NEXT:    not a0, a0
+; RV32IFD-NEXT:    flt.d a1, ft2, ft0
+; RV32IFD-NEXT:    xori a1, a1, 1
+; RV32IFD-NEXT:    and a0, a0, a1
+; RV32IFD-NEXT:    bnez a0, .LBB1_2
+; RV32IFD-NEXT:  # %bb.1: # %if.then
+; RV32IFD-NEXT:    call abort
+; RV32IFD-NEXT:  .LBB1_2: # %if.end
 ; RV32IFD-NEXT:    mv a0, zero
 ; RV32IFD-NEXT:    call exit
-; RV32IFD-NEXT:  .LBB1_3: # %if.then
-; RV32IFD-NEXT:    call abort
 entry:
   %call = call double @test(double 2.000000e+00)
   %cmp = fcmp olt double %call, 2.400000e-01
diff --git a/llvm/test/CodeGen/RISCV/select-or.ll b/llvm/test/CodeGen/RISCV/select-or.ll
--- a/llvm/test/CodeGen/RISCV/select-or.ll
+++ b/llvm/test/CodeGen/RISCV/select-or.ll
@@ -10,32 +10,28 @@
 define signext i32 @select_of_or(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
 ; RV32I-LABEL: select_of_or:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    mv a4, a0
-; RV32I-NEXT:    bne a2, a3, .LBB0_3
+; RV32I-NEXT:    xor a4, a0, a1
+; RV32I-NEXT:    seqz a4, a4
+; RV32I-NEXT:    xor a2, a2, a3
+; RV32I-NEXT:    seqz a2, a2
+; RV32I-NEXT:    or a2, a4, a2
+; RV32I-NEXT:    bnez a2, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    bne a0, a1, .LBB0_4
+; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:  .LBB0_2:
 ; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB0_3:
-; RV32I-NEXT:    mv a4, a1
-; RV32I-NEXT:    beq a0, a1, .LBB0_2
-; RV32I-NEXT:  .LBB0_4:
-; RV32I-NEXT:    mv a0, a4
-; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: select_of_or:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    mv a4, a0
-; RV64I-NEXT:    bne a2, a3, .LBB0_3
+; RV64I-NEXT:    xor a4, a0, a1
+; RV64I-NEXT:    seqz a4, a4
+; RV64I-NEXT:    xor a2, a2, a3
+; RV64I-NEXT:    seqz a2, a2
+; RV64I-NEXT:    or a2, a4, a2
+; RV64I-NEXT:    bnez a2, .LBB0_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    bne a0, a1, .LBB0_4
+; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:  .LBB0_2:
-; RV64I-NEXT:    ret
-; RV64I-NEXT:  .LBB0_3:
-; RV64I-NEXT:    mv a4, a1
-; RV64I-NEXT:    beq a0, a1, .LBB0_2
-; RV64I-NEXT:  .LBB0_4:
-; RV64I-NEXT:    mv a0, a4
 ; RV64I-NEXT:    ret
   %1 = icmp eq i32 %a, %b
   %2 = icmp eq i32 %c, %d
diff --git a/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll b/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
--- a/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
+++ b/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
@@ -11,17 +11,16 @@
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a0, %hi(bytes)
 ; RV32I-NEXT:    lbu a1, %lo(bytes)(a0)
-; RV32I-NEXT:    addi a2, zero, 136
-; RV32I-NEXT:    bne a1, a2, .LBB0_3
-; RV32I-NEXT:  # %bb.1: # %entry
 ; RV32I-NEXT:    addi a0, a0, %lo(bytes)
 ; RV32I-NEXT:    lbu a0, 1(a0)
-; RV32I-NEXT:    addi a1, zero, 7
-; RV32I-NEXT:    bne a0, a1, .LBB0_3
-; RV32I-NEXT:  # %bb.2: # %if.end
+; RV32I-NEXT:    xori a1, a1, 136
+; RV32I-NEXT:    xori a0, a0, 7
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB0_2
+; RV32I-NEXT:  # %bb.1: # %if.end
 ; RV32I-NEXT:    mv a0, zero
 ; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB0_3: # %if.then
+; RV32I-NEXT:  .LBB0_2: # %if.then
 ; RV32I-NEXT:    addi a0, zero, 1
 ; RV32I-NEXT:    ret
 entry:
@@ -46,18 +45,18 @@
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a0, %hi(shorts)
 ; RV32I-NEXT:    lhu a1, %lo(shorts)(a0)
-; RV32I-NEXT:    lui a2, 16
-; RV32I-NEXT:    addi a2, a2, -120
-; RV32I-NEXT:    bne a1, a2, .LBB1_3
-; RV32I-NEXT:  # %bb.1: # %entry
 ; RV32I-NEXT:    addi a0, a0, %lo(shorts)
 ; RV32I-NEXT:    lhu a0, 2(a0)
-; RV32I-NEXT:    addi a1, zero, 7
-; RV32I-NEXT:    bne a0, a1, .LBB1_3
-; RV32I-NEXT:  # %bb.2: # %if.end
+; RV32I-NEXT:    lui a2, 16
+; RV32I-NEXT:    addi a2, a2, -120
+; RV32I-NEXT:    xor a1, a1, a2
+; RV32I-NEXT:    xori a0, a0, 7
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB1_2
+; RV32I-NEXT:  # %bb.1: # %if.end
 ; RV32I-NEXT:    mv a0, zero
 ; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB1_3: # %if.then
+; RV32I-NEXT:  .LBB1_2: # %if.then
 ; RV32I-NEXT:    addi a0, zero, 1
 ; RV32I-NEXT:    ret
 entry: