diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp --- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp +++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp @@ -1452,17 +1452,26 @@ unsigned Opc = LoLoop.getStartOpcode(); MachineOperand &Count = LoLoop.getLoopStartOperand(); - MachineInstrBuilder MIB = - BuildMI(*MBB, InsertPt, Start->getDebugLoc(), TII->get(Opc)); + // A DLS lr, lr we needn't emit + MachineInstr* NewStart; + if (Opc == ARM::t2DLS && Count.isReg() && Count.getReg() == ARM::LR) { + LLVM_DEBUG(dbgs() << "ARM Loops: Didn't insert start: DLS lr, lr"); + NewStart = nullptr; + } else { + MachineInstrBuilder MIB = + BuildMI(*MBB, InsertPt, Start->getDebugLoc(), TII->get(Opc)); - MIB.addDef(ARM::LR); - MIB.add(Count); - if (!isDo(Start)) - MIB.add(Start->getOperand(1)); + MIB.addDef(ARM::LR); + MIB.add(Count); + if (!isDo(Start)) + MIB.add(Start->getOperand(1)); + + LLVM_DEBUG(dbgs() << "ARM Loops: Inserted start: " << *MIB); + NewStart = &*MIB; + } LoLoop.ToRemove.insert(Start); - LLVM_DEBUG(dbgs() << "ARM Loops: Inserted start: " << *MIB); - return &*MIB; + return NewStart; } void ARMLowOverheadLoops::ConvertVPTBlocks(LowOverheadLoop &LoLoop) { @@ -1644,7 +1653,8 @@ RevertLoopEnd(LoLoop.End, RevertLoopDec(LoLoop.Dec)); } else { LoLoop.Start = ExpandLoopStart(LoLoop); - RemoveDeadBranch(LoLoop.Start); + if (LoLoop.Start) + RemoveDeadBranch(LoLoop.Start); LoLoop.End = ExpandLoopEnd(LoLoop); RemoveDeadBranch(LoLoop.End); if (LoLoop.IsTailPredicationLegal()) diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll @@ -17,7 +17,6 @@ ; CHECK-NEXT: sub.w r12, r12, #4 ; CHECK-NEXT: add.w lr, lr, r12, lsr #2 ; CHECK-NEXT: mov.w r12, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB0_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: and r4, r12, #15 @@ -109,7 +108,6 @@ ; CHECK-NEXT: movs r4, #1 ; CHECK-NEXT: add.w lr, r4, lr, lsr #2 ; CHECK-NEXT: movs r4, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB1_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: and r5, r4, #15 @@ -212,7 +210,6 @@ ; CHECK-NEXT: movs r4, #1 ; CHECK-NEXT: add.w lr, r4, lr, lsr #2 ; CHECK-NEXT: movs r4, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB2_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r12 @@ -311,7 +308,6 @@ ; CHECK-NEXT: movs r4, #1 ; CHECK-NEXT: add.w lr, r4, lr, lsr #2 ; CHECK-NEXT: movs r4, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB3_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r12 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/constbound.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/constbound.ll --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/constbound.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/constbound.ll @@ -10,7 +10,6 @@ ; CHECK-NEXT: adr r2, .LCPI0_0 ; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: mov.w r2, #500 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vdup.32 q1, r2 ; CHECK-NEXT: movs r1, #0 ; CHECK-NEXT: movs r2, #0 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/ctlz-non-zeros.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/ctlz-non-zeros.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/ctlz-non-zeros.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/ctlz-non-zeros.mir @@ -171,7 +171,6 @@ ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8) - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: bb.2.loop.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) @@ -279,7 +278,6 @@ ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4 ; CHECK: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8) - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: bb.2.loop.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) @@ -386,7 +384,6 @@ ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4 ; CHECK: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8) - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: bb.2.loop.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir @@ -147,7 +147,6 @@ ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0 ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.bb9: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir @@ -123,7 +123,6 @@ ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll @@ -226,7 +226,6 @@ ; CHECK-NEXT: subs r3, #4 ; CHECK-NEXT: add.w lr, r12, r3, lsr #2 ; CHECK-NEXT: movs r3, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB1_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r2 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir @@ -113,7 +113,6 @@ ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir @@ -121,7 +121,6 @@ ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir @@ -114,7 +114,6 @@ ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir @@ -151,7 +151,6 @@ ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir @@ -151,7 +151,6 @@ ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir @@ -151,7 +151,6 @@ ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain-store.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain-store.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain-store.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain-store.mir @@ -143,7 +143,6 @@ ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: t2STRi12 renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.iter.addr) - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: bb.1.do.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) @@ -248,7 +247,6 @@ ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: t2STRi12 renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.iter.addr) - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: bb.1.do.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll @@ -18,7 +18,7 @@ ; CHECK: t2CMPri renamable $lr, 0 ; CHECK: tBcc %bb.4 ; CHECK: bb.2.while.body.preheader: -; CHECK: $lr = t2DLS killed renamable $lr +; CHECK-NOT: $lr = t2DLS killed renamable $lr ; CHECK: bb.3.while.body: ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.3 define void @ne_and_guard(i1 zeroext %t1, i1 zeroext %t2, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) { @@ -51,7 +51,7 @@ ; CHECK: t2CMPri renamable $lr, 0 ; CHECK: tBcc %bb.4 ; CHECK: bb.2.while.body.preheader: -; CHECK: $lr = t2DLS killed renamable $lr +; CHECK-NOT: $lr = t2DLS killed renamable $lr ; CHECK: bb.3.while.body: ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.3 define void @ne_preheader(i1 zeroext %t1, i1 zeroext %t2, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) { @@ -86,7 +86,7 @@ ; CHECK: t2CMPri renamable $lr, 0 ; CHECK: tBcc %bb.4 ; CHECK: bb.2.while.body.preheader: -; CHECK: $lr = t2DLS killed renamable $lr +; CHECK-NOT: $lr = t2DLS killed renamable $lr ; CHECK: bb.3.while.body: ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.3 define void @eq_preheader(i1 zeroext %t1, i1 zeroext %t2, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) { @@ -121,7 +121,7 @@ ; CHECK: t2CMPri renamable $lr, 0 ; CHECK: tBcc %bb.4 ; CHECK: bb.2.while.body.preheader: -; CHECK: $lr = t2DLS killed renamable $lr +; CHECK-NOT: $lr = t2DLS killed renamable $lr ; CHECK: bb.3.while.body: ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.3 define void @ne_prepreheader(i1 zeroext %t1, i1 zeroext %t2, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) { diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir @@ -159,7 +159,6 @@ ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool) - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 ; CHECK: $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1 ; CHECK: bb.2.vector.body: @@ -292,7 +291,6 @@ ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $lr = t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool) - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 ; CHECK: renamable $r2, dead $cpsr = tLSRri killed renamable $r2, 2, 14 /* CC::al */, $noreg ; CHECK: $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir @@ -321,7 +321,6 @@ ; CHECK: liveins: $lr, $r4, $r12 ; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r1 = IMPLICIT_DEF - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.10.for.body.i57: ; CHECK: successors: %bb.10(0x7c000000), %bb.11(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r4, $r12 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/minloop.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/minloop.ll --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/minloop.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/minloop.ll @@ -26,7 +26,6 @@ ; CHECK-NEXT: subs r7, #4 ; CHECK-NEXT: add.w lr, r6, r7, lsr #2 ; CHECK-NEXT: movs r6, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: movs r7, #4 ; CHECK-NEXT: .LBB0_5: @ %while.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir @@ -124,7 +124,6 @@ ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: bb.2.vector.body: diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir @@ -123,7 +123,6 @@ ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir @@ -263,7 +263,6 @@ ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.8 (%ir-block.65): ; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll @@ -94,7 +94,6 @@ ; CHECK-NEXT: mov r5, r1 ; CHECK-NEXT: add.w lr, r6, r7, lsr #2 ; CHECK-NEXT: mov r6, r2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB0_12: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q0, [r5], #16 @@ -313,7 +312,6 @@ ; CHECK-NEXT: mov r5, r1 ; CHECK-NEXT: add.w lr, r6, r7, lsr #2 ; CHECK-NEXT: mov r6, r2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB1_12: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q0, [r5], #16 @@ -532,7 +530,6 @@ ; CHECK-NEXT: mov r5, r1 ; CHECK-NEXT: add.w lr, r6, r7, lsr #2 ; CHECK-NEXT: mov r6, r2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB2_12: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q0, [r5], #16 @@ -682,7 +679,6 @@ ; CHECK-NEXT: mov r5, r1 ; CHECK-NEXT: add.w lr, r6, r7, lsr #2 ; CHECK-NEXT: mov r6, r2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB3_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q0, [r5], #16 @@ -890,7 +886,6 @@ ; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: add.w lr, r5, r6, lsr #2 ; CHECK-NEXT: mov r5, r1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: mov r6, r2 ; CHECK-NEXT: .LBB4_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -909,7 +904,6 @@ ; CHECK-NEXT: add.w r0, r0, r12, lsl #2 ; CHECK-NEXT: add.w r1, r1, r12, lsl #2 ; CHECK-NEXT: add.w r2, r2, r12, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB4_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldr r3, [r0], #4 @@ -995,7 +989,6 @@ ; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: add.w lr, r5, r6, lsr #2 ; CHECK-NEXT: mov r5, r1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: mov r6, r2 ; CHECK-NEXT: .LBB5_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -1024,7 +1017,6 @@ ; CHECK-NEXT: add.w r0, r0, r12, lsl #1 ; CHECK-NEXT: add.w r1, r1, r12, lsl #1 ; CHECK-NEXT: add.w r2, r2, r12, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB5_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldr.16 s0, [r1] @@ -1112,7 +1104,6 @@ ; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: add.w lr, r5, r6, lsr #2 ; CHECK-NEXT: mov r5, r1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: mov r6, r2 ; CHECK-NEXT: .LBB6_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -1141,7 +1132,6 @@ ; CHECK-NEXT: add.w r0, r0, r12, lsl #1 ; CHECK-NEXT: add.w r1, r1, r12, lsl #1 ; CHECK-NEXT: add.w r2, r2, r12, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB6_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldr.16 s0, [r1] @@ -1229,7 +1219,6 @@ ; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: add.w lr, r5, r6, lsr #2 ; CHECK-NEXT: mov r5, r1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: mov r6, r2 ; CHECK-NEXT: .LBB7_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -1258,7 +1247,6 @@ ; CHECK-NEXT: add.w r0, r0, r12, lsl #1 ; CHECK-NEXT: add.w r1, r1, r12, lsl #1 ; CHECK-NEXT: add.w r2, r2, r12, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB7_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldr.16 s0, [r1] @@ -1346,7 +1334,6 @@ ; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: add.w lr, r5, r6, lsr #2 ; CHECK-NEXT: mov r5, r1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: mov r6, r2 ; CHECK-NEXT: .LBB8_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -1380,7 +1367,6 @@ ; CHECK-NEXT: add.w r0, r0, r12, lsl #1 ; CHECK-NEXT: add.w r1, r1, r12, lsl #1 ; CHECK-NEXT: add.w r2, r2, r12, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB8_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldrsh r3, [r1], #2 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll @@ -17,7 +17,6 @@ ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 ; CHECK-NEXT: movs r3, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB0_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r2 @@ -93,7 +92,6 @@ ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 ; CHECK-NEXT: movs r3, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB1_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r2 @@ -169,7 +167,6 @@ ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 ; CHECK-NEXT: movs r3, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB2_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r2 @@ -245,7 +242,6 @@ ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 ; CHECK-NEXT: movs r3, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB3_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r2 @@ -321,7 +317,6 @@ ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 ; CHECK-NEXT: movs r3, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB4_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r2 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir @@ -131,7 +131,6 @@ ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 35, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2LSRri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 34, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir @@ -118,7 +118,6 @@ ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 15, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 16, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll @@ -74,7 +74,6 @@ ; CHECK-NEXT: sub.w r12, r3, #8 ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #3 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB1_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.16 r2 @@ -147,7 +146,6 @@ ; CHECK-NEXT: sub.w r12, r3, #16 ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #4 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB2_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.8 r2 @@ -217,7 +215,6 @@ ; CHECK-NEXT: sub.w r12, r3, #8 ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #3 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB3_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.16 r2 @@ -289,7 +286,6 @@ ; CHECK-NEXT: sub.w r12, r3, #16 ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #4 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB4_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.8 r2 @@ -359,7 +355,6 @@ ; CHECK-NEXT: sub.w r12, r3, #8 ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #3 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB5_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.16 r2 @@ -431,7 +426,6 @@ ; CHECK-NEXT: mov r5, r1 ; CHECK-NEXT: add.w lr, r3, r6, lsr #2 ; CHECK-NEXT: mov r3, r2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB6_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r3 @@ -453,7 +447,6 @@ ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r6, lsr #2 ; CHECK-NEXT: vmov.32 q0[0], r12 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB6_5: @ %vector.body46 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r2 @@ -558,7 +551,6 @@ ; CHECK-NEXT: add.w lr, r4, r3, lsr #3 ; CHECK-NEXT: mov r3, r0 ; CHECK-NEXT: mov r4, r1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB7_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.16 r2 @@ -677,7 +669,6 @@ ; CHECK-NEXT: bic r0, r0, #3 ; CHECK-NEXT: subs r0, #4 ; CHECK-NEXT: add.w lr, r12, r0, lsr #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB8_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r2 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remat-vctp.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remat-vctp.ll --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remat-vctp.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remat-vctp.ll @@ -106,7 +106,6 @@ ; CHECK-NEXT: add.w lr, r5, #3 ; CHECK-NEXT: movs r5, #1 ; CHECK-NEXT: add.w lr, r5, lr, lsr #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB1_1: @ %bb6 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r12 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir @@ -210,7 +210,6 @@ ; CHECK: liveins: $lr, $r3, $r12 ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r1 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.8.while.body: ; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000) ; CHECK: liveins: $lr, $r0, $r1 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir @@ -200,7 +200,6 @@ ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg, debug-location !28 ; CHECK: renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14 /* CC::al */, $noreg, debug-location !28 ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg, debug-location !28 - ; CHECK: $lr = t2DLS killed renamable $lr, debug-location !28 ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredload.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredload.ll --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredload.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredload.ll @@ -59,7 +59,6 @@ ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 ; CHECK-NEXT: mov.w r12, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB1_1: @ %do.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r2 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir @@ -301,7 +301,6 @@ ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.7.for.body: ; CHECK: successors: %bb.7(0x7c000000), %bb.8(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir @@ -2980,7 +2980,6 @@ ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.while.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir @@ -291,7 +291,6 @@ ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.bb9: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 @@ -434,7 +433,6 @@ ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.bb9: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 @@ -577,7 +575,6 @@ ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.bb9: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir @@ -137,7 +137,6 @@ ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from constant-pool) ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll @@ -17,7 +17,6 @@ ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 ; CHECK-NEXT: movs r3, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB0_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r2 @@ -94,7 +93,6 @@ ; CHECK-NEXT: subs r1, #4 ; CHECK-NEXT: add.w lr, r3, r1, lsr #2 ; CHECK-NEXT: movs r1, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB1_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r2 @@ -165,7 +163,6 @@ ; CHECK-NEXT: subs r1, #4 ; CHECK-NEXT: add.w lr, r3, r1, lsr #2 ; CHECK-NEXT: movs r1, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB2_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r2 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir @@ -349,7 +349,6 @@ ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 @@ -481,7 +480,6 @@ ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 @@ -956,7 +954,6 @@ ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: dead renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2 @@ -1254,7 +1251,6 @@ ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2 - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2 (align 4): ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir @@ -137,7 +137,6 @@ ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 2, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from constant-pool) ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 diff --git a/llvm/test/CodeGen/Thumb2/active_lane_mask.ll b/llvm/test/CodeGen/Thumb2/active_lane_mask.ll --- a/llvm/test/CodeGen/Thumb2/active_lane_mask.ll +++ b/llvm/test/CodeGen/Thumb2/active_lane_mask.ll @@ -424,7 +424,6 @@ ; CHECK-NEXT: vldrw.u32 q2, [r2] ; CHECK-NEXT: add.w lr, r3, r0, lsr #1 ; CHECK-NEXT: mov.w r8, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vand q1, q1, q0 ; CHECK-NEXT: .LBB4_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 diff --git a/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll b/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll --- a/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll +++ b/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll @@ -7,7 +7,6 @@ ; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #500 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: movs r1, #0 ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: .LBB0_1: @ %for.body diff --git a/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll b/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll --- a/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll +++ b/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll @@ -703,7 +703,6 @@ ; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: ldrd lr, r12, [sp, #16] ; CHECK-NEXT: lsl.w r3, r12, #1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB14_1: @ %for.body.us ; CHECK-NEXT: @ =>This Loop Header: Depth=1 ; CHECK-NEXT: @ Child Loop BB14_2 Depth 2 diff --git a/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll b/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll --- a/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll +++ b/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll @@ -703,7 +703,6 @@ ; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: ldrd lr, r12, [sp, #16] ; CHECK-NEXT: lsl.w r3, r12, #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB14_1: @ %for.body.us ; CHECK-NEXT: @ =>This Loop Header: Depth=1 ; CHECK-NEXT: @ Child Loop BB14_2 Depth 2 diff --git a/llvm/test/CodeGen/Thumb2/mve-fp16convertloops.ll b/llvm/test/CodeGen/Thumb2/mve-fp16convertloops.ll --- a/llvm/test/CodeGen/Thumb2/mve-fp16convertloops.ll +++ b/llvm/test/CodeGen/Thumb2/mve-fp16convertloops.ll @@ -8,7 +8,6 @@ ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #256 ; CHECK-NEXT: adr r2, .LCPI0_0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: .LBB0_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -54,7 +53,6 @@ ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #128 ; CHECK-NEXT: adr r2, .LCPI1_0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: .LBB1_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -104,7 +102,6 @@ ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #64 ; CHECK-NEXT: adr r2, .LCPI2_0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: .LBB2_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -162,7 +159,6 @@ ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #256 ; CHECK-NEXT: adr r2, .LCPI3_0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: .LBB3_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -208,7 +204,6 @@ ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #128 ; CHECK-NEXT: adr r2, .LCPI4_0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: .LBB4_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -258,7 +253,6 @@ ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #64 ; CHECK-NEXT: adr r2, .LCPI5_0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: .LBB5_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -316,7 +310,6 @@ ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #256 ; CHECK-NEXT: adr r2, .LCPI6_0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: .LBB6_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -364,7 +357,6 @@ ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #128 ; CHECK-NEXT: adr r2, .LCPI7_0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: .LBB7_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -417,7 +409,6 @@ ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #64 ; CHECK-NEXT: adr r2, .LCPI8_0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: .LBB8_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -480,7 +471,6 @@ ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #128 ; CHECK-NEXT: adr r2, .LCPI9_0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: .LBB9_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -536,7 +526,6 @@ ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #128 ; CHECK-NEXT: adr r2, .LCPI10_0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: .LBB10_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 diff --git a/llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll b/llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll --- a/llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll +++ b/llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll @@ -701,7 +701,6 @@ ; CHECK-NEXT: subs r2, #4 ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r2, lsr #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB22_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q0, [r1], #16 @@ -747,7 +746,6 @@ ; CHECK-NEXT: subs r2, #4 ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r2, lsr #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB23_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q0, [r1], #16 diff --git a/llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll b/llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll --- a/llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll +++ b/llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll @@ -713,7 +713,6 @@ ; CHECK-NEXT: sub.w lr, r9, r7 ; CHECK-NEXT: mla r3, r0, r7, r1 ; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: add.w r5, r0, r5, lsl #1 ; CHECK-NEXT: add.w r3, r6, r3, lsl #1 ; CHECK-NEXT: .LBB10_14: @ %for.body8.us.us diff --git a/llvm/test/CodeGen/Thumb2/mve-gather-scatter-ptr-address.ll b/llvm/test/CodeGen/Thumb2/mve-gather-scatter-ptr-address.ll --- a/llvm/test/CodeGen/Thumb2/mve-gather-scatter-ptr-address.ll +++ b/llvm/test/CodeGen/Thumb2/mve-gather-scatter-ptr-address.ll @@ -9,7 +9,6 @@ ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #249 ; CHECK-NEXT: adr r3, .LCPI0_0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r3] ; CHECK-NEXT: .LBB0_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -60,7 +59,6 @@ ; CHECK-NEXT: mov.w lr, #249 ; CHECK-NEXT: adr r1, .LCPI1_0 ; CHECK-NEXT: adr r3, .LCPI1_1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r3] ; CHECK-NEXT: vldrw.u32 q1, [r1] ; CHECK-NEXT: .LBB1_1: @ %vector.body @@ -117,7 +115,6 @@ ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #249 ; CHECK-NEXT: adr r3, .LCPI2_0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r3] ; CHECK-NEXT: .LBB2_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -173,7 +170,6 @@ ; CHECK-NEXT: mov.w lr, #249 ; CHECK-NEXT: adr.w r12, .LCPI3_0 ; CHECK-NEXT: adr r3, .LCPI3_1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r3] ; CHECK-NEXT: vldrw.u32 q1, [r12] ; CHECK-NEXT: .LBB3_1: @ %vector.body @@ -239,7 +235,6 @@ ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #249 ; CHECK-NEXT: adr r3, .LCPI4_0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r3] ; CHECK-NEXT: .LBB4_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -303,7 +298,6 @@ ; CHECK-NEXT: mov.w lr, #249 ; CHECK-NEXT: adr.w r12, .LCPI5_0 ; CHECK-NEXT: adr r3, .LCPI5_1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r3] ; CHECK-NEXT: vldrw.u32 q1, [r12] ; CHECK-NEXT: .LBB5_1: @ %vector.body @@ -385,7 +379,6 @@ ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #249 ; CHECK-NEXT: adr r3, .LCPI6_0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r3] ; CHECK-NEXT: .LBB6_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -436,7 +429,6 @@ ; CHECK-NEXT: mov.w lr, #249 ; CHECK-NEXT: adr r1, .LCPI7_0 ; CHECK-NEXT: adr r3, .LCPI7_1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r3] ; CHECK-NEXT: vldrw.u32 q1, [r1] ; CHECK-NEXT: .LBB7_1: @ %vector.body @@ -496,7 +488,6 @@ ; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: adr r3, .LCPI8_0 ; CHECK-NEXT: vmov.f16 r2, s0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r3] ; CHECK-NEXT: .LBB8_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -556,7 +547,6 @@ ; CHECK-NEXT: vmov.f16 r1, s0 ; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: adr r2, .LCPI9_1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q1, [r2] ; CHECK-NEXT: .LBB9_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 diff --git a/llvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll b/llvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll --- a/llvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll +++ b/llvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll @@ -13,7 +13,6 @@ ; CHECK-NEXT: movw lr, #1250 ; CHECK-NEXT: vadd.i32 q0, q0, r1 ; CHECK-NEXT: adds r1, r3, #4 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB0_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r3 @@ -85,7 +84,6 @@ ; CHECK-NEXT: vmov.i32 q2, #0x0 ; CHECK-NEXT: vmov.i32 q0, #0x14 ; CHECK-NEXT: movw lr, #1250 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB1_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r3 @@ -160,7 +158,6 @@ ; CHECK-NEXT: vmov.i32 q2, #0x3 ; CHECK-NEXT: vadd.i32 q0, q0, r1 ; CHECK-NEXT: adds r1, r3, #4 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB2_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vctp.32 r3 diff --git a/llvm/test/CodeGen/Thumb2/mve-nounrolledremainder.ll b/llvm/test/CodeGen/Thumb2/mve-nounrolledremainder.ll --- a/llvm/test/CodeGen/Thumb2/mve-nounrolledremainder.ll +++ b/llvm/test/CodeGen/Thumb2/mve-nounrolledremainder.ll @@ -163,7 +163,6 @@ ; CHECK-NEXT: add.w r12, r0, r6, lsl #1 ; CHECK-NEXT: add.w lr, r5, r7, lsr #3 ; CHECK-NEXT: add.w r7, r2, r6, lsl #1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: and r5, r3, #7 ; CHECK-NEXT: .LBB1_8: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 diff --git a/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll b/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll --- a/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll +++ b/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll @@ -12,7 +12,6 @@ ; CHECK-NEXT: cmp r1, #1 ; CHECK-NEXT: blt .LBB0_4 ; CHECK-NEXT: @ %bb.1: @ %for.body.preheader -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: mov r1, r0 ; CHECK-NEXT: movs r0, #0 ; CHECK-NEXT: .LBB0_2: @ %for.body @@ -285,7 +284,6 @@ ; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: add.w lr, r5, r6, lsr #3 ; CHECK-NEXT: mov r5, r1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: mov r6, r2 ; CHECK-NEXT: .LBB2_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -309,7 +307,6 @@ ; CHECK-NEXT: add.w r0, r0, r12, lsl #2 ; CHECK-NEXT: add.w r1, r1, r12, lsl #2 ; CHECK-NEXT: add.w r2, r2, r12, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB2_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldr s0, [r0] diff --git a/llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll b/llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll --- a/llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll +++ b/llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll @@ -24,7 +24,6 @@ ; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: add.w lr, r5, r6, lsr #2 ; CHECK-NEXT: mov r5, r1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: mov r6, r2 ; CHECK-NEXT: .LBB0_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -43,7 +42,6 @@ ; CHECK-NEXT: add.w r0, r0, r12, lsl #2 ; CHECK-NEXT: add.w r1, r1, r12, lsl #2 ; CHECK-NEXT: add.w r2, r2, r12, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB0_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldr s0, [r0] @@ -136,7 +134,6 @@ ; CHECK-NEXT: vldrw.u32 q0, [r4] ; CHECK-NEXT: add.w lr, lr, r12, lsr #2 ; CHECK-NEXT: sub.w r12, r3, #1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: vdup.32 q1, r12 ; CHECK-NEXT: .LBB1_2: @ %vector.body diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll b/llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll --- a/llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll +++ b/llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll @@ -16,7 +16,6 @@ ; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: add.w lr, r3, r1, lsr #2 ; CHECK-NEXT: rsbs r1, r2, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB0_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r0] @@ -73,7 +72,6 @@ ; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: add.w lr, r3, r1, lsr #3 ; CHECK-NEXT: rsbs r1, r2, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB1_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrh.u16 q1, [r0] @@ -130,7 +128,6 @@ ; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: add.w lr, r3, r1, lsr #4 ; CHECK-NEXT: rsbs r1, r2, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB2_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrb.u8 q1, [r0] @@ -186,7 +183,6 @@ ; CHECK-NEXT: movs r2, #1 ; CHECK-NEXT: add.w lr, r2, r1, lsr #2 ; CHECK-NEXT: vmov r1, s0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: eor r2, r1, #-2147483648 ; CHECK-NEXT: .LBB3_2: @ %vector.body @@ -246,7 +242,6 @@ ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r1, lsr #3 ; CHECK-NEXT: vmov.f16 r1, s0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: .LBB4_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -309,7 +304,6 @@ ; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: add.w lr, r3, r1, lsr #2 ; CHECK-NEXT: rsbs r1, r2, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB5_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r0] @@ -366,7 +360,6 @@ ; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: add.w lr, r3, r1, lsr #3 ; CHECK-NEXT: rsbs r1, r2, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB6_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrh.u16 q1, [r0] @@ -423,7 +416,6 @@ ; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: add.w lr, r3, r1, lsr #4 ; CHECK-NEXT: rsbs r1, r2, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB7_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrb.u8 q1, [r0] @@ -479,7 +471,6 @@ ; CHECK-NEXT: movs r2, #1 ; CHECK-NEXT: add.w lr, r2, r1, lsr #2 ; CHECK-NEXT: vmov r1, s0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: eor r2, r1, #-2147483648 ; CHECK-NEXT: .LBB8_2: @ %vector.body @@ -539,7 +530,6 @@ ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r1, lsr #3 ; CHECK-NEXT: vmov.f16 r1, s0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: .LBB9_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 diff --git a/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll b/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll --- a/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll +++ b/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll @@ -34,7 +34,6 @@ ; CHECK-NEXT: add.w r11, r2, r3, lsl #2 ; CHECK-NEXT: add.w r10, r1, r3, lsl #2 ; CHECK-NEXT: add.w r12, r0, r3, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r4] ; CHECK-NEXT: vmvn.i32 q1, #0x80000000 ; CHECK-NEXT: .LBB0_4: @ %vector.body @@ -106,7 +105,6 @@ ; CHECK-NEXT: .LBB0_6: @ %for.body.preheader ; CHECK-NEXT: sub.w lr, r3, r7 ; CHECK-NEXT: mov.w r0, #-1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: mov.w r1, #-2147483648 ; CHECK-NEXT: mvn r2, #-2147483648 ; CHECK-NEXT: .LBB0_7: @ %for.body @@ -251,7 +249,6 @@ ; CHECK-NEXT: add.w r11, r2, r3, lsl #2 ; CHECK-NEXT: add.w r9, r1, r3, lsl #2 ; CHECK-NEXT: add.w r12, r0, r3, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q1, [r4] ; CHECK-NEXT: .LBB1_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -383,7 +380,6 @@ ; CHECK-NEXT: .LBB1_6: @ %for.body.preheader21 ; CHECK-NEXT: sub.w lr, r3, r7 ; CHECK-NEXT: mov.w r0, #-1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: mov.w r3, #-2147483648 ; CHECK-NEXT: mvn r2, #-2147483648 ; CHECK-NEXT: .LBB1_7: @ %for.body @@ -523,7 +519,6 @@ ; CHECK-NEXT: add.w lr, r6, r7, lsr #2 ; CHECK-NEXT: adr r6, .LCPI2_0 ; CHECK-NEXT: subs r7, r3, #1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q0, [r6] ; CHECK-NEXT: mov.w r9, #0 ; CHECK-NEXT: vdup.32 q1, r7 @@ -747,7 +742,6 @@ ; CHECK-NEXT: add.w r11, r1, r5, lsl #2 ; CHECK-NEXT: add.w lr, r6, r7, lsr #1 ; CHECK-NEXT: add.w r12, r0, r5, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB3_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldrd r4, r7, [r0] @@ -788,7 +782,6 @@ ; CHECK-NEXT: beq .LBB3_8 ; CHECK-NEXT: .LBB3_6: @ %for.body.preheader ; CHECK-NEXT: sub.w lr, r3, r7 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB3_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldr r0, [r12], #4 @@ -904,7 +897,6 @@ ; CHECK-NEXT: add.w r9, r1, r8, lsl #2 ; CHECK-NEXT: add.w lr, r6, r7, lsr #2 ; CHECK-NEXT: add.w r12, r0, r8, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB4_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16 @@ -977,7 +969,6 @@ ; CHECK-NEXT: beq .LBB4_8 ; CHECK-NEXT: .LBB4_6: @ %for.body.preheader21 ; CHECK-NEXT: sub.w lr, r3, r8 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB4_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldr r0, [r12], #4 @@ -1094,7 +1085,6 @@ ; CHECK-NEXT: add.w lr, r4, r6, lsr #2 ; CHECK-NEXT: add.w r4, r2, r5, lsl #1 ; CHECK-NEXT: add.w r6, r1, r5, lsl #1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB5_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrh.s32 q0, [r0], #8 @@ -1109,7 +1099,6 @@ ; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: .LBB5_6: @ %for.body.preheader21 ; CHECK-NEXT: sub.w lr, r3, r5 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB5_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldrsh r0, [r12], #2 @@ -1222,7 +1211,6 @@ ; CHECK-NEXT: add.w lr, r4, r6, lsr #3 ; CHECK-NEXT: add.w r4, r2, r5, lsl #1 ; CHECK-NEXT: add.w r6, r1, r5, lsl #1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB6_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrh.s32 q0, [r0, #8] @@ -1242,7 +1230,6 @@ ; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: .LBB6_6: @ %for.body.preheader21 ; CHECK-NEXT: sub.w lr, r3, r5 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB6_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldrsh r0, [r12], #2 @@ -1354,7 +1341,6 @@ ; CHECK-NEXT: add.w lr, r4, r6, lsr #3 ; CHECK-NEXT: add.w r4, r2, r5, lsl #1 ; CHECK-NEXT: add.w r6, r1, r5, lsl #1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB7_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrh.u16 q0, [r0], #16 @@ -1371,7 +1357,6 @@ ; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: .LBB7_6: @ %for.body.preheader21 ; CHECK-NEXT: sub.w lr, r3, r5 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB7_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldrsh r0, [r12], #2 @@ -1490,7 +1475,6 @@ ; CHECK-NEXT: vldrw.u32 q0, [r4] ; CHECK-NEXT: add.w lr, lr, r12, lsr #2 ; CHECK-NEXT: sub.w r12, r3, #1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: vdup.32 q1, r12 ; CHECK-NEXT: .LBB8_2: @ %vector.body @@ -1581,7 +1565,6 @@ ; CHECK-NEXT: movs r5, #0 ; CHECK-NEXT: add.w lr, lr, r12, lsr #3 ; CHECK-NEXT: sub.w r12, r3, #1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q4, [r4] ; CHECK-NEXT: vdup.32 q1, r12 ; CHECK-NEXT: vmov.i8 q2, #0x0 @@ -1747,7 +1730,6 @@ ; CHECK-NEXT: vmov.i8 q2, #0x0 ; CHECK-NEXT: add.w lr, lr, r12, lsr #3 ; CHECK-NEXT: sub.w r12, r3, #1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q4, [r4] ; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: vdup.32 q1, r12 @@ -1884,7 +1866,6 @@ ; CHECK-NEXT: add.w lr, r4, r6, lsr #2 ; CHECK-NEXT: add.w r4, r2, r5, lsl #1 ; CHECK-NEXT: add.w r6, r1, r5, lsl #1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB11_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrh.u32 q0, [r0], #8 @@ -1900,7 +1881,6 @@ ; CHECK-NEXT: .LBB11_6: @ %for.body.preheader21 ; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: movw r0, #65535 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB11_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldrh r1, [r12], #2 @@ -2013,7 +1993,6 @@ ; CHECK-NEXT: add.w lr, r4, r6, lsr #3 ; CHECK-NEXT: add.w r4, r2, r5, lsl #1 ; CHECK-NEXT: add.w r6, r1, r5, lsl #1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB12_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrh.u32 q0, [r0, #8] @@ -2034,7 +2013,6 @@ ; CHECK-NEXT: .LBB12_6: @ %for.body.preheader21 ; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: movw r0, #65535 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB12_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldrh r1, [r12], #2 @@ -2152,7 +2130,6 @@ ; CHECK-NEXT: add.w lr, r4, r6, lsr #2 ; CHECK-NEXT: adds r4, r2, r5 ; CHECK-NEXT: adds r6, r1, r5 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB13_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrb.s32 q2, [r0], #4 @@ -2169,7 +2146,6 @@ ; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: .LBB13_6: @ %for.body.preheader21 ; CHECK-NEXT: sub.w lr, r3, r5 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB13_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldrsb r0, [r12], #1 @@ -2281,7 +2257,6 @@ ; CHECK-NEXT: add.w lr, r4, r6, lsr #3 ; CHECK-NEXT: adds r4, r2, r5 ; CHECK-NEXT: adds r6, r1, r5 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB14_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrb.s16 q0, [r0], #8 @@ -2296,7 +2271,6 @@ ; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: .LBB14_6: @ %for.body.preheader23 ; CHECK-NEXT: sub.w lr, r3, r5 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB14_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldrsb r0, [r12], #1 @@ -2409,7 +2383,6 @@ ; CHECK-NEXT: add.w lr, r4, r6, lsr #4 ; CHECK-NEXT: adds r4, r2, r5 ; CHECK-NEXT: adds r6, r1, r5 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB15_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrb.s16 q0, [r0, #8] @@ -2429,7 +2402,6 @@ ; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: .LBB15_6: @ %for.body.preheader23 ; CHECK-NEXT: sub.w lr, r3, r5 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB15_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldrsb r0, [r12], #1 @@ -2541,7 +2513,6 @@ ; CHECK-NEXT: add.w lr, r4, r6, lsr #4 ; CHECK-NEXT: adds r4, r2, r5 ; CHECK-NEXT: adds r6, r1, r5 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB16_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrb.u8 q0, [r0], #16 @@ -2558,7 +2529,6 @@ ; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: .LBB16_6: @ %for.body.preheader23 ; CHECK-NEXT: sub.w lr, r3, r5 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB16_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldrsb r0, [r12], #1 @@ -2680,7 +2650,6 @@ ; CHECK-NEXT: vmov.i8 q2, #0x0 ; CHECK-NEXT: add.w lr, lr, r12, lsr #3 ; CHECK-NEXT: sub.w r12, r3, #1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vldrw.u32 q4, [r4] ; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: vdup.32 q1, r12 @@ -2800,7 +2769,6 @@ ; CHECK-NEXT: vmov.i8 q2, #0x0 ; CHECK-NEXT: add.w lr, lr, r12, lsr #4 ; CHECK-NEXT: sub.w r12, r3, #1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vstrw.32 q0, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vldrw.u32 q0, [r4] ; CHECK-NEXT: adr r4, .LCPI18_2 @@ -3100,7 +3068,6 @@ ; CHECK-NEXT: vmov.i8 q2, #0x0 ; CHECK-NEXT: add.w lr, lr, r12, lsr #4 ; CHECK-NEXT: sub.w r12, r3, #1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vstrw.32 q0, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vldrw.u32 q0, [r4] ; CHECK-NEXT: adr r4, .LCPI19_2 @@ -3315,7 +3282,6 @@ ; CHECK-NEXT: add.w lr, r4, r6, lsr #3 ; CHECK-NEXT: adds r4, r2, r5 ; CHECK-NEXT: adds r6, r1, r5 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB20_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrb.u16 q0, [r0], #8 @@ -3330,7 +3296,6 @@ ; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: .LBB20_6: @ %for.body.preheader23 ; CHECK-NEXT: sub.w lr, r3, r5 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB20_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldrb r0, [r12], #1 @@ -3443,7 +3408,6 @@ ; CHECK-NEXT: add.w lr, r4, r6, lsr #4 ; CHECK-NEXT: adds r4, r2, r5 ; CHECK-NEXT: adds r6, r1, r5 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB21_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrb.u16 q0, [r0, #8] @@ -3465,7 +3429,6 @@ ; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: .LBB21_6: @ %for.body.preheader23 ; CHECK-NEXT: sub.w lr, r3, r5 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB21_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldrb r0, [r12], #1 diff --git a/llvm/test/CodeGen/Thumb2/mve-shifts-scalar.ll b/llvm/test/CodeGen/Thumb2/mve-shifts-scalar.ll --- a/llvm/test/CodeGen/Thumb2/mve-shifts-scalar.ll +++ b/llvm/test/CodeGen/Thumb2/mve-shifts-scalar.ll @@ -10,7 +10,6 @@ ; CHECK-NEXT: sub.w r12, r3, #4 ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB0_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16 @@ -54,7 +53,6 @@ ; CHECK-NEXT: sub.w r12, r3, #4 ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB1_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q0, [r0], #8 @@ -98,7 +96,6 @@ ; CHECK-NEXT: sub.w r12, r3, #4 ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB2_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q0, [r0], #4 @@ -143,7 +140,6 @@ ; CHECK-NEXT: sub.w r12, r3, #4 ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB3_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16 @@ -188,7 +184,6 @@ ; CHECK-NEXT: sub.w r12, r3, #4 ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB4_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q0, [r0], #8 @@ -233,7 +228,6 @@ ; CHECK-NEXT: sub.w r12, r3, #4 ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB5_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q0, [r0], #4 @@ -278,7 +272,6 @@ ; CHECK-NEXT: sub.w r12, r3, #4 ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB6_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16 @@ -323,7 +316,6 @@ ; CHECK-NEXT: sub.w r12, r3, #4 ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB7_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q0, [r0], #8 @@ -368,7 +360,6 @@ ; CHECK-NEXT: sub.w r12, r3, #4 ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB8_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q0, [r0], #4 diff --git a/llvm/test/CodeGen/Thumb2/mve-vabdus.ll b/llvm/test/CodeGen/Thumb2/mve-vabdus.ll --- a/llvm/test/CodeGen/Thumb2/mve-vabdus.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vabdus.ll @@ -487,7 +487,6 @@ ; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #64 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB6_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrb.s32 q0, [r1, #12] @@ -548,7 +547,6 @@ ; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #128 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB7_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrh.s32 q0, [r1, #8] @@ -604,7 +602,6 @@ ; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: mov.w lr, #256 ; CHECK-NEXT: mov.w r12, #1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: .LBB8_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -700,7 +697,6 @@ ; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #64 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB9_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrb.u32 q0, [r1, #12] @@ -761,7 +757,6 @@ ; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #128 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB10_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrh.u32 q0, [r1, #8] @@ -817,7 +812,6 @@ ; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: mov.w lr, #256 ; CHECK-NEXT: vmov.i64 q0, #0xffffffff -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: .LBB11_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 diff --git a/llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll b/llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll --- a/llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll @@ -25,7 +25,6 @@ ; CHECK-NEXT: subs r0, r3, #4 ; CHECK-NEXT: add.w lr, r2, r0, lsr #2 ; CHECK-NEXT: movs r0, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: mov r2, r12 ; CHECK-NEXT: .LBB0_5: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -39,7 +38,6 @@ ; CHECK-NEXT: .LBB0_7: @ %for.body.preheader1 ; CHECK-NEXT: sub.w lr, r1, r3 ; CHECK-NEXT: add.w r2, r12, r3, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB0_8: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldr r1, [r2], #4 @@ -115,7 +113,6 @@ ; CHECK-NEXT: sub.w r3, r12, #4 ; CHECK-NEXT: add.w lr, r2, r3, lsr #2 ; CHECK-NEXT: mov r2, r0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB1_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r2], #16 @@ -134,7 +131,6 @@ ; CHECK-NEXT: .LBB1_6: @ %for.body.preheader1 ; CHECK-NEXT: sub.w lr, r1, r12 ; CHECK-NEXT: add.w r0, r0, r12, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB1_7: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldr r1, [r0], #4 @@ -215,7 +211,6 @@ ; CHECK-NEXT: vmov.i8 q0, #0xff ; CHECK-NEXT: add.w lr, r2, r12, lsr #2 ; CHECK-NEXT: mov r2, r0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB2_5: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r2], #16 @@ -234,7 +229,6 @@ ; CHECK-NEXT: .LBB2_7: @ %for.body.preheader1 ; CHECK-NEXT: sub.w lr, r1, r3 ; CHECK-NEXT: add.w r0, r0, r3, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB2_8: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldr r1, [r0], #4 @@ -315,7 +309,6 @@ ; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: add.w lr, r2, r12, lsr #2 ; CHECK-NEXT: mov r2, r0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB3_5: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r2], #16 @@ -334,7 +327,6 @@ ; CHECK-NEXT: .LBB3_7: @ %for.body.preheader1 ; CHECK-NEXT: sub.w lr, r1, r3 ; CHECK-NEXT: add.w r0, r0, r3, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB3_8: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldr r1, [r0], #4 @@ -415,7 +407,6 @@ ; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: add.w lr, r2, r12, lsr #2 ; CHECK-NEXT: mov r2, r0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB4_5: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r2], #16 @@ -434,7 +425,6 @@ ; CHECK-NEXT: .LBB4_7: @ %for.body.preheader1 ; CHECK-NEXT: sub.w lr, r1, r3 ; CHECK-NEXT: add.w r0, r0, r3, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB4_8: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldr r1, [r0], #4 @@ -515,7 +505,6 @@ ; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 ; CHECK-NEXT: mov r3, r0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB5_5: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r3], #16 @@ -530,7 +519,6 @@ ; CHECK-NEXT: .LBB5_7: @ %for.body.preheader1 ; CHECK-NEXT: sub.w lr, r1, r2 ; CHECK-NEXT: add.w r0, r0, r2, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB5_8: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldr s2, [r0] @@ -616,7 +604,6 @@ ; CHECK-NEXT: vmov.f32 q0, #1.000000e+00 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 ; CHECK-NEXT: mov r3, r0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB6_5: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r3], #16 @@ -631,7 +618,6 @@ ; CHECK-NEXT: .LBB6_7: @ %for.body.preheader1 ; CHECK-NEXT: sub.w lr, r1, r2 ; CHECK-NEXT: add.w r0, r0, r2, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB6_8: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldr s2, [r0] @@ -713,7 +699,6 @@ ; CHECK-NEXT: vmvn.i32 q0, #0x80000000 ; CHECK-NEXT: add.w lr, r2, r12, lsr #2 ; CHECK-NEXT: mov r2, r0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB7_5: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r2], #16 @@ -727,7 +712,6 @@ ; CHECK-NEXT: .LBB7_7: @ %for.body.preheader1 ; CHECK-NEXT: sub.w lr, r1, r3 ; CHECK-NEXT: add.w r0, r0, r3, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB7_8: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldr r1, [r0], #4 @@ -811,7 +795,6 @@ ; CHECK-NEXT: subs r0, r3, #4 ; CHECK-NEXT: add.w lr, r2, r0, lsr #2 ; CHECK-NEXT: mvn r0, #-2147483648 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: mov r2, r12 ; CHECK-NEXT: .LBB8_5: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -825,7 +808,6 @@ ; CHECK-NEXT: .LBB8_7: @ %for.body.preheader1 ; CHECK-NEXT: sub.w lr, r1, r3 ; CHECK-NEXT: add.w r2, r12, r3, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB8_8: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldr r1, [r2], #4 @@ -909,7 +891,6 @@ ; CHECK-NEXT: vmov.i32 q0, #0x80000000 ; CHECK-NEXT: add.w lr, r2, r12, lsr #2 ; CHECK-NEXT: mov r2, r0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB9_5: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r2], #16 @@ -923,7 +904,6 @@ ; CHECK-NEXT: .LBB9_7: @ %for.body.preheader1 ; CHECK-NEXT: sub.w lr, r1, r3 ; CHECK-NEXT: add.w r0, r0, r3, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB9_8: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldr r1, [r0], #4 @@ -1007,7 +987,6 @@ ; CHECK-NEXT: subs r0, r3, #4 ; CHECK-NEXT: add.w lr, r2, r0, lsr #2 ; CHECK-NEXT: mov.w r0, #-2147483648 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: mov r2, r12 ; CHECK-NEXT: .LBB10_5: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -1021,7 +1000,6 @@ ; CHECK-NEXT: .LBB10_7: @ %for.body.preheader1 ; CHECK-NEXT: sub.w lr, r1, r3 ; CHECK-NEXT: add.w r2, r12, r3, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB10_8: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldr r1, [r2], #4 @@ -1105,7 +1083,6 @@ ; CHECK-NEXT: vmov.i8 q0, #0xff ; CHECK-NEXT: add.w lr, r2, r12, lsr #2 ; CHECK-NEXT: mov r2, r0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB11_5: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r2], #16 @@ -1119,7 +1096,6 @@ ; CHECK-NEXT: .LBB11_7: @ %for.body.preheader1 ; CHECK-NEXT: sub.w lr, r1, r3 ; CHECK-NEXT: add.w r0, r0, r3, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB11_8: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldr r1, [r0], #4 @@ -1203,7 +1179,6 @@ ; CHECK-NEXT: subs r0, r3, #4 ; CHECK-NEXT: add.w lr, r2, r0, lsr #2 ; CHECK-NEXT: mov.w r0, #-1 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: mov r2, r12 ; CHECK-NEXT: .LBB12_5: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -1217,7 +1192,6 @@ ; CHECK-NEXT: .LBB12_7: @ %for.body.preheader1 ; CHECK-NEXT: sub.w lr, r1, r3 ; CHECK-NEXT: add.w r2, r12, r3, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB12_8: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldr r1, [r2], #4 @@ -1301,7 +1275,6 @@ ; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: add.w lr, r2, r12, lsr #2 ; CHECK-NEXT: mov r2, r0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB13_5: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r2], #16 @@ -1315,7 +1288,6 @@ ; CHECK-NEXT: .LBB13_7: @ %for.body.preheader1 ; CHECK-NEXT: sub.w lr, r1, r3 ; CHECK-NEXT: add.w r0, r0, r3, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB13_8: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldr r1, [r0], #4 @@ -1399,7 +1371,6 @@ ; CHECK-NEXT: subs r0, r3, #4 ; CHECK-NEXT: add.w lr, r2, r0, lsr #2 ; CHECK-NEXT: movs r0, #0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: mov r2, r12 ; CHECK-NEXT: .LBB14_5: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -1413,7 +1384,6 @@ ; CHECK-NEXT: .LBB14_7: @ %for.body.preheader1 ; CHECK-NEXT: sub.w lr, r1, r3 ; CHECK-NEXT: add.w r2, r12, r3, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB14_8: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldr r1, [r2], #4 @@ -1497,7 +1467,6 @@ ; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 ; CHECK-NEXT: mov r3, r0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB15_5: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r3], #16 @@ -1513,7 +1482,6 @@ ; CHECK-NEXT: .LBB15_7: @ %for.body.preheader1 ; CHECK-NEXT: sub.w lr, r1, r2 ; CHECK-NEXT: add.w r0, r0, r2, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB15_8: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldmia r0!, {s2} @@ -1602,7 +1570,6 @@ ; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2 ; CHECK-NEXT: mov r3, r0 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB16_5: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r3], #16 @@ -1618,7 +1585,6 @@ ; CHECK-NEXT: .LBB16_7: @ %for.body.preheader1 ; CHECK-NEXT: sub.w lr, r1, r2 ; CHECK-NEXT: add.w r0, r0, r2, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB16_8: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldmia r0!, {s2} diff --git a/llvm/test/CodeGen/Thumb2/mve-vldshuffle.ll b/llvm/test/CodeGen/Thumb2/mve-vldshuffle.ll --- a/llvm/test/CodeGen/Thumb2/mve-vldshuffle.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vldshuffle.ll @@ -25,7 +25,6 @@ ; CHECK-NEXT: add.w r12, r1, r4, lsl #1 ; CHECK-NEXT: add.w lr, r5, r3, lsr #3 ; CHECK-NEXT: add.w r3, r0, r4, lsl #2 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: and r5, r2, #7 ; CHECK-NEXT: .LBB0_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 @@ -155,7 +154,6 @@ ; CHECK-NEXT: add.w r12, r1, r4, lsl #2 ; CHECK-NEXT: add.w lr, r5, r3, lsr #2 ; CHECK-NEXT: add.w r3, r0, r4, lsl #3 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: and r5, r2, #3 ; CHECK-NEXT: .LBB1_4: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 diff --git a/llvm/test/CodeGen/Thumb2/mve-vldst4.ll b/llvm/test/CodeGen/Thumb2/mve-vldst4.ll --- a/llvm/test/CodeGen/Thumb2/mve-vldst4.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vldst4.ll @@ -21,7 +21,6 @@ ; CHECK-NEXT: sub.w r12, r3, #8 ; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: add.w lr, r3, r12, lsr #3 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB0_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrh.u16 q5, [r0, #32] diff --git a/llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll b/llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll --- a/llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll @@ -200,7 +200,6 @@ ; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #64 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB8_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrb.u8 q0, [r0], #16 @@ -245,7 +244,6 @@ ; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #128 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB9_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrh.u16 q0, [r0], #16 @@ -290,7 +288,6 @@ ; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mov.w lr, #256 -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB10_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16 diff --git a/llvm/test/Transforms/HardwareLoops/ARM/calls-codegen.ll b/llvm/test/Transforms/HardwareLoops/ARM/calls-codegen.ll --- a/llvm/test/Transforms/HardwareLoops/ARM/calls-codegen.ll +++ b/llvm/test/Transforms/HardwareLoops/ARM/calls-codegen.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: test_target_specific: ; CHECK: mov.w lr, #50 -; CHECK: dls lr, lr +; CHECK-NOT: dls lr, lr ; CHECK-NOT: mov lr, ; CHECK: [[LOOP_HEADER:\.LBB[0-9_]+]]: ; CHECK: le lr, [[LOOP_HEADER]] @@ -32,7 +32,7 @@ ; CHECK-LABEL: test_fabs: ; CHECK: mov.w lr, #100 -; CHECK: dls lr, lr +; CHECK-NOT: dls lr, lr ; CHECK-NOT: mov lr, ; CHECK: [[LOOP_HEADER:\.LBB[0-9_]+]]: ; CHECK-NOT: bl diff --git a/llvm/test/Transforms/HardwareLoops/ARM/simple-do.ll b/llvm/test/Transforms/HardwareLoops/ARM/simple-do.ll --- a/llvm/test/Transforms/HardwareLoops/ARM/simple-do.ll +++ b/llvm/test/Transforms/HardwareLoops/ARM/simple-do.ll @@ -109,7 +109,8 @@ ; CHECK-LLC: do_inc2: ; CHECK-LLC-NOT: mov lr, -; CHECK-LLC: dls lr, {{.*}} +; CHECK-LLC: add.w lr, +; CHECK-LLC-NOT: dls lr, ; CHECK-LLC-NOT: mov lr, ; CHECK-LLC: [[LOOP_HEADER:\.LBB[0-9._]+]]: ; CHECK-LLC: le lr, [[LOOP_HEADER]] @@ -162,7 +163,8 @@ ; CHECK-LLC: do_dec2 ; CHECK-LLC-NOT: mov lr, -; CHECK-LLC: dls lr, {{.*}} +; CHECK-LLC: add.w lr, +; CHECK-LLC-NOT: dls lr, ; CHECK-LLC-NOT: mov lr, ; CHECK-LLC: [[LOOP_HEADER:\.LBB[0-9_]+]]: ; CHECK-LLC: le lr, [[LOOP_HEADER]] diff --git a/llvm/test/Transforms/HardwareLoops/ARM/structure.ll b/llvm/test/Transforms/HardwareLoops/ARM/structure.ll --- a/llvm/test/Transforms/HardwareLoops/ARM/structure.ll +++ b/llvm/test/Transforms/HardwareLoops/ARM/structure.ll @@ -395,7 +395,6 @@ ; CHECK-UNROLL-NEXT: [[PROLOGUE:.LBB[0-9_]+]]: ; CHECK-UNROLL: le lr, [[PROLOGUE]] ; CHECK-UNROLL-NEXT: [[PROLOGUE_EXIT:.LBB[0-9_]+]]: -; CHECK-UNROLL: dls lr, lr ; CHECK-UNROLL: [[BODY:.LBB[0-9_]+]]: ; CHECK-UNROLL: le lr, [[BODY]] ; CHECK-UNROLL-NOT: b