diff --git a/llvm/lib/Target/VE/VEAsmPrinter.cpp b/llvm/lib/Target/VE/VEAsmPrinter.cpp --- a/llvm/lib/Target/VE/VEAsmPrinter.cpp +++ b/llvm/lib/Target/VE/VEAsmPrinter.cpp @@ -88,9 +88,12 @@ static void emitBSIC(MCStreamer &OutStreamer, MCOperand &R1, MCOperand &R2, const MCSubtargetInfo &STI) { MCInst BSICInst; - BSICInst.setOpcode(VE::BSIC); + BSICInst.setOpcode(VE::BSICrii); BSICInst.addOperand(R1); BSICInst.addOperand(R2); + MCOperand czero = MCOperand::createImm(0); + BSICInst.addOperand(czero); + BSICInst.addOperand(czero); OutStreamer.emitInstruction(BSICInst, STI); } diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp b/llvm/lib/Target/VE/VEInstrInfo.cpp --- a/llvm/lib/Target/VE/VEInstrInfo.cpp +++ b/llvm/lib/Target/VE/VEInstrInfo.cpp @@ -68,25 +68,38 @@ llvm_unreachable("Invalid cond code"); } -// Treat br.l [BCR AT] as unconditional branch +// Treat br.l [BRCF AT] as unconditional branch static bool isUncondBranchOpcode(int Opc) { - return Opc == VE::BCRLa || Opc == VE::BCRWa || - Opc == VE::BCRDa || Opc == VE::BCRSa; + return Opc == VE::BRCFLa || Opc == VE::BRCFWa || + Opc == VE::BRCFLa_nt || Opc == VE::BRCFWa_nt || + Opc == VE::BRCFLa_t || Opc == VE::BRCFWa_t || + Opc == VE::BRCFDa || Opc == VE::BRCFSa || + Opc == VE::BRCFDa_nt || Opc == VE::BRCFSa_nt || + Opc == VE::BRCFDa_t || Opc == VE::BRCFSa_t; } static bool isCondBranchOpcode(int Opc) { - return Opc == VE::BCRLrr || Opc == VE::BCRLir || - Opc == VE::BCRLrm0 || Opc == VE::BCRLrm1 || - Opc == VE::BCRLim0 || Opc == VE::BCRLim1 || - Opc == VE::BCRWrr || Opc == VE::BCRWir || - Opc == VE::BCRWrm0 || Opc == VE::BCRWrm1 || - Opc == VE::BCRWim0 || Opc == VE::BCRWim1 || - Opc == VE::BCRDrr || Opc == VE::BCRDir || - Opc == VE::BCRDrm0 || Opc == VE::BCRDrm1 || - Opc == VE::BCRDim0 || Opc == VE::BCRDim1 || - Opc == VE::BCRSrr || Opc == VE::BCRSir || - Opc == VE::BCRSrm0 || Opc == VE::BCRSrm1 || - Opc == VE::BCRSim0 || Opc == VE::BCRSim1; + return Opc == VE::BRCFLrr || Opc == VE::BRCFLir || + Opc == VE::BRCFLrr_nt || Opc == VE::BRCFLir_nt || + Opc == VE::BRCFLrr_t || Opc == VE::BRCFLir_t || + Opc == VE::BRCFWrr || Opc == VE::BRCFWir || + Opc == VE::BRCFWrr_nt || Opc == VE::BRCFWir_nt || + Opc == VE::BRCFWrr_t || Opc == VE::BRCFWir_t || + Opc == VE::BRCFDrr || Opc == VE::BRCFDir || + Opc == VE::BRCFDrr_nt || Opc == VE::BRCFDir_nt || + Opc == VE::BRCFDrr_t || Opc == VE::BRCFDir_t || + Opc == VE::BRCFSrr || Opc == VE::BRCFSir || + Opc == VE::BRCFSrr_nt || Opc == VE::BRCFSir_nt || + Opc == VE::BRCFSrr_t || Opc == VE::BRCFSir_t; +} + +static bool isIndirectBranchOpcode(int Opc) { + return Opc == VE::BCFLari || Opc == VE::BCFLari || + Opc == VE::BCFLari_nt || Opc == VE::BCFLari_nt || + Opc == VE::BCFLari_t || Opc == VE::BCFLari_t || + Opc == VE::BCFLari || Opc == VE::BCFLari || + Opc == VE::BCFLari_nt || Opc == VE::BCFLari_nt || + Opc == VE::BCFLari_t || Opc == VE::BCFLari_t; } static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, @@ -165,14 +178,14 @@ return false; } - // TODO ...likewise if it ends with an indirect branch followed by an unconditional + // ...likewise if it ends with an indirect branch followed by an unconditional // branch. - // if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { - // I = LastInst; - // if (AllowModify) - // I->eraseFromParent(); - // return true; - // } + if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { + I = LastInst; + if (AllowModify) + I->eraseFromParent(); + return true; + } // Otherwise, can't handle this. return true; @@ -190,13 +203,13 @@ if (Cond.empty()) { // Uncondition branch assert(!FBB && "Unconditional branch with multiple successors!"); - BuildMI(&MBB, DL, get(VE::BCRLa)) + BuildMI(&MBB, DL, get(VE::BRCFLa_t)) .addMBB(TBB); return 1; } // Conditional branch - // (BCRir CC sy sz addr) + // (BRCFir CC sy sz addr) assert(Cond[0].isImm() && Cond[2].isReg() && "not implemented"); unsigned opc[2]; @@ -206,19 +219,19 @@ unsigned Reg = Cond[2].getReg(); if (IsIntegerCC(Cond[0].getImm())) { if (TRI->getRegSizeInBits(Reg, MRI) == 32) { - opc[0] = VE::BCRWir; - opc[1] = VE::BCRWrr; + opc[0] = VE::BRCFWir; + opc[1] = VE::BRCFWrr; } else { - opc[0] = VE::BCRLir; - opc[1] = VE::BCRLrr; + opc[0] = VE::BRCFLir; + opc[1] = VE::BRCFLrr; } } else { if (TRI->getRegSizeInBits(Reg, MRI) == 32) { - opc[0] = VE::BCRSir; - opc[1] = VE::BCRSrr; + opc[0] = VE::BRCFSir; + opc[1] = VE::BRCFSrr; } else { - opc[0] = VE::BCRDir; - opc[1] = VE::BCRDrr; + opc[0] = VE::BRCFDir; + opc[1] = VE::BRCFDrr; } } if (Cond[1].isImm()) { @@ -238,7 +251,7 @@ if (!FBB) return 1; - BuildMI(&MBB, DL, get(VE::BCRLa)) + BuildMI(&MBB, DL, get(VE::BRCFLa_t)) .addMBB(FBB); return 2; } @@ -488,7 +501,7 @@ // Next, add the true and fallthrough blocks as its successors. BB->addSuccessor(syscallMBB); BB->addSuccessor(sinkMBB); - BuildMI(BB, dl, TII.get(VE::BCRLrr)) + BuildMI(BB, dl, TII.get(VE::BRCFLrr_t)) .addImm(VECC::CC_IGE) .addReg(VE::SX11) // %sp .addReg(VE::SX8) // %sl diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td --- a/llvm/lib/Target/VE/VEInstrInfo.td +++ b/llvm/lib/Target/VE/VEInstrInfo.td @@ -185,6 +185,24 @@ return CurDAG->getTargetConstant(cc, SDLoc(N), MVT::i32); }]>; +def icond2ccSwap : SDNodeXFormget()) { + default: llvm_unreachable("Unknown integer condition code!"); + case ISD::SETEQ: cc = VECC::CC_IEQ; break; + case ISD::SETNE: cc = VECC::CC_INE; break; + case ISD::SETLT: cc = VECC::CC_IG; break; + case ISD::SETGT: cc = VECC::CC_IL; break; + case ISD::SETLE: cc = VECC::CC_IGE; break; + case ISD::SETGE: cc = VECC::CC_ILE; break; + case ISD::SETULT: cc = VECC::CC_IG; break; + case ISD::SETULE: cc = VECC::CC_IGE; break; + case ISD::SETUGT: cc = VECC::CC_IL; break; + case ISD::SETUGE: cc = VECC::CC_ILE; break; + } + return CurDAG->getTargetConstant(cc, SDLoc(N), MVT::i32); +}]>; + def fcond2cc : SDNodeXFormget()) { @@ -215,6 +233,36 @@ return CurDAG->getTargetConstant(cc, SDLoc(N), MVT::i32); }]>; +def fcond2ccSwap : SDNodeXFormget()) { + default: llvm_unreachable("Unknown float condition code!"); + case ISD::SETFALSE: cc = VECC::CC_AF; break; + case ISD::SETEQ: + case ISD::SETOEQ: cc = VECC::CC_EQ; break; + case ISD::SETNE: + case ISD::SETONE: cc = VECC::CC_NE; break; + case ISD::SETLT: + case ISD::SETOLT: cc = VECC::CC_G; break; + case ISD::SETGT: + case ISD::SETOGT: cc = VECC::CC_L; break; + case ISD::SETLE: + case ISD::SETOLE: cc = VECC::CC_GE; break; + case ISD::SETGE: + case ISD::SETOGE: cc = VECC::CC_LE; break; + case ISD::SETO: cc = VECC::CC_NUM; break; + case ISD::SETUO: cc = VECC::CC_NAN; break; + case ISD::SETUEQ: cc = VECC::CC_EQNAN; break; + case ISD::SETUNE: cc = VECC::CC_NENAN; break; + case ISD::SETULT: cc = VECC::CC_GNAN; break; + case ISD::SETUGT: cc = VECC::CC_LNAN; break; + case ISD::SETULE: cc = VECC::CC_GENAN; break; + case ISD::SETUGE: cc = VECC::CC_LENAN; break; + case ISD::SETTRUE: cc = VECC::CC_AT; break; + } + return CurDAG->getTargetConstant(cc, SDLoc(N), MVT::i32); +}]>; + // Addressing modes. def ADDRri : ComplexPattern; @@ -252,6 +300,7 @@ // ASX format: // MEMrri, MEMrii, MEMzri, MEMzii // AS format: +// MEMriASX, MEMziASX : simple AS format // well be added later. def ADDRrri : ComplexPattern; @@ -296,6 +345,26 @@ let MIOperandInfo = (ops i32imm /* = 0 */, i32imm, i32imm); let ParserMatchClass = VEMEMziiAsmOperand; } +// AS assembly instrcution format: +def VEMEMriAsmOperand : AsmOperandClass { + let Name = "MEMri"; + let ParserMethod = "parseMEMAsOperand"; +} +def VEMEMziAsmOperand : AsmOperandClass { + let Name = "MEMzi"; + let ParserMethod = "parseMEMAsOperand"; +} +// AS generic assembly instruction format: +def MEMriASX : Operand { + let PrintMethod = "printMemASOperandASX"; + let MIOperandInfo = (ops ptr_rc, i32imm); + let ParserMatchClass = VEMEMriAsmOperand; +} +def MEMziASX : Operand { + let PrintMethod = "printMemASOperandASX"; + let MIOperandInfo = (ops i32imm /* = 0 */, i32imm); + let ParserMatchClass = VEMEMziAsmOperand; +} // Branch targets have OtherVT type. def brtarget32 : Operand { @@ -580,67 +649,62 @@ !strconcat(opcStr, " $sx, $sy")>; } -// Branch multiclass -let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in -multiclass BCRm opc, - RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> { - def rr : CF< - opc, (outs), - (ins CCOp:$cf, RC:$sy, RC:$sz, brtarget32:$imm32), - !strconcat(opcStr, " $sy, $sz, $imm32")> { - let cy = 1; - let cz = 1; - let hasSideEffects = 0; - } - def ir : CF< - opc, (outs), - (ins CCOp:$cf, immOp:$sy, RC:$sz, brtarget32:$imm32), - !strconcat(opcStr, " $sy, $sz, $imm32")> { - let cy = 0; - let cz = 1; - let hasSideEffects = 0; - } - def rm0 : CF< - opc, (outs), (ins CCOp:$cf, RC:$sy, immOp2:$sz, brtarget32:$imm32), - !strconcat(opcStr, " $sy, (${sz})0, $imm32"), []> { - let cy = 1; - let cz = 0; - let sz{6} = 1; - let hasSideEffects = 0; - } - def rm1 : CF< - opc, (outs), (ins CCOp:$cf, RC:$sy, immOp2:$sz, brtarget32:$imm32), - !strconcat(opcStr, " $sy, (${sz})1, $imm32"), []> { - let cy = 1; - let cz = 0; - let hasSideEffects = 0; - } - def im0 : CF< - opc, (outs), (ins CCOp:$cf, immOp:$sy, immOp2:$sz, brtarget32:$imm32), - !strconcat(opcStr, " $sy, (${sz})0, $imm32"), []> { - let cy = 0; - let cz = 0; - let sz{6} = 1; - let hasSideEffects = 0; - } - def im1 : CF< - opc, (outs), (ins CCOp:$cf, immOp:$sy, immOp2:$sz, brtarget32:$imm32), - !strconcat(opcStr, " $sy, (${sz})1, $imm32"), []> { - let cy = 0; - let cz = 0; - let hasSideEffects = 0; - } - def a : CF< - opc, (outs), (ins brtarget32:$imm32), - !strconcat(opcStrAt, " $imm32"), []> { - let cy = 0; - let sy = 0; - let cz = 0; - let sz = 0; - let cf = 15; /* AT */ - let isBarrier = 1; - let hasSideEffects = 0; - } +// Multiclass for branch instructions +// e.g. BCFL, BCFW, BCFD, and etc. +let isBranch = 1, isTerminator = 1, isIndirectBranch = 1, hasSideEffects = 0 in +multiclass BCbpfm opc, dag cond, + Operand ADDR> { + let bpf = 0 /* NONE */ in + def "" : CF; + let bpf = 2 /* NOT TaKEN */ in + def _nt : CF; + let bpf = 3 /* TaKEN */ in + def _t : CF; +} +multiclass BCtgm opc, dag cond> { + defm ri : BCbpfm; + let cz = 0 in defm zi : BCbpfm; +} +multiclass BCm opc, + RegisterClass RC, Operand immOp> { + let DecoderMethod = "DecodeBranchCondition" in + defm r : BCtgm; + let DecoderMethod = "DecodeBranchCondition", cy = 0 in + defm i : BCtgm; + let DecoderMethod = "DecodeBranchConditionAlways", cy = 0, sy = 0, + cf = 15 /* AT */, isBarrier = 1 in + defm a : BCtgm; + let DecoderMethod = "DecodeBranchConditionAlways", cy = 0, sy = 0, + cf = 0 /* AF */ in + defm na : BCtgm; +} + +// Multiclass for relative branch instructions +// e.g. BRCFL, BRCFW, BRCFD, and etc. +let isBranch = 1, isTerminator = 1, hasSideEffects = 0 in +multiclass BCRbpfm opc, dag cond> { + let bpf = 0 /* NONE */ in + def "" : CF; + let bpf = 2 /* NOT TaKEN */ in + def _nt : CF; + let bpf = 3 /* TaKEN */ in + def _t : CF; +} +multiclass BCRm opc, + RegisterClass RC, Operand immOp> { + defm rr : BCRbpfm; + let cy = 0 in + defm ir : BCRbpfm; + let cy = 0, sy = 0, cz = 0, sz = 0, cf = 15 /* AT */, isBarrier = 1 in + defm a : BCRbpfm; + let cy = 0, sy = 0, cz = 0, sz = 0, cf = 0 /* AF */ in + defm na : BCRbpfm; } //===----------------------------------------------------------------------===// @@ -1019,59 +1083,50 @@ // Section 8.7.17 - CVQ (Convert to Single-format) -// Control-flow - -// Jump instruction -let cx = 0, cx2 = 0, bpf = 0 /* NONE */, cy = 1, cz = 1, - isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasSideEffects = 0 in -def BC : CF< - 0x19, (outs), (ins CCOp:$cf, I64:$sy, brtarget32:$imm32), - "b.${cf}.l $sy, $imm32">; - -// Jump always instruction is treated as a special case of jump in order -// to make finding unconditional jump easy. -let cx = 0, cx2 = 0, bpf = 0 /* NONE */, cf = 15 /* AT */, cy = 0, sy = 0, - cz = 1, - isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1, - hasDelaySlot = 1, isCodeGenOnly = 1, hasSideEffects = 0 in { -def BAri : CF< - 0x19, (outs), (ins MEMri:$addr), - "b.l $addr", - [(brind ADDRri:$addr)]>; -} +//----------------------------------------------------------------------------- +// Section 8.8 - Branch instructions +//----------------------------------------------------------------------------- + +// Section 8.8.1 - BC (Branch on Codition) +defm BCFL : BCm<"b${cond}.l", "b.l", "baf.l", 0x19, I64, simm7>; + +// Indirect branch aliases +def : Pat<(brind I64:$reg), (BCFLari_t $reg, 0)>; +def : Pat<(brind tblockaddress:$imm), (BCFLazi_t 0, $imm)>; + +// Return instruction is a special case of jump. +let Uses = [SX10], bpf = 3 /* TAKEN */, cf = 15 /* AT */, cy = 0, sy = 0, + sz = 10 /* SX10 */, imm32 = 0, isReturn = 1, isTerminator = 1, + isBarrier = 1, isCodeGenOnly = 1, hasSideEffects = 0 in +def RET : CF<0x19, (outs), (ins), "b.l.t (, %s10)", [(retflag)]>; + +// Section 8.8.2 - BCS (Branch on Condition Single) +defm BCFW : BCm<"b${cond}.w", "b.w", "baf.w", 0x1B, I32, simm7>; -// Jump never instruction is also a special case of jump. -let cx = 0, cx2 = 0, bpf = 0 /* NONE */, cf = 0 /* AF */, cy = 1, sy = 0, - cz = 1, - isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasSideEffects = 0 in -def BN : CF< - 0x19, (outs), (ins brtarget32:$imm32), - "b.af.l $imm32">; - -// Return instruction is also a special case of jump. -let cx = 0, cx2 = 0, bpf = 0 /* NONE */, cf = 15 /* AT */, cy = 0, sy = 0, - cz = 1, sz = 0x10 /* SX10 */, imm32 = 0, Uses = [SX10], - isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1, - isCodeGenOnly = 1, hasSideEffects = 0 in -def RET : CF< - 0x19, (outs), (ins), - "b.l (,%lr)", - [(retflag)]>; - -// Branch and Save IC - -let cx = 0, cy = 0, cy = 0, cz = 1, hasSideEffects = 0 /* , Uses = [IC] */ in -def BSIC : RM<0x08, (outs), (ins I64:$sx, I64:$sz), "bsic $sx, (, ${sz})">; - -// Branch instruction -let cx = 0, cx2 = 0, bpf = 0 /* NONE */ in -defm BCRL : BCRm<"br${cf}.l", "br.l", 0x18, I64, i64, simm7, uimm6>; -let cx = 1, cx2 = 0, bpf = 0 /* NONE */ in -defm BCRW : BCRm<"br${cf}.w", "br.w", 0x18, I32, i32, simm7, uimm6>; -let cx = 0, cx2 = 1, bpf = 0 /* NONE */ in -defm BCRD : BCRm<"br${cf}.d", "br.d", 0x18, I64, f64, simm7, uimm6>; -let cx = 1, cx2 = 1, bpf = 0 /* NONE */ in -defm BCRS : BCRm<"br${cf}.s", "br.s", 0x18, F32, f32, simm7, uimm6>; +// Section 8.8.3 - BCF (Branch on Condition Floating Point) +defm BCFD : BCm<"b${cond}.d", "b.d", "baf.d", 0x1C, I64, simm7fp>; +let cx = 1 in +defm BCFS : BCm<"b${cond}.s", "b.s", "baf.s", 0x1C, F32, simm7fp>; + +// Section 8.8.4 - BCR (Branch on Condition Relative) +let cx = 0, cx2 = 0 in +defm BRCFL : BCRm<"br${cf}.l", "br.l", "braf.l", 0x18, I64, simm7>; +let cx = 1, cx2 = 0 in +defm BRCFW : BCRm<"br${cf}.w", "br.w", "braf.w", 0x18, I32, simm7>; +let cx = 0, cx2 = 1 in +defm BRCFD : BCRm<"br${cf}.d", "br.d", "braf.d", 0x18, I64, simm7fp>; +let cx = 1, cx2 = 1 in +defm BRCFS : BCRm<"br${cf}.s", "br.s", "braf.s", 0x18, F32, simm7fp>; + +// Section 8.8.5 - BSIC (Branch and Save IC) +let isCall = 1, hasSideEffects = 0, DecoderMethod = "DecodeCall" in +defm BSIC : RMm<"bsic", 0x08, I64>; + +// Call instruction is a special case of BSIC. +let Defs = [SX10], sx = 10 /* SX10 */, cy = 0, sy = 0, imm32 = 0, + isCall = 1, isCodeGenOnly = 1, hasSideEffects = 0 in +def CALLr : RM<0x08, (outs), (ins I64:$sz, variable_ops), + "bsic %s10, (, $sz)", [(call i64:$sz)]>; let cx = 0, cy = 0, cz = 1, hasSideEffects = 0 in { let sy = 3 in @@ -1094,23 +1149,6 @@ // Instructions for CodeGenOnly //===----------------------------------------------------------------------===// -let isCodeGenOnly = 1 in { - -// Call instruction -let Defs = [SX10], Uses = [SX11], hasDelaySlot = 1, isCall = 1, hasSideEffects = 0 in { -let cx = 0, sx = 10, cy = 0, sy = 0, cz = 0, sz = 0 in -def CALL : RM< - 0x08, (outs), (ins calltarget:$imm32, variable_ops), - "bsic %lr, $imm32">; -// use sz to represent a register -let cx = 0, sx = 10, cy = 0, sy = 0, cz = 1, imm32 = 0 in -def CALLr : RM< - 0x08, (outs), (ins I64:$sz, variable_ops), - "bsic %lr, (,$sz)">; -} - -} - //===----------------------------------------------------------------------===// // Pattern Matchings //===----------------------------------------------------------------------===// @@ -1283,28 +1321,38 @@ (LEASLrii (ANDrm (LEAzii 0, 0, texternalsym:$in2), !add(32, 64)), 0, (texternalsym:$in1))>; -// Calls -def : Pat<(call tglobaladdr:$dst), - (CALL tglobaladdr:$dst)>; -def : Pat<(call i64:$dst), - (CALLr i64:$dst)>; - // Branches -def : Pat<(br bb:$addr), (BCRLa bb:$addr)>; +def : Pat<(br bb:$addr), (BRCFLa bb:$addr)>; // brcc -def : Pat<(brcc CCSIOp:$cond, i32:$l, i32:$r, bb:$addr), - (BCRWrr (icond2cc $cond), $l, $r, bb:$addr)>; -def : Pat<(brcc CCUIOp:$cond, i32:$l, i32:$r, bb:$addr), - (BCRWir (icond2cc $cond), 0, (CMPUWrr $r, $l), bb:$addr)>; -def : Pat<(brcc CCSIOp:$cond, i64:$l, i64:$r, bb:$addr), - (BCRLrr (icond2cc $cond), $l, $r, bb:$addr)>; -def : Pat<(brcc CCUIOp:$cond, i64:$l, i64:$r, bb:$addr), - (BCRLir (icond2cc $cond), 0, (CMPULrr $r, $l), bb:$addr)>; -def : Pat<(brcc cond:$cond, f32:$l, f32:$r, bb:$addr), - (BCRSrr (fcond2cc $cond), $l, $r, bb:$addr)>; -def : Pat<(brcc cond:$cond, f64:$l, f64:$r, bb:$addr), - (BCRDrr (fcond2cc $cond), $l, $r, bb:$addr)>; +// integer brcc +multiclass BRCCIm { + def : Pat<(brcc CCSIOp:$cond, ty:$l, simm7:$r, bb:$addr), + (BrOpNode2 (icond2ccSwap $cond), (LO7 $r), $l, bb:$addr)>; + def : Pat<(brcc CCSIOp:$cond, ty:$l, ty:$r, bb:$addr), + (BrOpNode1 (icond2cc $cond), $l, $r, bb:$addr)>; + def : Pat<(brcc CCUIOp:$cond, ty:$l, simm7:$r, bb:$addr), + (BrOpNode2 (icond2cc $cond), 0, (CmpOpNode2 (LO7 $r), $l), + bb:$addr)>; + def : Pat<(brcc CCUIOp:$cond, ty:$l, ty:$r, bb:$addr), + (BrOpNode2 (icond2cc $cond), 0, (CmpOpNode1 $r, $l), bb:$addr)>; +} +defm : BRCCIm; +defm : BRCCIm; + +// floating point brcc +multiclass BRCCFm { + def : Pat<(brcc cond:$cond, ty:$l, simm7fp:$r, bb:$addr), + (BrOpNode2 (fcond2ccSwap $cond), (LO7FP $r), $l, bb:$addr)>; + def : Pat<(brcc cond:$cond, ty:$l, ty:$r, bb:$addr), + (BrOpNode1 (fcond2cc $cond), $l, $r, bb:$addr)>; +} +defm : BRCCFm; +defm : BRCCFm; //===----------------------------------------------------------------------===// // Pseudo Instructions diff --git a/llvm/test/CodeGen/VE/branch1.ll b/llvm/test/CodeGen/VE/branch1.ll --- a/llvm/test/CodeGen/VE/branch1.ll +++ b/llvm/test/CodeGen/VE/branch1.ll @@ -9,8 +9,8 @@ ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, ret@hi(, %s0) ; CHECK-NEXT: or %s0, 2, (0)1 -; CHECK-NEXT: bsic %lr, (,%s12) -; CHECK-NEXT: br.l .LBB0_3 +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: br.l.t .LBB0_3 ; CHECK: .LBB{{[0-9]+}}_1: ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK: .LBB{{[0-9]+}}_3: @@ -42,8 +42,8 @@ ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, ret@hi(, %s0) ; CHECK-NEXT: or %s0, 2, (0)1 -; CHECK-NEXT: bsic %lr, (,%s12) -; CHECK-NEXT: br.l .LBB1_3 +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: br.l.t .LBB1_3 ; CHECK: .LBB{{[0-9]+}}_1: ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK: .LBB{{[0-9]+}}_3: @@ -70,8 +70,8 @@ ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, ret@hi(, %s0) ; CHECK-NEXT: or %s0, 2, (0)1 -; CHECK-NEXT: bsic %lr, (,%s12) -; CHECK-NEXT: br.l .LBB2_3 +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: br.l.t .LBB2_3 ; CHECK: .LBB{{[0-9]+}}_1: ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK: .LBB{{[0-9]+}}_3: @@ -98,8 +98,8 @@ ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, ret@hi(, %s0) ; CHECK-NEXT: or %s0, 2, (0)1 -; CHECK-NEXT: bsic %lr, (,%s12) -; CHECK-NEXT: br.l .LBB3_3 +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: br.l.t .LBB3_3 ; CHECK: .LBB{{[0-9]+}}_1: ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK: .LBB{{[0-9]+}}_3: @@ -127,8 +127,8 @@ ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, ret@hi(, %s0) ; CHECK-NEXT: or %s0, 2, (0)1 -; CHECK-NEXT: bsic %lr, (,%s12) -; CHECK-NEXT: br.l .LBB4_3 +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: br.l.t .LBB4_3 ; CHECK: .LBB{{[0-9]+}}_1: ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK: .LBB{{[0-9]+}}_3: @@ -156,8 +156,8 @@ ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, ret@hi(, %s0) ; CHECK-NEXT: or %s0, 2, (0)1 -; CHECK-NEXT: bsic %lr, (,%s12) -; CHECK-NEXT: br.l .LBB5_3 +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: br.l.t .LBB5_3 ; CHECK: .LBB{{[0-9]+}}_1: ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK: .LBB{{[0-9]+}}_3: @@ -185,8 +185,8 @@ ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, ret@hi(, %s0) ; CHECK-NEXT: or %s0, 2, (0)1 -; CHECK-NEXT: bsic %lr, (,%s12) -; CHECK-NEXT: br.l .LBB6_3 +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: br.l.t .LBB6_3 ; CHECK: .LBB{{[0-9]+}}_1: ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK: .LBB{{[0-9]+}}_3: @@ -213,8 +213,8 @@ ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, ret@hi(, %s0) ; CHECK-NEXT: or %s0, 2, (0)1 -; CHECK-NEXT: bsic %lr, (,%s12) -; CHECK-NEXT: br.l .LBB7_3 +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: br.l.t .LBB7_3 ; CHECK: .LBB{{[0-9]+}}_1: ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK: .LBB{{[0-9]+}}_3: @@ -241,8 +241,8 @@ ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, ret@hi(, %s0) ; CHECK-NEXT: or %s0, 2, (0)1 -; CHECK-NEXT: bsic %lr, (,%s12) -; CHECK-NEXT: br.l .LBB8_3 +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: br.l.t .LBB8_3 ; CHECK: .LBB{{[0-9]+}}_1: ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK: .LBB{{[0-9]+}}_3: @@ -270,8 +270,8 @@ ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, ret@hi(, %s0) ; CHECK-NEXT: or %s0, 2, (0)1 -; CHECK-NEXT: bsic %lr, (,%s12) -; CHECK-NEXT: br.l .LBB9_3 +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: br.l.t .LBB9_3 ; CHECK: .LBB{{[0-9]+}}_1: ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK: .LBB{{[0-9]+}}_3: diff --git a/llvm/test/CodeGen/VE/call.ll b/llvm/test/CodeGen/VE/call.ll --- a/llvm/test/CodeGen/VE/call.ll +++ b/llvm/test/CodeGen/VE/call.ll @@ -8,7 +8,7 @@ ; CHECK-NEXT: lea.sl %s12, sample_add@hi(, %s0) ; CHECK-NEXT: or %s0, 1, (0)1 ; CHECK-NEXT: or %s1, 2, (0)1 -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: or %s11, 0, %s9 %r = tail call i32 @sample_add(i32 1, i32 2) ret i32 %r @@ -34,7 +34,7 @@ ; CHECK-NEXT: or %s6, 7, (0)1 ; CHECK-NEXT: or %s7, 8, (0)1 ; CHECK-NEXT: stl %s34, 240(, %s11) -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: or %s11, 0, %s9 %r = tail call i32 @stack_callee_int(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10) ret i32 %r @@ -59,7 +59,7 @@ ; CHECK-NEXT: or %s6, 7, (0)1 ; CHECK-NEXT: or %s7, 8, (0)1 ; CHECK-NEXT: stl %s34, 240(, %s11) -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: or %s11, 0, %s9 %r = tail call i32 @stack_callee_int_szext(i1 -1, i8 -1, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i16 -1, i8 -1) ret i32 %r @@ -93,7 +93,7 @@ ; CHECK-NEXT: or %s5, 0, %s6 ; CHECK-NEXT: or %s6, 0, %s7 ; CHECK-NEXT: or %s7, 0, %s34 -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: or %s11, 0, %s9 %r = tail call float @stack_callee_float(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0) ret float %r @@ -116,7 +116,7 @@ ; CHECK-NEXT: or %s5, 0, %s0 ; CHECK-NEXT: or %s6, 0, %s0 ; CHECK-NEXT: or %s7, 0, %s0 -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: or %s11, 0, %s9 %r = tail call float @stack_callee_float(float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0) ret float %r diff --git a/llvm/test/CodeGen/VE/callstruct.ll b/llvm/test/CodeGen/VE/callstruct.ll --- a/llvm/test/CodeGen/VE/callstruct.ll +++ b/llvm/test/CodeGen/VE/callstruct.ll @@ -28,7 +28,7 @@ ; CHECK-NEXT: lea %s0, -8(, %s9) ; CHECK-NEXT: or %s1, 3, (0)1 ; CHECK-NEXT: or %s2, 4, (0)1 -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: ld %s0, -8(, %s9) ; CHECK-NEXT: lea %s1, A@lo ; CHECK-NEXT: and %s1, %s1, (32)0 diff --git a/llvm/test/CodeGen/VE/fp_extload_truncstore.ll b/llvm/test/CodeGen/VE/fp_extload_truncstore.ll --- a/llvm/test/CodeGen/VE/fp_extload_truncstore.ll +++ b/llvm/test/CodeGen/VE/fp_extload_truncstore.ll @@ -13,7 +13,7 @@ ; CHECK-NEXT: lea %s1, __gnu_h2f_ieee@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s12, __gnu_h2f_ieee@hi(, %s1) -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: or %s11, 0, %s9 %a.val = load i16, i16* %a, align 4 %a.asd = call float @llvm.convert.from.fp16.f32(i16 %a.val) @@ -27,7 +27,7 @@ ; CHECK-NEXT: lea %s1, __gnu_h2f_ieee@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s12, __gnu_h2f_ieee@hi(, %s1) -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: cvt.d.s %s0, %s0 ; CHECK-NEXT: or %s11, 0, %s9 %a.val = load i16, i16* %a, align 4 @@ -42,7 +42,7 @@ ; CHECK-NEXT: lea %s1, __gnu_h2f_ieee@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s12, __gnu_h2f_ieee@hi(, %s1) -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: or %s11, 0, %s9 %a.val = load half, half* %a, align 4 %a.asd = fpext half %a.val to float @@ -56,7 +56,7 @@ ; CHECK-NEXT: lea %s1, __gnu_h2f_ieee@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s12, __gnu_h2f_ieee@hi(, %s1) -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: cvt.d.s %s0, %s0 ; CHECK-NEXT: or %s11, 0, %s9 %a.val = load half, half* %a, align 4 @@ -73,7 +73,7 @@ ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, __gnu_f2h_ieee@hi(, %s0) ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: st2b %s0, (, %s18) ; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload ; CHECK-NEXT: or %s11, 0, %s9 @@ -92,13 +92,13 @@ ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, __gnu_f2h_ieee@hi(, %s0) ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: or %s19, 0, %s0 ; CHECK-NEXT: lea %s0, __gnu_h2f_ieee@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, __gnu_h2f_ieee@hi(, %s0) ; CHECK-NEXT: or %s0, 0, %s19 -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: st2b %s19, (, %s18) ; CHECK-NEXT: ld %s19, 56(, %s9) # 8-byte Folded Reload ; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload @@ -128,7 +128,7 @@ ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, __truncdfhf2@hi(, %s0) ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: st2b %s0, (, %s18) ; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload ; CHECK-NEXT: or %s11, 0, %s9 @@ -146,7 +146,7 @@ ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, __truncdfhf2@hi(, %s0) ; CHECK-NEXT: or %s0, 0, %s1 -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: st2b %s0, (, %s18) ; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload ; CHECK-NEXT: or %s11, 0, %s9 diff --git a/llvm/test/CodeGen/VE/pic_access_static_data.ll b/llvm/test/CodeGen/VE/pic_access_static_data.ll --- a/llvm/test/CodeGen/VE/pic_access_static_data.ll +++ b/llvm/test/CodeGen/VE/pic_access_static_data.ll @@ -47,7 +47,7 @@ ; CHECK-NEXT: and %s12, %s12, (32)0 ; CHECK-NEXT: sic %s16 ; CHECK-NEXT: lea.sl %s12, func@plt_hi(%s16, %s12) -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: lea %s0, dst@gotoff_lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, dst@gotoff_hi(, %s0) @@ -62,7 +62,7 @@ ; CHECK-NEXT: sic %s16 ; CHECK-NEXT: lea.sl %s12, printf@plt_hi(%s16, %s12) ; CHECK-NEXT: st %s0, 176(, %s11) -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: or %s11, 0, %s9 store i1 true, i1* @src, align 4 diff --git a/llvm/test/CodeGen/VE/pic_func_call.ll b/llvm/test/CodeGen/VE/pic_func_call.ll --- a/llvm/test/CodeGen/VE/pic_func_call.ll +++ b/llvm/test/CodeGen/VE/pic_func_call.ll @@ -11,7 +11,7 @@ ; CHECK-NEXT: and %s12, %s12, (32)0 ; CHECK-NEXT: sic %s16 ; CHECK-NEXT: lea.sl %s12, function@plt_hi(%s16, %s12) -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: or %s11, 0, %s9 call void bitcast (void (...)* @function to void ()*)() diff --git a/llvm/test/CodeGen/VE/pic_indirect_func_call.ll b/llvm/test/CodeGen/VE/pic_indirect_func_call.ll --- a/llvm/test/CodeGen/VE/pic_indirect_func_call.ll +++ b/llvm/test/CodeGen/VE/pic_indirect_func_call.ll @@ -19,7 +19,7 @@ ; CHECK-NEXT: ld %s1, (%s1, %s15) ; CHECK-NEXT: st %s0, (, %s1) ; CHECK-NEXT: or %s12, 0, %s0 -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: or %s11, 0, %s9 store void (...)* @function, void (...)** @ptr, align 8 diff --git a/llvm/test/CodeGen/VE/simple_prologue_epilogue.ll b/llvm/test/CodeGen/VE/simple_prologue_epilogue.ll --- a/llvm/test/CodeGen/VE/simple_prologue_epilogue.ll +++ b/llvm/test/CodeGen/VE/simple_prologue_epilogue.ll @@ -11,7 +11,7 @@ ; CHECK-NEXT: lea %s13, -176 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) -; CHECK-NEXT: brge.l %s11, %s8, .LBB0_2 +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB0_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 @@ -27,7 +27,7 @@ ; CHECK-NEXT: ld %s15, 24(, %s11) ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) -; CHECK-NEXT: b.l (,%lr) +; CHECK-NEXT: b.l.t (, %s10) ret void } @@ -42,7 +42,7 @@ ; CHECK-NEXT: lea %s13, -176 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) -; CHECK-NEXT: brge.l %s11, %s8, .LBB1_2 +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB1_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 @@ -58,7 +58,7 @@ ; CHECK-NEXT: ld %s15, 24(, %s11) ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) -; CHECK-NEXT: b.l (,%lr) +; CHECK-NEXT: b.l.t (, %s10) ret i64 %0 } @@ -73,7 +73,7 @@ ; CHECK-NEXT: lea %s13, -176 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) -; CHECK-NEXT: brge.l %s11, %s8, .LBB2_2 +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB2_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 @@ -90,6 +90,6 @@ ; CHECK-NEXT: ld %s15, 24(, %s11) ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) -; CHECK-NEXT: b.l (,%lr) +; CHECK-NEXT: b.l.t (, %s10) ret i64 %4 } diff --git a/llvm/test/CodeGen/VE/va_caller.ll b/llvm/test/CodeGen/VE/va_caller.ll --- a/llvm/test/CodeGen/VE/va_caller.ll +++ b/llvm/test/CodeGen/VE/va_caller.ll @@ -38,7 +38,7 @@ ; CHECK-NEXT: stl %s18, 176(, %s11) ; CHECK-NEXT: or %s6, 0, %s0 ; CHECK-NEXT: or %s0, 0, %s18 -; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: or %s0, 0, %s18 ; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload ; CHECK-NEXT: or %s11, 0, %s9