diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1177,6 +1177,8 @@
       return MatchOperand_ParseFail;
 
     auto SysReg = RISCVSysReg::lookupSysRegByName(Identifier);
+    if (!SysReg)
+      SysReg = RISCVSysReg::lookupSysRegByAltName(Identifier);
     // Accept a named Sys Reg if the required features are present.
     if (SysReg) {
       if (!SysReg->haveRequiredFeatures(getSTI().getFeatureBits())) {
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -20,6 +20,8 @@
 class SysReg<string name, bits<12> op> {
   string Name = name;
   bits<12> Encoding = op;
+  // FIXME: support multiple aliases when needed
+  string AltName = name;
   // FIXME: add these additional fields when needed.
   // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
   // Privilege Mode: User = 0, System = 1 or Machine = 3.
@@ -36,7 +38,7 @@
 def SysRegsList : GenericTable {
   let FilterClass = "SysReg";
   // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
-  let Fields = [ "Name", "Encoding", "FeaturesRequired", "isRV32Only" ];
+  let Fields = [ "Name", "Encoding", "AltName", "FeaturesRequired", "isRV32Only" ];
 
   let PrimaryKey = [ "Encoding" ];
   let PrimaryKeyName = "lookupSysRegByEncoding";
@@ -47,6 +49,11 @@
   let Key = [ "Name" ];
 }
 
+def lookupSysRegByAltName : SearchIndex {
+  let Table = SysRegsList;
+  let Key = [ "AltName" ];
+}
+
 // The following CSR encodings match those given in Tables 2.2,
 // 2.3, 2.4 and  2.5 in the RISC-V Instruction Set Manual
 // Volume II: Privileged Architecture.
@@ -346,4 +353,8 @@
 //===-----------------------------------------------
 def : SysReg<"dcsr", 0x7B0>;
 def : SysReg<"dpc", 0x7B1>;
-def : SysReg<"dscratch", 0x7B2>;
+// "dscratch" is an alternative name for "dscratch0" which appeared in earlier
+// drafts of the RISC-V debug spec
+let AltName = "dscratch" in
+def : SysReg<"dscratch0", 0x7B2>;
+def : SysReg<"dscratch1", 0x7B3>;
diff --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
--- a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
@@ -157,6 +157,8 @@
 struct SysReg {
   const char *Name;
   unsigned Encoding;
+  // FIXME: support multiple aliases when needed
+  const char *AltName;
   // FIXME: add these additional fields when needed.
   // Privilege Access: Read, Write, Read-Only.
   // unsigned ReadWrite;
diff --git a/llvm/test/MC/RISCV/debug-csr-names.s b/llvm/test/MC/RISCV/debug-csr-names.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/debug-csr-names.s
@@ -0,0 +1,84 @@
+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:     | llvm-objdump -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+#
+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
+# RUN:     | llvm-objdump -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+
+#######################
+# Debug Mode Registers
+########################
+# dcsr
+# name
+# CHECK-INST: csrrs t1, dcsr, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x7b]
+# CHECK-INST-ALIAS: csrr t1, dcsr
+# uimm12
+# CHECK-INST: csrrs t2, dcsr, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7b]
+# CHECK-INST-ALIAS: csrr t2, dcsr
+# name
+csrrs t1, dcsr, zero
+# uimm12
+csrrs t2, 0x7B0, zero
+
+# dpc
+# name
+# CHECK-INST: csrrs t1, dpc, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x7b]
+# CHECK-INST-ALIAS: csrr t1, dpc
+# uimm12
+# CHECK-INST: csrrs t2, dpc, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7b]
+# CHECK-INST-ALIAS: csrr t2, dpc
+# name
+csrrs t1, dpc, zero
+# uimm12
+csrrs t2, 0x7B1, zero
+
+# dscratch0
+# name
+# CHECK-INST: csrrs t1, dscratch0, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x7b]
+# CHECK-INST-ALIAS: csrr t1, dscratch0
+# uimm12
+# CHECK-INST: csrrs t2, dscratch0, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7b]
+# CHECK-INST-ALIAS: csrr t2, dscratch0
+# name
+csrrs t1, dscratch0, zero
+# uimm12
+csrrs t2, 0x7B2, zero
+
+# dscratch
+# name
+# CHECK-INST: csrrs t1, dscratch0, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x7b]
+# CHECK-INST-ALIAS: csrr t1, dscratch0
+# uimm12
+# CHECK-INST: csrrs t2, dscratch0, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7b]
+# CHECK-INST-ALIAS: csrr t2, dscratch0
+# name
+csrrs t1, dscratch, zero
+# uimm12
+csrrs t2, 0x7B2, zero
+
+# dscratch1
+# name
+# CHECK-INST: csrrs t1, dscratch1, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x30,0x7b]
+# CHECK-INST-ALIAS: csrr t1, dscratch1
+# uimm12
+# CHECK-INST: csrrs t2, dscratch1, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7b]
+# CHECK-INST-ALIAS: csrr t2, dscratch1
+# name
+csrrs t1, dscratch1, zero
+# uimm12
+csrrs t2, 0x7B3, zero
diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s
--- a/llvm/test/MC/RISCV/machine-csr-names.s
+++ b/llvm/test/MC/RISCV/machine-csr-names.s
@@ -366,51 +366,6 @@
 # uimm12
 csrrs t2, 0x7A3, zero
 
-#######################
-# Debug Mode Registers
-########################
-# dcsr
-# name
-# CHECK-INST: csrrs t1, dcsr, zero
-# CHECK-ENC: encoding: [0x73,0x23,0x00,0x7b]
-# CHECK-INST-ALIAS: csrr t1, dcsr
-# uimm12
-# CHECK-INST: csrrs t2, dcsr, zero
-# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7b]
-# CHECK-INST-ALIAS: csrr t2, dcsr
-# name
-csrrs t1, dcsr, zero
-# uimm12
-csrrs t2, 0x7B0, zero
-
-# dpc
-# name
-# CHECK-INST: csrrs t1, dpc, zero
-# CHECK-ENC: encoding: [0x73,0x23,0x10,0x7b]
-# CHECK-INST-ALIAS: csrr t1, dpc
-# uimm12
-# CHECK-INST: csrrs t2, dpc, zero
-# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7b]
-# CHECK-INST-ALIAS: csrr t2, dpc
-# name
-csrrs t1, dpc, zero
-# uimm12
-csrrs t2, 0x7B1, zero
-
-# dscratch
-# name
-# CHECK-INST: csrrs t1, dscratch, zero
-# CHECK-ENC: encoding: [0x73,0x23,0x20,0x7b]
-# CHECK-INST-ALIAS: csrr t1, dscratch
-# uimm12
-# CHECK-INST: csrrs t2, dscratch, zero
-# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7b]
-# CHECK-INST-ALIAS: csrr t2, dscratch
-# name
-csrrs t1, dscratch, zero
-# uimm12
-csrrs t2, 0x7B2, zero
-
 # mhpmcounter3
 # name
 # CHECK-INST: csrrs t1, mhpmcounter3, zero