diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
@@ -1,10 +1,9 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :7:27: incorrect register class for field
-# CHECK: scratchRSrcReg:  '$noreg'
 ---
 name: noreg_rsrc_reg
 machineFunctionInfo:
   scratchRSrcReg:  '$noreg'
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
 body:             |
   bb.0:
 
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
@@ -1,10 +1,9 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :7:21: unknown register name 'not_a_register_name'
-# CHECK: scratchRSrcReg:  '$not_a_register_name'
 ---
 name: invalid_rsrc_reg
 machineFunctionInfo:
   scratchRSrcReg:  '$not_a_register_name'
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: unknown register name 'not_a_register_name'
 body:             |
   bb.0:
 
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
@@ -1,11 +1,10 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :8:27: incorrect register class for field
-# CHECK: frameOffsetReg:  '$vgpr0'
 
 ---
 name: wrong_reg_class_frame_offset_reg
 machineFunctionInfo:
   frameOffsetReg:  '$vgpr0'
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
 body:             |
   bb.0:
 
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
@@ -1,10 +1,9 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :7:21: expected a named register
-# CHECK: frameOffsetReg:  ''
 ---
 name: empty_frame_offset_reg
 machineFunctionInfo:
   frameOffsetReg:  ''
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: expected a named register
 body:             |
   bb.0:
 
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
@@ -1,10 +1,9 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :7:21: expected a named register
-# CHECK: scratchRSrcReg:  ''
 ---
 name: empty_scratch_rsrc_reg
 machineFunctionInfo:
   scratchRSrcReg:  ''
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: expected a named register
 body:             |
   bb.0:
 
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
@@ -1,10 +1,9 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :7:24: expected a named register
-# CHECK: stackPtrOffsetReg:  ''
 ---
 name: empty_stack_ptr_offset_reg
 machineFunctionInfo:
   stackPtrOffsetReg:  ''
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: expected a named register
 body:             |
   bb.0:
 
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
@@ -1,11 +1,10 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :8:45: incorrect register class for field
-# CHECK: scratchRSrcReg:  '$vgpr0_vgpr1_vgpr2_vgpr3'
 
 ---
 name: wrong_reg_class_scratch_rsrc_reg
 machineFunctionInfo:
   scratchRSrcReg:  '$vgpr0_vgpr1_vgpr2_vgpr3'
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
 body:             |
   bb.0:
 
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
@@ -1,11 +1,10 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :8:30: incorrect register class for field
-# CHECK: stackPtrOffsetReg:  '$vgpr0'
 
 ---
 name: wrong_reg_class_stack_ptr_offset_reg
 machineFunctionInfo:
   stackPtrOffsetReg:  '$vgpr0'
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
 body:             |
   bb.0: