diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -230,22 +230,22 @@ // Loads // Load one vector (scalar base) -def SVLD1 : MInst<"svld1[_{2}]", "dPc", "csilUcUsUiUlhfd", [IsLoad]>; -def SVLD1SB : MInst<"svld1sb_{d}", "dPS", "silUsUiUl", [IsLoad], MemEltTyInt8>; -def SVLD1UB : MInst<"svld1ub_{d}", "dPW", "silUsUiUl", [IsLoad, IsZExtReturn], MemEltTyInt8>; -def SVLD1SH : MInst<"svld1sh_{d}", "dPT", "ilUiUl", [IsLoad], MemEltTyInt16>; -def SVLD1UH : MInst<"svld1uh_{d}", "dPX", "ilUiUl", [IsLoad, IsZExtReturn], MemEltTyInt16>; -def SVLD1SW : MInst<"svld1sw_{d}", "dPU", "lUl", [IsLoad], MemEltTyInt32>; -def SVLD1UW : MInst<"svld1uw_{d}", "dPY", "lUl", [IsLoad, IsZExtReturn], MemEltTyInt32>; +def SVLD1 : MInst<"svld1[_{2}]", "dPc", "csilUcUsUiUlhfd", [IsLoad], MemEltTyDefault, "aarch64_sve_ld1">; +def SVLD1SB : MInst<"svld1sb_{d}", "dPS", "silUsUiUl", [IsLoad], MemEltTyInt8, "aarch64_sve_ld1">; +def SVLD1UB : MInst<"svld1ub_{d}", "dPW", "silUsUiUl", [IsLoad, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ld1">; +def SVLD1SH : MInst<"svld1sh_{d}", "dPT", "ilUiUl", [IsLoad], MemEltTyInt16, "aarch64_sve_ld1">; +def SVLD1UH : MInst<"svld1uh_{d}", "dPX", "ilUiUl", [IsLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ld1">; +def SVLD1SW : MInst<"svld1sw_{d}", "dPU", "lUl", [IsLoad], MemEltTyInt32, "aarch64_sve_ld1">; +def SVLD1UW : MInst<"svld1uw_{d}", "dPY", "lUl", [IsLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ld1">; // Load one vector (scalar base, VL displacement) -def SVLD1_VNUM : MInst<"svld1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfd", [IsLoad]>; -def SVLD1SB_VNUM : MInst<"svld1sb_vnum_{d}", "dPSl", "silUsUiUl", [IsLoad], MemEltTyInt8>; -def SVLD1UB_VNUM : MInst<"svld1ub_vnum_{d}", "dPWl", "silUsUiUl", [IsLoad, IsZExtReturn], MemEltTyInt8>; -def SVLD1SH_VNUM : MInst<"svld1sh_vnum_{d}", "dPTl", "ilUiUl", [IsLoad], MemEltTyInt16>; -def SVLD1UH_VNUM : MInst<"svld1uh_vnum_{d}", "dPXl", "ilUiUl", [IsLoad, IsZExtReturn], MemEltTyInt16>; -def SVLD1SW_VNUM : MInst<"svld1sw_vnum_{d}", "dPUl", "lUl", [IsLoad], MemEltTyInt32>; -def SVLD1UW_VNUM : MInst<"svld1uw_vnum_{d}", "dPYl", "lUl", [IsLoad, IsZExtReturn], MemEltTyInt32>; +def SVLD1_VNUM : MInst<"svld1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfd", [IsLoad], MemEltTyDefault, "aarch64_sve_ld1">; +def SVLD1SB_VNUM : MInst<"svld1sb_vnum_{d}", "dPSl", "silUsUiUl", [IsLoad], MemEltTyInt8, "aarch64_sve_ld1">; +def SVLD1UB_VNUM : MInst<"svld1ub_vnum_{d}", "dPWl", "silUsUiUl", [IsLoad, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ld1">; +def SVLD1SH_VNUM : MInst<"svld1sh_vnum_{d}", "dPTl", "ilUiUl", [IsLoad], MemEltTyInt16, "aarch64_sve_ld1">; +def SVLD1UH_VNUM : MInst<"svld1uh_vnum_{d}", "dPXl", "ilUiUl", [IsLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ld1">; +def SVLD1SW_VNUM : MInst<"svld1sw_vnum_{d}", "dPUl", "lUl", [IsLoad], MemEltTyInt32, "aarch64_sve_ld1">; +def SVLD1UW_VNUM : MInst<"svld1uw_vnum_{d}", "dPYl", "lUl", [IsLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ld1">; // Load one vector (vector base) def SVLD1_GATHER_BASES_U : MInst<"svld1_gather[_{2}base]_{d}", "dPu", "ilUiUlfd", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ld1_gather_scalar_offset">; @@ -449,22 +449,22 @@ // Stores // Store one vector (scalar base) -def SVST1 : MInst<"svst1[_{d}]", "vPpd", "csilUcUsUiUlhfd", [IsStore]>; -def SVST1B_S : MInst<"svst1b[_{d}]", "vPAd", "sil", [IsStore], MemEltTyInt8>; -def SVST1B_U : MInst<"svst1b[_{d}]", "vPEd", "UsUiUl", [IsStore], MemEltTyInt8>; -def SVST1H_S : MInst<"svst1h[_{d}]", "vPBd", "il", [IsStore], MemEltTyInt16>; -def SVST1H_U : MInst<"svst1h[_{d}]", "vPFd", "UiUl", [IsStore], MemEltTyInt16>; -def SVST1W_S : MInst<"svst1w[_{d}]", "vPCd", "l", [IsStore], MemEltTyInt32>; -def SVST1W_U : MInst<"svst1w[_{d}]", "vPGd", "Ul", [IsStore], MemEltTyInt32>; +def SVST1 : MInst<"svst1[_{d}]", "vPpd", "csilUcUsUiUlhfd", [IsStore], MemEltTyDefault, "aarch64_sve_st1">; +def SVST1B_S : MInst<"svst1b[_{d}]", "vPAd", "sil", [IsStore], MemEltTyInt8, "aarch64_sve_st1">; +def SVST1B_U : MInst<"svst1b[_{d}]", "vPEd", "UsUiUl", [IsStore], MemEltTyInt8, "aarch64_sve_st1">; +def SVST1H_S : MInst<"svst1h[_{d}]", "vPBd", "il", [IsStore], MemEltTyInt16, "aarch64_sve_st1">; +def SVST1H_U : MInst<"svst1h[_{d}]", "vPFd", "UiUl", [IsStore], MemEltTyInt16, "aarch64_sve_st1">; +def SVST1W_S : MInst<"svst1w[_{d}]", "vPCd", "l", [IsStore], MemEltTyInt32, "aarch64_sve_st1">; +def SVST1W_U : MInst<"svst1w[_{d}]", "vPGd", "Ul", [IsStore], MemEltTyInt32, "aarch64_sve_st1">; // Store one vector (scalar base, VL displacement) -def SVST1_VNUM : MInst<"svst1_vnum[_{d}]", "vPpld", "csilUcUsUiUlhfd", [IsStore]>; -def SVST1B_VNUM_S : MInst<"svst1b_vnum[_{d}]", "vPAld", "sil", [IsStore], MemEltTyInt8>; -def SVST1B_VNUM_U : MInst<"svst1b_vnum[_{d}]", "vPEld", "UsUiUl", [IsStore], MemEltTyInt8>; -def SVST1H_VNUM_S : MInst<"svst1h_vnum[_{d}]", "vPBld", "il", [IsStore], MemEltTyInt16>; -def SVST1H_VNUM_U : MInst<"svst1h_vnum[_{d}]", "vPFld", "UiUl", [IsStore], MemEltTyInt16>; -def SVST1W_VNUM_S : MInst<"svst1w_vnum[_{d}]", "vPCld", "l", [IsStore], MemEltTyInt32>; -def SVST1W_VNUM_U : MInst<"svst1w_vnum[_{d}]", "vPGld", "Ul", [IsStore], MemEltTyInt32>; +def SVST1_VNUM : MInst<"svst1_vnum[_{d}]", "vPpld", "csilUcUsUiUlhfd", [IsStore], MemEltTyDefault, "aarch64_sve_st1">; +def SVST1B_VNUM_S : MInst<"svst1b_vnum[_{d}]", "vPAld", "sil", [IsStore], MemEltTyInt8, "aarch64_sve_st1">; +def SVST1B_VNUM_U : MInst<"svst1b_vnum[_{d}]", "vPEld", "UsUiUl", [IsStore], MemEltTyInt8, "aarch64_sve_st1">; +def SVST1H_VNUM_S : MInst<"svst1h_vnum[_{d}]", "vPBld", "il", [IsStore], MemEltTyInt16, "aarch64_sve_st1">; +def SVST1H_VNUM_U : MInst<"svst1h_vnum[_{d}]", "vPFld", "UiUl", [IsStore], MemEltTyInt16, "aarch64_sve_st1">; +def SVST1W_VNUM_S : MInst<"svst1w_vnum[_{d}]", "vPCld", "l", [IsStore], MemEltTyInt32, "aarch64_sve_st1">; +def SVST1W_VNUM_U : MInst<"svst1w_vnum[_{d}]", "vPGld", "Ul", [IsStore], MemEltTyInt32, "aarch64_sve_st1">; // Store one vector, with no truncation, non-temporal (scalar base) def SVSTNT1 : MInst<"svstnt1[_{d}]", "vPpd", "csilUcUsUiUlhfd", [IsStore], MemEltTyDefault, "aarch64_sve_stnt1">; diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -7726,17 +7726,9 @@ Value *Offset = Ops.size() > 2 ? Ops[2] : Builder.getInt32(0); BasePtr = Builder.CreateGEP(MemoryTy, BasePtr, Offset); - Value *Splat0 = Constant::getNullValue(MemoryTy); - - Value *Load = nullptr; - if (!BuiltinID) - // Regular masked loads take a different path from the SVE-specific ones. - Load = Builder.CreateMaskedLoad(BasePtr, llvm::Align(1), Predicate, Splat0); - else { - BasePtr = Builder.CreateBitCast(BasePtr, MemEltTy->getPointerTo()); - Function *F = CGM.getIntrinsic(BuiltinID, MemoryTy); - Load = Builder.CreateCall(F, {Predicate, BasePtr}); - } + BasePtr = Builder.CreateBitCast(BasePtr, MemEltTy->getPointerTo()); + Function *F = CGM.getIntrinsic(BuiltinID, MemoryTy); + Value *Load = Builder.CreateCall(F, {Predicate, BasePtr}); return IsZExtReturn ? Builder.CreateZExt(Load, VectorTy) : Builder.CreateSExt(Load, VectorTy); @@ -7762,9 +7754,6 @@ // Last value is always the data llvm::Value *Val = Builder.CreateTrunc(Ops.back(), MemoryTy); - if (!BuiltinID) - return Builder.CreateMaskedStore(Val, BasePtr, llvm::Align(1), Predicate); - BasePtr = Builder.CreateBitCast(BasePtr, MemEltTy->getPointerTo()); Function *F = CGM.getIntrinsic(BuiltinID, MemoryTy); return Builder.CreateCall(F, {Val, Predicate, BasePtr}); diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c @@ -13,8 +13,7 @@ svint8_t test_svld1_s8(svbool_t pg, const int8_t *base) { // CHECK-LABEL: test_svld1_s8 - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK-DAG: %[[LOAD:.*]] = call @llvm.masked.load.nxv16i8.p0nxv16i8(* %[[BASE]], i32 1, %pg, zeroinitializer) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv16i8( %pg, i8* %base) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1,_s8,,)(pg, base); } @@ -22,9 +21,8 @@ svint16_t test_svld1_s16(svbool_t pg, const int16_t *base) { // CHECK-LABEL: test_svld1_s16 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv8i16.p0nxv8i16(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv8i16( %[[PG]], i16* %base) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1,_s16,,)(pg, base); } @@ -32,9 +30,8 @@ svint32_t test_svld1_s32(svbool_t pg, const int32_t *base) { // CHECK-LABEL: test_svld1_s32 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i32.p0nxv4i32(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i32( %[[PG]], i32* %base) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1,_s32,,)(pg, base); } @@ -42,9 +39,8 @@ svint64_t test_svld1_s64(svbool_t pg, const int64_t *base) { // CHECK-LABEL: test_svld1_s64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i64.p0nxv2i64(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i64( %[[PG]], i64* %base) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1,_s64,,)(pg, base); } @@ -52,8 +48,7 @@ svuint8_t test_svld1_u8(svbool_t pg, const uint8_t *base) { // CHECK-LABEL: test_svld1_u8 - // CHECK: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv16i8.p0nxv16i8(* %[[BASE]], i32 1, %pg, zeroinitializer) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv16i8( %pg, i8* %base) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1,_u8,,)(pg, base); } @@ -61,9 +56,8 @@ svuint16_t test_svld1_u16(svbool_t pg, const uint16_t *base) { // CHECK-LABEL: test_svld1_u16 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv8i16.p0nxv8i16(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv8i16( %[[PG]], i16* %base) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1,_u16,,)(pg, base); } @@ -71,9 +65,8 @@ svuint32_t test_svld1_u32(svbool_t pg, const uint32_t *base) { // CHECK-LABEL: test_svld1_u32 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i32.p0nxv4i32(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i32( %[[PG]], i32* %base) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1,_u32,,)(pg, base); } @@ -81,9 +74,8 @@ svuint64_t test_svld1_u64(svbool_t pg, const uint64_t *base) { // CHECK-LABEL: test_svld1_u64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i64.p0nxv2i64(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i64( %[[PG]], i64* %base) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1,_u64,,)(pg, base); } @@ -91,9 +83,8 @@ svfloat16_t test_svld1_f16(svbool_t pg, const float16_t *base) { // CHECK-LABEL: test_svld1_f16 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast half* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv8f16.p0nxv8f16(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv8f16( %[[PG]], half* %base) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1,_f16,,)(pg, base); } @@ -101,9 +92,8 @@ svfloat32_t test_svld1_f32(svbool_t pg, const float32_t *base) { // CHECK-LABEL: test_svld1_f32 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast float* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4f32.p0nxv4f32(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4f32( %[[PG]], float* %base) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1,_f32,,)(pg, base); } @@ -111,9 +101,8 @@ svfloat64_t test_svld1_f64(svbool_t pg, const float64_t *base) { // CHECK-LABEL: test_svld1_f64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast double* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2f64.p0nxv2f64(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2f64( %[[PG]], double* %base) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1,_f64,,)(pg, base); } @@ -121,9 +110,9 @@ svint8_t test_svld1_vnum_s8(svbool_t pg, const int8_t *base, int64_t vnum) { // CHECK-LABEL: test_svld1_vnum_s8 - // CHECK: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv16i8.p0nxv16i8(* %[[GEP]], i32 1, %pg, zeroinitializer) + // CHECK: %[[BITCAST:.*]] = bitcast i8* %base to * + // CHECK: %[[GEP:.*]] = getelementptr , * %[[BITCAST]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv16i8( %pg, i8* %[[GEP]]) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1_vnum,_s8,,)(pg, base, vnum); } @@ -132,9 +121,9 @@ { // CHECK-LABEL: test_svld1_vnum_s16 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv8i16.p0nxv8i16(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[BITCAST:.*]] = bitcast i16* %base to * + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BITCAST]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv8i16( %[[PG]], i16* %[[GEP]]) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1_vnum,_s16,,)(pg, base, vnum); } @@ -143,9 +132,9 @@ { // CHECK-LABEL: test_svld1_vnum_s32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i32.p0nxv4i32(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[BITCAST:.*]] = bitcast i32* %base to * + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BITCAST]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i32( %[[PG]], i32* %[[GEP]]) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1_vnum,_s32,,)(pg, base, vnum); } @@ -154,9 +143,9 @@ { // CHECK-LABEL: test_svld1_vnum_s64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i64.p0nxv2i64(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[BITCAST:.*]] = bitcast i64* %base to * + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BITCAST]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i64( %[[PG]], i64* %[[GEP]]) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1_vnum,_s64,,)(pg, base, vnum); } @@ -164,9 +153,9 @@ svuint8_t test_svld1_vnum_u8(svbool_t pg, const uint8_t *base, int64_t vnum) { // CHECK-LABEL: test_svld1_vnum_u8 - // CHECK: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv16i8.p0nxv16i8(* %[[GEP]], i32 1, %pg, zeroinitializer) + // CHECK: %[[BITCAST:.*]] = bitcast i8* %base to * + // CHECK: %[[GEP:.*]] = getelementptr , * %[[BITCAST]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv16i8( %pg, i8* %[[GEP]]) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1_vnum,_u8,,)(pg, base, vnum); } @@ -175,9 +164,9 @@ { // CHECK-LABEL: test_svld1_vnum_u16 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv8i16.p0nxv8i16(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[BITCAST:.*]] = bitcast i16* %base to * + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BITCAST]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv8i16( %[[PG]], i16* %[[GEP]]) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1_vnum,_u16,,)(pg, base, vnum); } @@ -186,9 +175,9 @@ { // CHECK-LABEL: test_svld1_vnum_u32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i32.p0nxv4i32(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[BITCAST:.*]] = bitcast i32* %base to * + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BITCAST]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i32( %[[PG]], i32* %[[GEP]]) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1_vnum,_u32,,)(pg, base, vnum); } @@ -197,9 +186,9 @@ { // CHECK-LABEL: test_svld1_vnum_u64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i64.p0nxv2i64(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[BITCAST:.*]] = bitcast i64* %base to * + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BITCAST]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i64( %[[PG]], i64* %[[GEP]]) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1_vnum,_u64,,)(pg, base, vnum); } @@ -208,9 +197,9 @@ { // CHECK-LABEL: test_svld1_vnum_f16 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast half* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv8f16.p0nxv8f16(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[BITCAST:.*]] = bitcast half* %base to * + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BITCAST]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv8f16( %[[PG]], half* %[[GEP]]) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1_vnum,_f16,,)(pg, base, vnum); } @@ -219,9 +208,9 @@ { // CHECK-LABEL: test_svld1_vnum_f32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast float* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4f32.p0nxv4f32(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[BITCAST:.*]] = bitcast float* %base to * + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BITCAST]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4f32( %[[PG]], float* %[[GEP]]) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1_vnum,_f32,,)(pg, base, vnum); } @@ -230,9 +219,9 @@ { // CHECK-LABEL: test_svld1_vnum_f64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast double* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2f64.p0nxv2f64(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[BITCAST:.*]] = bitcast double* %base to * + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BITCAST]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2f64( %[[PG]], double* %[[GEP]]) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1_vnum,_f64,,)(pg, base, vnum); } diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sb.c @@ -13,9 +13,8 @@ svint16_t test_svld1sb_s16(svbool_t pg, const int8_t *base) { // CHECK-LABEL: test_svld1sb_s16 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv8i8.p0nxv8i8(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv8i8( %[[PG]], i8* %base) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sb_s16(pg, base); @@ -24,9 +23,8 @@ svint32_t test_svld1sb_s32(svbool_t pg, const int8_t *base) { // CHECK-LABEL: test_svld1sb_s32 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i8.p0nxv4i8(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i8( %[[PG]], i8* %base) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sb_s32(pg, base); @@ -35,9 +33,8 @@ svint64_t test_svld1sb_s64(svbool_t pg, const int8_t *base) { // CHECK-LABEL: test_svld1sb_s64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i8.p0nxv2i8(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i8( %[[PG]], i8* %base) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sb_s64(pg, base); @@ -46,9 +43,8 @@ svuint16_t test_svld1sb_u16(svbool_t pg, const int8_t *base) { // CHECK-LABEL: test_svld1sb_u16 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv8i8.p0nxv8i8(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv8i8( %[[PG]], i8* %base) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sb_u16(pg, base); @@ -57,9 +53,8 @@ svuint32_t test_svld1sb_u32(svbool_t pg, const int8_t *base) { // CHECK-LABEL: test_svld1sb_u32 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i8.p0nxv4i8(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i8( %[[PG]], i8* %base) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sb_u32(pg, base); @@ -68,9 +63,8 @@ svuint64_t test_svld1sb_u64(svbool_t pg, const int8_t *base) { // CHECK-LABEL: test_svld1sb_u64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i8.p0nxv2i8(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i8( %[[PG]], i8* %base) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sb_u64(pg, base); @@ -81,8 +75,8 @@ // CHECK-LABEL: test_svld1sb_vnum_s16 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv8i8.p0nxv8i8(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv8i8( %[[PG]], i8* %[[GEP]]) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sb_vnum_s16(pg, base, vnum); @@ -93,8 +87,8 @@ // CHECK-LABEL: test_svld1sb_vnum_s32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i8.p0nxv4i8(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i8( %[[PG]], i8* %[[GEP]]) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sb_vnum_s32(pg, base, vnum); @@ -105,8 +99,8 @@ // CHECK-LABEL: test_svld1sb_vnum_s64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i8.p0nxv2i8(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i8( %[[PG]], i8* %[[GEP]]) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sb_vnum_s64(pg, base, vnum); @@ -117,8 +111,8 @@ // CHECK-LABEL: test_svld1sb_vnum_u16 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv8i8.p0nxv8i8(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv8i8( %[[PG]], i8* %[[GEP]]) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sb_vnum_u16(pg, base, vnum); @@ -129,8 +123,8 @@ // CHECK-LABEL: test_svld1sb_vnum_u32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i8.p0nxv4i8(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i8( %[[PG]], i8* %[[GEP]]) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sb_vnum_u32(pg, base, vnum); @@ -141,8 +135,8 @@ // CHECK-LABEL: test_svld1sb_vnum_u64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i8.p0nxv2i8(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i8( %[[PG]], i8* %[[GEP]]) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sb_vnum_u64(pg, base, vnum); diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sh.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sh.c @@ -13,9 +13,8 @@ svint32_t test_svld1sh_s32(svbool_t pg, const int16_t *base) { // CHECK-LABEL: test_svld1sh_s32 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i16.p0nxv4i16(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i16( %[[PG]], i16* %base) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sh_s32(pg, base); @@ -24,9 +23,8 @@ svint64_t test_svld1sh_s64(svbool_t pg, const int16_t *base) { // CHECK-LABEL: test_svld1sh_s64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i16.p0nxv2i16(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i16( %[[PG]], i16* %base) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sh_s64(pg, base); @@ -35,9 +33,8 @@ svuint32_t test_svld1sh_u32(svbool_t pg, const int16_t *base) { // CHECK-LABEL: test_svld1sh_u32 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i16.p0nxv4i16(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i16( %[[PG]], i16* %base) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sh_u32(pg, base); @@ -46,9 +43,8 @@ svuint64_t test_svld1sh_u64(svbool_t pg, const int16_t *base) { // CHECK-LABEL: test_svld1sh_u64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i16.p0nxv2i16(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i16( %[[PG]], i16* %base) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sh_u64(pg, base); @@ -59,8 +55,8 @@ // CHECK-LABEL: test_svld1sh_vnum_s32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i16.p0nxv4i16(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i16( %[[PG]], i16* %[[GEP]]) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sh_vnum_s32(pg, base, vnum); @@ -71,8 +67,8 @@ // CHECK-LABEL: test_svld1sh_vnum_s64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i16.p0nxv2i16(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i16( %[[PG]], i16* %[[GEP]]) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sh_vnum_s64(pg, base, vnum); @@ -83,8 +79,8 @@ // CHECK-LABEL: test_svld1sh_vnum_u32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i16.p0nxv4i16(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i16( %[[PG]], i16* %[[GEP]]) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sh_vnum_u32(pg, base, vnum); @@ -95,8 +91,8 @@ // CHECK-LABEL: test_svld1sh_vnum_u64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i16.p0nxv2i16(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i16( %[[PG]], i16* %[[GEP]]) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sh_vnum_u64(pg, base, vnum); diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sw.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sw.c @@ -13,9 +13,8 @@ svint64_t test_svld1sw_s64(svbool_t pg, const int32_t *base) { // CHECK-LABEL: test_svld1sw_s64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i32.p0nxv2i32(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i32( %[[PG]], i32* %base) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sw_s64(pg, base); @@ -24,9 +23,8 @@ svuint64_t test_svld1sw_u64(svbool_t pg, const int32_t *base) { // CHECK-LABEL: test_svld1sw_u64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i32.p0nxv2i32(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i32( %[[PG]], i32* %base) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sw_u64(pg, base); @@ -37,8 +35,8 @@ // CHECK-LABEL: test_svld1sw_vnum_s64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i32.p0nxv2i32(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i32( %[[PG]], i32* %[[GEP]]) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sw_vnum_s64(pg, base, vnum); @@ -49,8 +47,8 @@ // CHECK-LABEL: test_svld1sw_vnum_u64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i32.p0nxv2i32(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i32( %[[PG]], i32* %[[GEP]]) // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to // CHECK: ret %[[SEXT]] return svld1sw_vnum_u64(pg, base, vnum); diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ub.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ub.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ub.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ub.c @@ -13,9 +13,8 @@ svint16_t test_svld1ub_s16(svbool_t pg, const uint8_t *base) { // CHECK-LABEL: test_svld1ub_s16 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv8i8.p0nxv8i8(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv8i8( %[[PG]], i8* %base) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1ub_s16(pg, base); @@ -24,9 +23,8 @@ svint32_t test_svld1ub_s32(svbool_t pg, const uint8_t *base) { // CHECK-LABEL: test_svld1ub_s32 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i8.p0nxv4i8(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i8( %[[PG]], i8* %base) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1ub_s32(pg, base); @@ -35,9 +33,8 @@ svint64_t test_svld1ub_s64(svbool_t pg, const uint8_t *base) { // CHECK-LABEL: test_svld1ub_s64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i8.p0nxv2i8(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i8( %[[PG]], i8* %base) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1ub_s64(pg, base); @@ -46,9 +43,8 @@ svuint16_t test_svld1ub_u16(svbool_t pg, const uint8_t *base) { // CHECK-LABEL: test_svld1ub_u16 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv8i8.p0nxv8i8(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv8i8( %[[PG]], i8* %base) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1ub_u16(pg, base); @@ -57,9 +53,8 @@ svuint32_t test_svld1ub_u32(svbool_t pg, const uint8_t *base) { // CHECK-LABEL: test_svld1ub_u32 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i8.p0nxv4i8(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i8( %[[PG]], i8* %base) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1ub_u32(pg, base); @@ -68,9 +63,8 @@ svuint64_t test_svld1ub_u64(svbool_t pg, const uint8_t *base) { // CHECK-LABEL: test_svld1ub_u64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i8.p0nxv2i8(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i8( %[[PG]], i8* %base) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1ub_u64(pg, base); @@ -81,8 +75,8 @@ // CHECK-LABEL: test_svld1ub_vnum_s16 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv8i8.p0nxv8i8(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv8i8( %[[PG]], i8* %[[GEP]]) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1ub_vnum_s16(pg, base, vnum); @@ -93,8 +87,8 @@ // CHECK-LABEL: test_svld1ub_vnum_s32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i8.p0nxv4i8(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i8( %[[PG]], i8* %[[GEP]]) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1ub_vnum_s32(pg, base, vnum); @@ -105,8 +99,8 @@ // CHECK-LABEL: test_svld1ub_vnum_s64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i8.p0nxv2i8(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i8( %[[PG]], i8* %[[GEP]]) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1ub_vnum_s64(pg, base, vnum); @@ -117,8 +111,8 @@ // CHECK-LABEL: test_svld1ub_vnum_u16 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv8i8.p0nxv8i8(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv8i8( %[[PG]], i8* %[[GEP]]) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1ub_vnum_u16(pg, base, vnum); @@ -129,8 +123,8 @@ // CHECK-LABEL: test_svld1ub_vnum_u32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i8.p0nxv4i8(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i8( %[[PG]], i8* %[[GEP]]) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1ub_vnum_u32(pg, base, vnum); @@ -141,8 +135,8 @@ // CHECK-LABEL: test_svld1ub_vnum_u64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i8.p0nxv2i8(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i8( %[[PG]], i8* %[[GEP]]) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1ub_vnum_u64(pg, base, vnum); diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uh.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uh.c @@ -13,9 +13,8 @@ svint32_t test_svld1uh_s32(svbool_t pg, const uint16_t *base) { // CHECK-LABEL: test_svld1uh_s32 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i16.p0nxv4i16(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i16( %[[PG]], i16* %base) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1uh_s32(pg, base); @@ -24,9 +23,8 @@ svint64_t test_svld1uh_s64(svbool_t pg, const uint16_t *base) { // CHECK-LABEL: test_svld1uh_s64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i16.p0nxv2i16(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i16( %[[PG]], i16* %base) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1uh_s64(pg, base); @@ -35,9 +33,8 @@ svuint32_t test_svld1uh_u32(svbool_t pg, const uint16_t *base) { // CHECK-LABEL: test_svld1uh_u32 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i16.p0nxv4i16(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i16( %[[PG]], i16* %base) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1uh_u32(pg, base); @@ -46,9 +43,8 @@ svuint64_t test_svld1uh_u64(svbool_t pg, const uint16_t *base) { // CHECK-LABEL: test_svld1uh_u64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i16.p0nxv2i16(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i16( %[[PG]], i16* %base) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1uh_u64(pg, base); @@ -59,8 +55,8 @@ // CHECK-LABEL: test_svld1uh_vnum_s32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i16.p0nxv4i16(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i16( %[[PG]], i16* %[[GEP]]) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1uh_vnum_s32(pg, base, vnum); @@ -71,8 +67,8 @@ // CHECK-LABEL: test_svld1uh_vnum_s64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i16.p0nxv2i16(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i16( %[[PG]], i16* %[[GEP]]) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1uh_vnum_s64(pg, base, vnum); @@ -83,8 +79,8 @@ // CHECK-LABEL: test_svld1uh_vnum_u32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv4i16.p0nxv4i16(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv4i16( %[[PG]], i16* %[[GEP]]) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1uh_vnum_u32(pg, base, vnum); @@ -95,8 +91,8 @@ // CHECK-LABEL: test_svld1uh_vnum_u64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i16.p0nxv2i16(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i16( %[[PG]], i16* %[[GEP]]) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1uh_vnum_u64(pg, base, vnum); diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uw.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uw.c @@ -13,9 +13,8 @@ svint64_t test_svld1uw_s64(svbool_t pg, const uint32_t *base) { // CHECK-LABEL: test_svld1uw_s64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i32.p0nxv2i32(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i32( %[[PG]], i32* %base) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1uw_s64(pg, base); @@ -24,9 +23,8 @@ svuint64_t test_svld1uw_u64(svbool_t pg, const uint32_t *base) { // CHECK-LABEL: test_svld1uw_u64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i32.p0nxv2i32(* %[[BASE]], i32 1, %[[PG]], zeroinitializer) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i32( %[[PG]], i32* %base) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1uw_u64(pg, base); @@ -37,8 +35,8 @@ // CHECK-LABEL: test_svld1uw_vnum_s64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i32.p0nxv2i32(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i32( %[[PG]], i32* %[[GEP]]) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1uw_vnum_s64(pg, base, vnum); @@ -49,8 +47,8 @@ // CHECK-LABEL: test_svld1uw_vnum_u64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: %[[LOAD:.*]] = call @llvm.masked.load.nxv2i32.p0nxv2i32(* %[[GEP]], i32 1, %[[PG]], zeroinitializer) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.nxv2i32( %[[PG]], i32* %[[GEP]]) // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to // CHECK: ret %[[ZEXT]] return svld1uw_vnum_u64(pg, base, vnum); diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1.c @@ -13,106 +13,107 @@ void test_svst1_s8(svbool_t pg, int8_t *base, svint8_t data) { // CHECK-LABEL: test_svst1_s8 - // CHECK: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK: call void @llvm.masked.store.nxv16i8.p0nxv16i8( %data, * %[[BASE]], i32 1, %pg) + // CHECK: call void @llvm.aarch64.sve.st1.nxv16i8( %data, %pg, i8* %base) + // CHECK: ret void return SVE_ACLE_FUNC(svst1,_s8,,)(pg, base, data); } void test_svst1_s16(svbool_t pg, int16_t *base, svint16_t data) { // CHECK-LABEL: test_svst1_s16 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK: call void @llvm.masked.store.nxv8i16.p0nxv8i16( %data, * %[[BASE]], i32 1, %[[PG]]) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK: call void @llvm.aarch64.sve.st1.nxv8i16( %data, %[[PG]], i16* %base) + // CHECK: ret void return SVE_ACLE_FUNC(svst1,_s16,,)(pg, base, data); } void test_svst1_s32(svbool_t pg, int32_t *base, svint32_t data) { // CHECK-LABEL: test_svst1_s32 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * - // CHECK: call void @llvm.masked.store.nxv4i32.p0nxv4i32( %data, * %[[BASE]], i32 1, %[[PG]]) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.st1.nxv4i32( %data, %[[PG]], i32* %base) + // CHECK: ret void return SVE_ACLE_FUNC(svst1,_s32,,)(pg, base, data); } void test_svst1_s64(svbool_t pg, int64_t *base, svint64_t data) { // CHECK-LABEL: test_svst1_s64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to * - // CHECK: call void @llvm.masked.store.nxv2i64.p0nxv2i64( %data, * %[[BASE]], i32 1, %[[PG]]) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.st1.nxv2i64( %data, %[[PG]], i64* %base) + // CHECK: ret void return SVE_ACLE_FUNC(svst1,_s64,,)(pg, base, data); } void test_svst1_u8(svbool_t pg, uint8_t *base, svuint8_t data) { // CHECK-LABEL: test_svst1_u8 - // CHECK: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK: call void @llvm.masked.store.nxv16i8.p0nxv16i8( %data, * %[[BASE]], i32 1, %pg) + // CHECK: call void @llvm.aarch64.sve.st1.nxv16i8( %data, %pg, i8* %base) + // CHECK: ret void return SVE_ACLE_FUNC(svst1,_u8,,)(pg, base, data); } void test_svst1_u16(svbool_t pg, uint16_t *base, svuint16_t data) { // CHECK-LABEL: test_svst1_u16 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK: call void @llvm.masked.store.nxv8i16.p0nxv8i16( %data, * %[[BASE]], i32 1, %[[PG]]) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK: call void @llvm.aarch64.sve.st1.nxv8i16( %data, %[[PG]], i16* %base) + // CHECK: ret void return SVE_ACLE_FUNC(svst1,_u16,,)(pg, base, data); } void test_svst1_u32(svbool_t pg, uint32_t *base, svuint32_t data) { // CHECK-LABEL: test_svst1_u32 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * - // CHECK: call void @llvm.masked.store.nxv4i32.p0nxv4i32( %data, * %[[BASE]], i32 1, %[[PG]]) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.st1.nxv4i32( %data, %[[PG]], i32* %base) + // CHECK: ret void return SVE_ACLE_FUNC(svst1,_u32,,)(pg, base, data); } void test_svst1_u64(svbool_t pg, uint64_t *base, svuint64_t data) { // CHECK-LABEL: test_svst1_u64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to * - // CHECK: call void @llvm.masked.store.nxv2i64.p0nxv2i64( %data, * %[[BASE]], i32 1, %[[PG]]) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.st1.nxv2i64( %data, %[[PG]], i64* %base) + // CHECK: ret void return SVE_ACLE_FUNC(svst1,_u64,,)(pg, base, data); } void test_svst1_f16(svbool_t pg, float16_t *base, svfloat16_t data) { // CHECK-LABEL: test_svst1_f16 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast half* %base to * - // CHECK: call void @llvm.masked.store.nxv8f16.p0nxv8f16( %data, * %[[BASE]], i32 1, %[[PG]]) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK: call void @llvm.aarch64.sve.st1.nxv8f16( %data, %[[PG]], half* %base) + // CHECK: ret void return SVE_ACLE_FUNC(svst1,_f16,,)(pg, base, data); } void test_svst1_f32(svbool_t pg, float32_t *base, svfloat32_t data) { // CHECK-LABEL: test_svst1_f32 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast float* %base to * - // CHECK: call void @llvm.masked.store.nxv4f32.p0nxv4f32( %data, * %[[BASE]], i32 1, %[[PG]]) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.st1.nxv4f32( %data, %[[PG]], float* %base) + // CHECK: ret void return SVE_ACLE_FUNC(svst1,_f32,,)(pg, base, data); } void test_svst1_f64(svbool_t pg, float64_t *base, svfloat64_t data) { // CHECK-LABEL: test_svst1_f64 - // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast double* %base to * - // CHECK: call void @llvm.masked.store.nxv2f64.p0nxv2f64( %data, * %[[BASE]], i32 1, %[[PG]]) + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.st1.nxv2f64( %data, %[[PG]], double* %base) + // CHECK: ret void return SVE_ACLE_FUNC(svst1,_f64,,)(pg, base, data); } void test_svst1_vnum_s8(svbool_t pg, int8_t *base, int64_t vnum, svint8_t data) { // CHECK-LABEL: test_svst1_vnum_s8 - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv16i8.p0nxv16i8( %data, * %[[GEP]], i32 1, %pg) + // CHECK: %[[BASE:.*]] = bitcast i8* %base to * + // CHECK: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv16i8( %data, %pg, i8* %[[GEP]]) + // CHECK: ret void return SVE_ACLE_FUNC(svst1_vnum,_s8,,)(pg, base, vnum, data); } @@ -121,8 +122,9 @@ // CHECK-LABEL: test_svst1_vnum_s16 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv8i16.p0nxv8i16( %data, * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv8i16( %data, %[[PG]], i16* %[[GEP]]) + // CHECK: ret void return SVE_ACLE_FUNC(svst1_vnum,_s16,,)(pg, base, vnum, data); } @@ -131,8 +133,9 @@ // CHECK-LABEL: test_svst1_vnum_s32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv4i32.p0nxv4i32( %data, * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv4i32( %data, %[[PG]], i32* %[[GEP]]) + // CHECK: ret void return SVE_ACLE_FUNC(svst1_vnum,_s32,,)(pg, base, vnum, data); } @@ -141,17 +144,19 @@ // CHECK-LABEL: test_svst1_vnum_s64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv2i64.p0nxv2i64( %data, * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv2i64( %data, %[[PG]], i64* %[[GEP]]) + // CHECK: ret void return SVE_ACLE_FUNC(svst1_vnum,_s64,,)(pg, base, vnum, data); } void test_svst1_vnum_u8(svbool_t pg, uint8_t *base, int64_t vnum, svuint8_t data) { // CHECK-LABEL: test_svst1_vnum_u8 - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv16i8.p0nxv16i8( %data, * %[[GEP]], i32 1, %pg) + // CHECK: %[[BASE:.*]] = bitcast i8* %base to * + // CHECK: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv16i8( %data, %pg, i8* %[[GEP]]) + // CHECK: ret void return SVE_ACLE_FUNC(svst1_vnum,_u8,,)(pg, base, vnum, data); } @@ -160,8 +165,9 @@ // CHECK-LABEL: test_svst1_vnum_u16 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv8i16.p0nxv8i16( %data, * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv8i16( %data, %[[PG]], i16* %[[GEP]]) + // CHECK: ret void return SVE_ACLE_FUNC(svst1_vnum,_u16,,)(pg, base, vnum, data); } @@ -170,8 +176,9 @@ // CHECK-LABEL: test_svst1_vnum_u32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv4i32.p0nxv4i32( %data, * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv4i32( %data, %[[PG]], i32* %[[GEP]]) + // CHECK: ret void return SVE_ACLE_FUNC(svst1_vnum,_u32,,)(pg, base, vnum, data); } @@ -180,8 +187,9 @@ // CHECK-LABEL: test_svst1_vnum_u64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv2i64.p0nxv2i64( %data, * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv2i64( %data, %[[PG]], i64* %[[GEP]]) + // CHECK: ret void return SVE_ACLE_FUNC(svst1_vnum,_u64,,)(pg, base, vnum, data); } @@ -190,8 +198,9 @@ // CHECK-LABEL: test_svst1_vnum_f16 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast half* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv8f16.p0nxv8f16( %data, * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv8f16( %data, %[[PG]], half* %[[GEP]]) + // CHECK: ret void return SVE_ACLE_FUNC(svst1_vnum,_f16,,)(pg, base, vnum, data); } @@ -200,8 +209,9 @@ // CHECK-LABEL: test_svst1_vnum_f32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast float* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv4f32.p0nxv4f32( %data, * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv4f32( %data, %[[PG]], float* %[[GEP]]) + // CHECK: ret void return SVE_ACLE_FUNC(svst1_vnum,_f32,,)(pg, base, vnum, data); } @@ -210,7 +220,7 @@ // CHECK-LABEL: test_svst1_vnum_f64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast double* %base to * - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv2f64.p0nxv2f64( %data, * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv2f64( %data, %[[PG]], double* %[[GEP]]) return SVE_ACLE_FUNC(svst1_vnum,_f64,,)(pg, base, vnum, data); } diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1b.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1b.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1b.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1b.c @@ -14,9 +14,8 @@ { // CHECK-LABEL: test_svst1b_s16 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK: call void @llvm.masked.store.nxv8i8.p0nxv8i8( %[[DATA]], * %[[BASE]], i32 1, %[[PG]]) + // CHECK: call void @llvm.aarch64.sve.st1.nxv8i8( %[[DATA]], %[[PG]], i8* %base) // CHECK: ret void return SVE_ACLE_FUNC(svst1b,_s16,,)(pg, base, data); } @@ -25,9 +24,8 @@ { // CHECK-LABEL: test_svst1b_s32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK: call void @llvm.masked.store.nxv4i8.p0nxv4i8( %[[DATA]], * %[[BASE]], i32 1, %[[PG]]) + // CHECK: call void @llvm.aarch64.sve.st1.nxv4i8( %[[DATA]], %[[PG]], i8* %base) // CHECK: ret void return SVE_ACLE_FUNC(svst1b,_s32,,)(pg, base, data); } @@ -36,9 +34,8 @@ { // CHECK-LABEL: test_svst1b_s64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK: call void @llvm.masked.store.nxv2i8.p0nxv2i8( %[[DATA]], * %[[BASE]], i32 1, %[[PG]]) + // CHECK: call void @llvm.aarch64.sve.st1.nxv2i8( %[[DATA]], %[[PG]], i8* %base) // CHECK: ret void return SVE_ACLE_FUNC(svst1b,_s64,,)(pg, base, data); } @@ -47,9 +44,8 @@ { // CHECK-LABEL: test_svst1b_u16 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK: call void @llvm.masked.store.nxv8i8.p0nxv8i8( %[[DATA]], * %[[BASE]], i32 1, %[[PG]]) + // CHECK: call void @llvm.aarch64.sve.st1.nxv8i8( %[[DATA]], %[[PG]], i8* %base) // CHECK: ret void return SVE_ACLE_FUNC(svst1b,_u16,,)(pg, base, data); } @@ -58,9 +54,8 @@ { // CHECK-LABEL: test_svst1b_u32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK: call void @llvm.masked.store.nxv4i8.p0nxv4i8( %[[DATA]], * %[[BASE]], i32 1, %[[PG]]) + // CHECK: call void @llvm.aarch64.sve.st1.nxv4i8( %[[DATA]], %[[PG]], i8* %base) // CHECK: ret void return SVE_ACLE_FUNC(svst1b,_u32,,)(pg, base, data); } @@ -69,9 +64,8 @@ { // CHECK-LABEL: test_svst1b_u64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK: call void @llvm.masked.store.nxv2i8.p0nxv2i8( %[[DATA]], * %[[BASE]], i32 1, %[[PG]]) + // CHECK: call void @llvm.aarch64.sve.st1.nxv2i8( %[[DATA]], %[[PG]], i8* %base) // CHECK: ret void return SVE_ACLE_FUNC(svst1b,_u64,,)(pg, base, data); } @@ -82,8 +76,8 @@ // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv8i8.p0nxv8i8( %[[DATA]], * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv8i8( %[[DATA]], %[[PG]], i8* %[[GEP]]) // CHECK: ret void return SVE_ACLE_FUNC(svst1b_vnum,_s16,,)(pg, base, vnum, data); } @@ -94,8 +88,8 @@ // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv4i8.p0nxv4i8( %[[DATA]], * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv4i8( %[[DATA]], %[[PG]], i8* %[[GEP]]) // CHECK: ret void return SVE_ACLE_FUNC(svst1b_vnum,_s32,,)(pg, base, vnum, data); } @@ -106,8 +100,8 @@ // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv2i8.p0nxv2i8( %[[DATA]], * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv2i8( %[[DATA]], %[[PG]], i8* %[[GEP]]) // CHECK: ret void return SVE_ACLE_FUNC(svst1b_vnum,_s64,,)(pg, base, vnum, data); } @@ -118,8 +112,8 @@ // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv8i8.p0nxv8i8( %[[DATA]], * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv8i8( %[[DATA]], %[[PG]], i8* %[[GEP]]) // CHECK: ret void return SVE_ACLE_FUNC(svst1b_vnum,_u16,,)(pg, base, vnum, data); } @@ -130,8 +124,8 @@ // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv4i8.p0nxv4i8( %[[DATA]], * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv4i8( %[[DATA]], %[[PG]], i8* %[[GEP]]) // CHECK: ret void return SVE_ACLE_FUNC(svst1b_vnum,_u32,,)(pg, base, vnum, data); } @@ -142,8 +136,8 @@ // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv2i8.p0nxv2i8( %[[DATA]], * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv2i8( %[[DATA]], %[[PG]], i8* %[[GEP]]) // CHECK: ret void return SVE_ACLE_FUNC(svst1b_vnum,_u64,,)(pg, base, vnum, data); } diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1h.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1h.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1h.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1h.c @@ -14,9 +14,8 @@ { // CHECK-LABEL: test_svst1h_s32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK: call void @llvm.masked.store.nxv4i16.p0nxv4i16( %[[DATA]], * %[[BASE]], i32 1, %[[PG]]) + // CHECK: call void @llvm.aarch64.sve.st1.nxv4i16( %[[DATA]], %[[PG]], i16* %base) // CHECK: ret void return SVE_ACLE_FUNC(svst1h,_s32,,)(pg, base, data); } @@ -25,9 +24,8 @@ { // CHECK-LABEL: test_svst1h_s64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK: call void @llvm.masked.store.nxv2i16.p0nxv2i16( %[[DATA]], * %[[BASE]], i32 1, %[[PG]]) + // CHECK: call void @llvm.aarch64.sve.st1.nxv2i16( %[[DATA]], %[[PG]], i16* %base) // CHECK: ret void return SVE_ACLE_FUNC(svst1h,_s64,,)(pg, base, data); } @@ -36,9 +34,8 @@ { // CHECK-LABEL: test_svst1h_u32 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK: call void @llvm.masked.store.nxv4i16.p0nxv4i16( %[[DATA]], * %[[BASE]], i32 1, %[[PG]]) + // CHECK: call void @llvm.aarch64.sve.st1.nxv4i16( %[[DATA]], %[[PG]], i16* %base) // CHECK: ret void return SVE_ACLE_FUNC(svst1h,_u32,,)(pg, base, data); } @@ -47,9 +44,8 @@ { // CHECK-LABEL: test_svst1h_u64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK: call void @llvm.masked.store.nxv2i16.p0nxv2i16( %[[DATA]], * %[[BASE]], i32 1, %[[PG]]) + // CHECK: call void @llvm.aarch64.sve.st1.nxv2i16( %[[DATA]], %[[PG]], i16* %base) // CHECK: ret void return SVE_ACLE_FUNC(svst1h,_u64,,)(pg, base, data); } @@ -60,8 +56,8 @@ // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv4i16.p0nxv4i16( %[[DATA]], * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv4i16( %[[DATA]], %[[PG]], i16* %[[GEP]]) // CHECK: ret void return SVE_ACLE_FUNC(svst1h_vnum,_s32,,)(pg, base, vnum, data); } @@ -72,8 +68,8 @@ // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv2i16.p0nxv2i16( %[[DATA]], * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv2i16( %[[DATA]], %[[PG]], i16* %[[GEP]]) // CHECK: ret void return SVE_ACLE_FUNC(svst1h_vnum,_s64,,)(pg, base, vnum, data); } @@ -84,8 +80,8 @@ // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv4i16.p0nxv4i16( %[[DATA]], * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv4i16( %[[DATA]], %[[PG]], i16* %[[GEP]]) // CHECK: ret void return SVE_ACLE_FUNC(svst1h_vnum,_u32,,)(pg, base, vnum, data); } @@ -96,8 +92,8 @@ // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv2i16.p0nxv2i16( %[[DATA]], * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv2i16( %[[DATA]], %[[PG]], i16* %[[GEP]]) // CHECK: ret void return SVE_ACLE_FUNC(svst1h_vnum,_u64,,)(pg, base, vnum, data); } diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1w.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1w.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1w.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1w.c @@ -14,9 +14,8 @@ { // CHECK-LABEL: test_svst1w_s64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK: call void @llvm.masked.store.nxv2i32.p0nxv2i32( %[[DATA]], * %[[BASE]], i32 1, %[[PG]]) + // CHECK: call void @llvm.aarch64.sve.st1.nxv2i32( %[[DATA]], %[[PG]], i32* %base) // CHECK: ret void return SVE_ACLE_FUNC(svst1w,_s64,,)(pg, base, data); } @@ -25,9 +24,8 @@ { // CHECK-LABEL: test_svst1w_u64 // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) - // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK: call void @llvm.masked.store.nxv2i32.p0nxv2i32( %[[DATA]], * %[[BASE]], i32 1, %[[PG]]) + // CHECK: call void @llvm.aarch64.sve.st1.nxv2i32( %[[DATA]], %[[PG]], i32* %base) // CHECK: ret void return SVE_ACLE_FUNC(svst1w,_u64,,)(pg, base, data); } @@ -38,8 +36,8 @@ // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv2i32.p0nxv2i32( %[[DATA]], * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv2i32( %[[DATA]], %[[PG]], i32* %[[GEP]]) // CHECK: ret void return SVE_ACLE_FUNC(svst1w_vnum,_s64,,)(pg, base, vnum, data); } @@ -50,8 +48,8 @@ // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to * // CHECK-DAG: %[[DATA:.*]] = trunc %data to - // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum - // CHECK: call void @llvm.masked.store.nxv2i32.p0nxv2i32( %[[DATA]], * %[[GEP]], i32 1, %[[PG]]) + // CHECK-DAG: %[[GEP:.*]] = getelementptr , * %[[BASE]], i64 %vnum, i64 0 + // CHECK: call void @llvm.aarch64.sve.st1.nxv2i32( %[[DATA]], %[[PG]], i32* %[[GEP]]) // CHECK: ret void return SVE_ACLE_FUNC(svst1w_vnum,_u64,,)(pg, base, vnum, data); }