diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp
--- a/llvm/lib/CodeGen/LiveIntervals.cpp
+++ b/llvm/lib/CodeGen/LiveIntervals.cpp
@@ -862,6 +862,11 @@
 float LiveIntervals::getSpillWeight(bool isDef, bool isUse,
                                     const MachineBlockFrequencyInfo *MBFI,
                                     const MachineInstr &MI) {
+  // FIXME: Is there place to add the check better than here?
+  // The pass x86-slh attached an post instruction symbol to call instruction.
+  // We don't want its register been spilt out.
+  if (MI.isCall() && MI.getPostInstrSymbol())
+    return huge_valf;
   return getSpillWeight(isDef, isUse, MBFI, MI.getParent());
 }
 
diff --git a/llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll b/llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll
--- a/llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll
+++ b/llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll
@@ -2,8 +2,8 @@
 
 define i32 @foo(void ()** %0) {
 ; CHECK-LABEL: foo:
-; CHECK-NOT:    .Lslh_ret_addr0:
-; CHECK:         callq *(%{{.*}})
+; CHECK:         callq *%{{.*}}
+; CHECK-NEXT:  .Lslh_ret_addr0:
 ; CHECK-NEXT:    movq %rsp, %rcx
 ; CHECK-NEXT:    movq -{{[0-9]+}}(%rsp), %rax
 ; CHECK-NEXT:    sarq $63, %rcx