diff --git a/clang/include/clang/Basic/TargetBuiltins.h b/clang/include/clang/Basic/TargetBuiltins.h
--- a/clang/include/clang/Basic/TargetBuiltins.h
+++ b/clang/include/clang/Basic/TargetBuiltins.h
@@ -238,7 +238,6 @@
     bool isOverloadDefault() const { return !(Flags & OverloadKindMask); }
     bool isOverloadWhileRW() const { return Flags & IsOverloadWhileRW; }
     bool isOverloadCvt() const { return Flags & IsOverloadCvt; }
-    bool isFPConvert() const { return Flags & IsFPConvert; }
 
     uint64_t getBits() const { return Flags; }
     bool isFlagSet(uint64_t Flag) const { return Flags & Flag; }
diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -74,10 +74,13 @@
 // l: int64_t
 // m: uint32_t
 // n: uint64_t
-//
-// I: Predicate Pattern (sv_pattern)
 
-// l: int64_t
+// t: svint32_t
+// z: svuint32_t
+// g: svuint64_t
+// O: svfloat16_t
+// M: svfloat32_t
+// N: svfloat64_t
 
 // A: pointer to int8_t
 // B: pointer to int16_t
@@ -173,7 +176,6 @@
 def IsOverloadCvt             : FlagType<0x00800000>; // Use {typeof(operand0), typeof(last operand)} as overloaded types.
 def OverloadKindMask          : FlagType<0x00E00000>; // When the masked values are all '0', the default type is used as overload type.
 def IsByteIndexed             : FlagType<0x01000000>;
-def IsFPConvert               : FlagType<0x02000000>;
 
 // These must be kept in sync with the flags in include/clang/Basic/TargetBuiltins.h
 class ImmCheckType<int val> {
@@ -558,7 +560,7 @@
 
 multiclass SInstCvtMXZ<
     string name, string m_types, string xz_types, string types,
-    string intrinsic, list<FlagType> flags = [IsFPConvert, IsOverloadNone]> {
+    string intrinsic, list<FlagType> flags = [IsOverloadNone]> {
   def _M : SInst<name, m_types,  types, MergeOp1,     intrinsic, flags>;
   def _X : SInst<name, xz_types, types, MergeAnyExp,  intrinsic, flags>;
   def _Z : SInst<name, xz_types, types, MergeZeroExp, intrinsic, flags>;
@@ -566,7 +568,7 @@
 
 multiclass SInstCvtMX<string name, string m_types, string xz_types,
                       string types, string intrinsic,
-                      list<FlagType> flags = [IsFPConvert, IsOverloadNone]> {
+                      list<FlagType> flags = [IsOverloadNone]> {
   def _M : SInst<name, m_types,  types, MergeOp1,     intrinsic, flags>;
   def _X : SInst<name, xz_types, types, MergeAnyExp,  intrinsic, flags>;
 }
@@ -581,7 +583,7 @@
 defm SVFCVTZS_S64_F32 : SInstCvtMXZ<"svcvt_s64[_f32]", "ddPM", "dPM", "l",  "aarch64_sve_fcvtzs_i64f32">;
 
 // svcvt_s##_f64
-defm SVFCVTZS_S32_F64 : SInstCvtMXZ<"svcvt_s32[_f64]", "ddPN", "dPN", "i",  "aarch64_sve_fcvtzs_i32f64">;
+defm SVFCVTZS_S32_F64 : SInstCvtMXZ<"svcvt_s32[_f64]", "ttPd", "tPd", "d",  "aarch64_sve_fcvtzs_i32f64">;
 defm SVFCVTZS_S64_F64 : SInstCvtMXZ<"svcvt_s64[_f64]", "ddPN", "dPN", "l",  "aarch64_sve_fcvtzs", [IsOverloadCvt]>;
 
 // svcvt_u##_f16
@@ -594,7 +596,7 @@
 defm SVFCVTZU_U64_F32 : SInstCvtMXZ<"svcvt_u64[_f32]", "ddPM", "dPM", "Ul", "aarch64_sve_fcvtzu_i64f32">;
 
 // svcvt_u##_f64
-defm SVFCVTZU_U32_F64 : SInstCvtMXZ<"svcvt_u32[_f64]", "ddPN", "dPN", "Ui", "aarch64_sve_fcvtzu_i32f64">;
+defm SVFCVTZU_U32_F64 : SInstCvtMXZ<"svcvt_u32[_f64]", "zzPd", "zPd", "d",  "aarch64_sve_fcvtzu_i32f64">;
 defm SVFCVTZU_U64_F64 : SInstCvtMXZ<"svcvt_u64[_f64]", "ddPN", "dPN", "Ul", "aarch64_sve_fcvtzu", [IsOverloadCvt]>;
 
 // svcvt_f16_s##
@@ -607,7 +609,7 @@
 defm SVFCVTZS_F32_S64 : SInstCvtMXZ<"svcvt_f32[_s64]", "MMPd", "MPd", "l",  "aarch64_sve_scvtf_f32i64">;
 
 // svcvt_f64_s##
-defm SVFCVTZS_F64_S32 : SInstCvtMXZ<"svcvt_f64[_s32]", "NNPd", "NPd", "i",  "aarch64_sve_scvtf_f64i32">;
+defm SVFCVTZS_F64_S32 : SInstCvtMXZ<"svcvt_f64[_s32]", "ddPt", "dPt", "d",  "aarch64_sve_scvtf_f64i32">;
 defm SVFCVTZS_F64_S64 : SInstCvtMXZ<"svcvt_f64[_s64]", "NNPd", "NPd", "l",  "aarch64_sve_scvtf", [IsOverloadCvt]>;
 
 // svcvt_f16_u##
@@ -620,7 +622,7 @@
 defm SVFCVTZU_F32_U64 : SInstCvtMXZ<"svcvt_f32[_u64]", "MMPd", "MPd", "Ul", "aarch64_sve_ucvtf_f32i64">;
 
 // svcvt_f64_u##
-defm SVFCVTZU_F64_U32 : SInstCvtMXZ<"svcvt_f64[_u32]", "NNPd", "NPd", "Ui", "aarch64_sve_ucvtf_f64i32">;
+defm SVFCVTZU_F64_U32 : SInstCvtMXZ<"svcvt_f64[_u32]", "ddPz", "dPz", "d",  "aarch64_sve_ucvtf_f64i32">;
 defm SVFCVTZU_F64_U64 : SInstCvtMXZ<"svcvt_f64[_u64]", "NNPd", "NPd", "Ul", "aarch64_sve_ucvtf", [IsOverloadCvt]>;
 
 // svcvt_f16_f##
@@ -628,12 +630,12 @@
 defm SVFCVT_F16_F64   : SInstCvtMXZ<"svcvt_f16[_f64]", "OOPd", "OPd", "d", "aarch64_sve_fcvt_f16f64">;
 
 // svcvt_f32_f##
-defm SVFCVT_F32_F16   : SInstCvtMXZ<"svcvt_f32[_f16]", "MMPd", "MPd", "h", "aarch64_sve_fcvt_f32f16">;
+defm SVFCVT_F32_F16   : SInstCvtMXZ<"svcvt_f32[_f16]", "ddPO", "dPO", "f", "aarch64_sve_fcvt_f32f16">;
 defm SVFCVT_F32_F64   : SInstCvtMXZ<"svcvt_f32[_f64]", "MMPd", "MPd", "d", "aarch64_sve_fcvt_f32f64">;
 
 // svcvt_f64_f##
-defm SVFCVT_F64_F16   : SInstCvtMXZ<"svcvt_f64[_f16]", "NNPd", "NPd", "h", "aarch64_sve_fcvt_f64f16">;
-defm SVFCVT_F64_F32   : SInstCvtMXZ<"svcvt_f64[_f32]", "NNPd", "NPd", "f", "aarch64_sve_fcvt_f64f32">;
+defm SVFCVT_F64_F16   : SInstCvtMXZ<"svcvt_f64[_f16]", "ddPO", "dPO", "d", "aarch64_sve_fcvt_f64f16">;
+defm SVFCVT_F64_F32   : SInstCvtMXZ<"svcvt_f64[_f32]", "ddPM", "dPM", "d", "aarch64_sve_fcvt_f64f32">;
 
 let ArchGuard = "defined(__ARM_FEATURE_SVE2)" in {
 defm SVCVTLT_F32    : SInstCvtMX<"svcvtlt_f32[_f16]",  "ddPh", "dPh", "f", "aarch64_sve_fcvtlt_f32f16">;
@@ -641,11 +643,11 @@
 
 defm SVCVTX_F32     : SInstCvtMXZ<"svcvtx_f32[_f64]",  "MMPd", "MPd", "d", "aarch64_sve_fcvtx_f32f64">;
 
-def SVCVTNT_F32     : SInst<"svcvtnt_f16[_f32]",  "hhPd", "f", MergeOp1, "aarch64_sve_fcvtnt_f16f32">;
-def SVCVTNT_F64     : SInst<"svcvtnt_f32[_f64]",  "hhPd", "d", MergeOp1, "aarch64_sve_fcvtnt_f32f64">;
+def SVCVTNT_F32     : SInst<"svcvtnt_f16[_f32]",  "hhPd", "f", MergeOp1, "aarch64_sve_fcvtnt_f16f32", [IsOverloadNone]>;
+def SVCVTNT_F64     : SInst<"svcvtnt_f32[_f64]",  "hhPd", "d", MergeOp1, "aarch64_sve_fcvtnt_f32f64", [IsOverloadNone]>;
 //  SVCVTNT_X       : Implemented as macro by SveEmitter.cpp
 
-def SVCVTXNT_F32    : SInst<"svcvtxnt_f32[_f64]", "MMPd", "d", MergeOp1, "aarch64_sve_fcvtxnt_f32f64">;
+def SVCVTXNT_F32    : SInst<"svcvtxnt_f32[_f64]", "MMPd", "d", MergeOp1, "aarch64_sve_fcvtxnt_f32f64", [IsOverloadNone]>;
 //  SVCVTXNT_X_F32  : Implemented as macro by SveEmitter.cpp
 
 }
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -7868,18 +7868,8 @@
     // Predicates must match the main datatype.
     for (unsigned i = 0, e = Ops.size(); i != e; ++i)
       if (auto PredTy = dyn_cast<llvm::VectorType>(Ops[i]->getType()))
-        if (PredTy->getElementType()->isIntegerTy(1)) {
-          // The special case for `isFPConvert` is because the predicates of the
-          // ACLE IR intrinsics for FP converts are always of type <vscale x 16 x i1>.
-          // This special-case will be removed in a follow-up patch that updates
-          // the FP conversion intrinsics with predicates that match the
-          // default type.
-          llvm::VectorType *NewPredTy =
-              TypeFlags.isFPConvert()
-                  ? llvm::VectorType::get(Builder.getInt1Ty(), {16, true})
-                  : getSVEType(TypeFlags);
-          Ops[i] = EmitSVEPredicateCast(Ops[i], NewPredTy);
-        }
+        if (PredTy->getElementType()->isIntegerTy(1))
+          Ops[i] = EmitSVEPredicateCast(Ops[i], getSVEType(TypeFlags));
 
     // Splat scalar operand to vector (intrinsics with _n infix)
     if (TypeFlags.hasSplatOperand()) {
diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt.c
--- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt.c
+++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt.c
@@ -67,7 +67,8 @@
 svint32_t test_svcvt_s32_f16_z(svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_s32_f16_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_s32,_f16,_z,)(pg, op);
 }
@@ -84,7 +85,8 @@
 svint32_t test_svcvt_s32_f64_z(svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvt_s32_f64_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_s32,_f64,_z,)(pg, op);
 }
@@ -92,7 +94,8 @@
 svint32_t test_svcvt_s32_f16_m(svint32_t inactive, svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_s32_f16_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> %inactive, <vscale x 4 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_s32,_f16,_m,)(inactive, pg, op);
 }
@@ -109,7 +112,8 @@
 svint32_t test_svcvt_s32_f64_m(svint32_t inactive, svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvt_s32_f64_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_s32,_f64,_m,)(inactive, pg, op);
 }
@@ -117,7 +121,8 @@
 svint32_t test_svcvt_s32_f16_x(svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_s32_f16_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> undef, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> undef, <vscale x 4 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_s32,_f16,_x,)(pg, op);
 }
@@ -134,7 +139,8 @@
 svint32_t test_svcvt_s32_f64_x(svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvt_s32_f64_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> undef, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> undef, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_s32,_f64,_x,)(pg, op);
 }
@@ -142,7 +148,8 @@
 svint64_t test_svcvt_s64_f16_z(svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_s64_f16_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f16(<vscale x 2 x i64> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f16(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_s64,_f16,_z,)(pg, op);
 }
@@ -150,7 +157,8 @@
 svint64_t test_svcvt_s64_f32_z(svbool_t pg, svfloat32_t op)
 {
   // CHECK-LABEL: test_svcvt_s64_f32_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f32(<vscale x 2 x i64> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f32(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 4 x float> %op)
   // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_s64,_f32,_z,)(pg, op);
 }
@@ -167,7 +175,8 @@
 svint64_t test_svcvt_s64_f16_m(svint64_t inactive, svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_s64_f16_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f16(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f16(<vscale x 2 x i64> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_s64,_f16,_m,)(inactive, pg, op);
 }
@@ -175,7 +184,8 @@
 svint64_t test_svcvt_s64_f32_m(svint64_t inactive, svbool_t pg, svfloat32_t op)
 {
   // CHECK-LABEL: test_svcvt_s64_f32_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f32(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f32(<vscale x 2 x i64> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 4 x float> %op)
   // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_s64,_f32,_m,)(inactive, pg, op);
 }
@@ -192,7 +202,8 @@
 svint64_t test_svcvt_s64_f16_x(svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_s64_f16_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f16(<vscale x 2 x i64> undef, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f16(<vscale x 2 x i64> undef, <vscale x 2 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_s64,_f16,_x,)(pg, op);
 }
@@ -200,7 +211,8 @@
 svint64_t test_svcvt_s64_f32_x(svbool_t pg, svfloat32_t op)
 {
   // CHECK-LABEL: test_svcvt_s64_f32_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f32(<vscale x 2 x i64> undef, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f32(<vscale x 2 x i64> undef, <vscale x 2 x i1> %[[PG]], <vscale x 4 x float> %op)
   // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_s64,_f32,_x,)(pg, op);
 }
@@ -217,7 +229,8 @@
 svuint32_t test_svcvt_u32_f16_z(svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_u32_f16_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f16(<vscale x 4 x i32> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f16(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_u32,_f16,_z,)(pg, op);
 }
@@ -234,7 +247,8 @@
 svuint32_t test_svcvt_u32_f64_z(svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvt_u32_f64_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f64(<vscale x 4 x i32> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f64(<vscale x 4 x i32> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_u32,_f64,_z,)(pg, op);
 }
@@ -242,7 +256,8 @@
 svuint32_t test_svcvt_u32_f16_m(svuint32_t inactive, svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_u32_f16_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f16(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f16(<vscale x 4 x i32> %inactive, <vscale x 4 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_u32,_f16,_m,)(inactive, pg, op);
 }
@@ -259,7 +274,8 @@
 svuint32_t test_svcvt_u32_f64_m(svuint32_t inactive, svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvt_u32_f64_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f64(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f64(<vscale x 4 x i32> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_u32,_f64,_m,)(inactive, pg, op);
 }
@@ -267,7 +283,8 @@
 svuint32_t test_svcvt_u32_f16_x(svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_u32_f16_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f16(<vscale x 4 x i32> undef, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f16(<vscale x 4 x i32> undef, <vscale x 4 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_u32,_f16,_x,)(pg, op);
 }
@@ -284,7 +301,8 @@
 svuint32_t test_svcvt_u32_f64_x(svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvt_u32_f64_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f64(<vscale x 4 x i32> undef, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f64(<vscale x 4 x i32> undef, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_u32,_f64,_x,)(pg, op);
 }
@@ -292,7 +310,8 @@
 svuint64_t test_svcvt_u64_f16_z(svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_u64_f16_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f16(<vscale x 2 x i64> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f16(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_u64,_f16,_z,)(pg, op);
 }
@@ -300,7 +319,8 @@
 svuint64_t test_svcvt_u64_f32_z(svbool_t pg, svfloat32_t op)
 {
   // CHECK-LABEL: test_svcvt_u64_f32_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f32(<vscale x 2 x i64> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f32(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 4 x float> %op)
   // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_u64,_f32,_z,)(pg, op);
 }
@@ -317,7 +337,8 @@
 svuint64_t test_svcvt_u64_f16_m(svuint64_t inactive, svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_u64_f16_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f16(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f16(<vscale x 2 x i64> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_u64,_f16,_m,)(inactive, pg, op);
 }
@@ -325,7 +346,8 @@
 svuint64_t test_svcvt_u64_f32_m(svuint64_t inactive, svbool_t pg, svfloat32_t op)
 {
   // CHECK-LABEL: test_svcvt_u64_f32_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f32(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f32(<vscale x 2 x i64> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 4 x float> %op)
   // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_u64,_f32,_m,)(inactive, pg, op);
 }
@@ -342,7 +364,8 @@
 svuint64_t test_svcvt_u64_f16_x(svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_u64_f16_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f16(<vscale x 2 x i64> undef, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f16(<vscale x 2 x i64> undef, <vscale x 2 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_u64,_f16,_x,)(pg, op);
 }
@@ -350,7 +373,8 @@
 svuint64_t test_svcvt_u64_f32_x(svbool_t pg, svfloat32_t op)
 {
   // CHECK-LABEL: test_svcvt_u64_f32_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f32(<vscale x 2 x i64> undef, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f32(<vscale x 2 x i64> undef, <vscale x 2 x i1> %[[PG]], <vscale x 4 x float> %op)
   // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_u64,_f32,_x,)(pg, op);
 }
@@ -367,7 +391,8 @@
 svfloat16_t test_svcvt_f16_s32_z(svbool_t pg, svint32_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_s32_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i32(<vscale x 8 x half> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i32(<vscale x 8 x half> zeroinitializer, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_s32,_z,)(pg, op);
 }
@@ -384,7 +409,8 @@
 svfloat64_t test_svcvt_f64_s32_z(svbool_t pg, svint32_t op)
 {
   // CHECK-LABEL: test_svcvt_f64_s32_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.scvtf.f64i32(<vscale x 2 x double> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.scvtf.f64i32(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 4 x i32> %op)
   // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f64,_s32,_z,)(pg, op);
 }
@@ -392,7 +418,8 @@
 svfloat16_t test_svcvt_f16_s32_m(svfloat16_t inactive, svbool_t pg, svint32_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_s32_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i32(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i32(<vscale x 8 x half> %inactive, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_s32,_m,)(inactive, pg, op);
 }
@@ -409,7 +436,8 @@
 svfloat64_t test_svcvt_f64_s32_m(svfloat64_t inactive, svbool_t pg, svint32_t op)
 {
   // CHECK-LABEL: test_svcvt_f64_s32_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.scvtf.f64i32(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.scvtf.f64i32(<vscale x 2 x double> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 4 x i32> %op)
   // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f64,_s32,_m,)(inactive, pg, op);
 }
@@ -417,7 +445,8 @@
 svfloat16_t test_svcvt_f16_s32_x(svbool_t pg, svint32_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_s32_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i32(<vscale x 8 x half> undef, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i32(<vscale x 8 x half> undef, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_s32,_x,)(pg, op);
 }
@@ -434,7 +463,8 @@
 svfloat64_t test_svcvt_f64_s32_x(svbool_t pg, svint32_t op)
 {
   // CHECK-LABEL: test_svcvt_f64_s32_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.scvtf.f64i32(<vscale x 2 x double> undef, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.scvtf.f64i32(<vscale x 2 x double> undef, <vscale x 2 x i1> %[[PG]], <vscale x 4 x i32> %op)
   // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f64,_s32,_x,)(pg, op);
 }
@@ -442,7 +472,8 @@
 svfloat16_t test_svcvt_f16_s64_z(svbool_t pg, svint64_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_s64_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i64(<vscale x 8 x half> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i64(<vscale x 8 x half> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_s64,_z,)(pg, op);
 }
@@ -450,7 +481,8 @@
 svfloat32_t test_svcvt_f32_s64_z(svbool_t pg, svint64_t op)
 {
   // CHECK-LABEL: test_svcvt_f32_s64_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.scvtf.f32i64(<vscale x 4 x float> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.scvtf.f32i64(<vscale x 4 x float> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f32,_s64,_z,)(pg, op);
 }
@@ -467,7 +499,8 @@
 svfloat16_t test_svcvt_f16_s64_m(svfloat16_t inactive, svbool_t pg, svint64_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_s64_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i64(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i64(<vscale x 8 x half> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_s64,_m,)(inactive, pg, op);
 }
@@ -475,7 +508,8 @@
 svfloat32_t test_svcvt_f32_s64_m(svfloat32_t inactive, svbool_t pg, svint64_t op)
 {
   // CHECK-LABEL: test_svcvt_f32_s64_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.scvtf.f32i64(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.scvtf.f32i64(<vscale x 4 x float> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f32,_s64,_m,)(inactive, pg, op);
 }
@@ -492,7 +526,8 @@
 svfloat16_t test_svcvt_f16_s64_x(svbool_t pg, svint64_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_s64_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i64(<vscale x 8 x half> undef, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i64(<vscale x 8 x half> undef, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_s64,_x,)(pg, op);
 }
@@ -500,7 +535,8 @@
 svfloat32_t test_svcvt_f32_s64_x(svbool_t pg, svint64_t op)
 {
   // CHECK-LABEL: test_svcvt_f32_s64_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.scvtf.f32i64(<vscale x 4 x float> undef, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.scvtf.f32i64(<vscale x 4 x float> undef, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f32,_s64,_x,)(pg, op);
 }
@@ -517,7 +553,8 @@
 svfloat16_t test_svcvt_f16_u32_z(svbool_t pg, svuint32_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_u32_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i32(<vscale x 8 x half> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i32(<vscale x 8 x half> zeroinitializer, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_u32,_z,)(pg, op);
 }
@@ -534,7 +571,8 @@
 svfloat64_t test_svcvt_f64_u32_z(svbool_t pg, svuint32_t op)
 {
   // CHECK-LABEL: test_svcvt_f64_u32_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.ucvtf.f64i32(<vscale x 2 x double> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.ucvtf.f64i32(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 4 x i32> %op)
   // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f64,_u32,_z,)(pg, op);
 }
@@ -542,7 +580,8 @@
 svfloat16_t test_svcvt_f16_u32_m(svfloat16_t inactive, svbool_t pg, svuint32_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_u32_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i32(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i32(<vscale x 8 x half> %inactive, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_u32,_m,)(inactive, pg, op);
 }
@@ -559,7 +598,8 @@
 svfloat64_t test_svcvt_f64_u32_m(svfloat64_t inactive, svbool_t pg, svuint32_t op)
 {
   // CHECK-LABEL: test_svcvt_f64_u32_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.ucvtf.f64i32(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.ucvtf.f64i32(<vscale x 2 x double> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 4 x i32> %op)
   // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f64,_u32,_m,)(inactive, pg, op);
 }
@@ -567,7 +607,8 @@
 svfloat16_t test_svcvt_f16_u32_x(svbool_t pg, svuint32_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_u32_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i32(<vscale x 8 x half> undef, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i32(<vscale x 8 x half> undef, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_u32,_x,)(pg, op);
 }
@@ -584,7 +625,8 @@
 svfloat64_t test_svcvt_f64_u32_x(svbool_t pg, svuint32_t op)
 {
   // CHECK-LABEL: test_svcvt_f64_u32_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.ucvtf.f64i32(<vscale x 2 x double> undef, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.ucvtf.f64i32(<vscale x 2 x double> undef, <vscale x 2 x i1> %[[PG]], <vscale x 4 x i32> %op)
   // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f64,_u32,_x,)(pg, op);
 }
@@ -592,7 +634,8 @@
 svfloat16_t test_svcvt_f16_u64_z(svbool_t pg, svuint64_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_u64_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i64(<vscale x 8 x half> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i64(<vscale x 8 x half> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_u64,_z,)(pg, op);
 }
@@ -600,7 +643,8 @@
 svfloat32_t test_svcvt_f32_u64_z(svbool_t pg, svuint64_t op)
 {
   // CHECK-LABEL: test_svcvt_f32_u64_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.ucvtf.f32i64(<vscale x 4 x float> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.ucvtf.f32i64(<vscale x 4 x float> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f32,_u64,_z,)(pg, op);
 }
@@ -617,7 +661,8 @@
 svfloat16_t test_svcvt_f16_u64_m(svfloat16_t inactive, svbool_t pg, svuint64_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_u64_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i64(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i64(<vscale x 8 x half> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_u64,_m,)(inactive, pg, op);
 }
@@ -625,7 +670,8 @@
 svfloat32_t test_svcvt_f32_u64_m(svfloat32_t inactive, svbool_t pg, svuint64_t op)
 {
   // CHECK-LABEL: test_svcvt_f32_u64_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.ucvtf.f32i64(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.ucvtf.f32i64(<vscale x 4 x float> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f32,_u64,_m,)(inactive, pg, op);
 }
@@ -642,7 +688,8 @@
 svfloat16_t test_svcvt_f16_u64_x(svbool_t pg, svuint64_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_u64_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i64(<vscale x 8 x half> undef, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i64(<vscale x 8 x half> undef, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_u64,_x,)(pg, op);
 }
@@ -650,7 +697,8 @@
 svfloat32_t test_svcvt_f32_u64_x(svbool_t pg, svuint64_t op)
 {
   // CHECK-LABEL: test_svcvt_f32_u64_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.ucvtf.f32i64(<vscale x 4 x float> undef, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.ucvtf.f32i64(<vscale x 4 x float> undef, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f32,_u64,_x,)(pg, op);
 }
@@ -667,7 +715,8 @@
 svfloat32_t test_svcvt_f32_f16_z(svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_f32_f16_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f16(<vscale x 4 x float> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f16(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f32,_f16,_z,)(pg, op);
 }
@@ -675,7 +724,8 @@
 svfloat64_t test_svcvt_f64_f16_z(svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_f64_f16_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f16(<vscale x 2 x double> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f16(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f64,_f16,_z,)(pg, op);
 }
@@ -683,7 +733,8 @@
 svfloat32_t test_svcvt_f32_f16_m(svfloat32_t inactive, svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_f32_f16_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f16(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f16(<vscale x 4 x float> %inactive, <vscale x 4 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f32,_f16,_m,)(inactive, pg, op);
 }
@@ -691,7 +742,8 @@
 svfloat64_t test_svcvt_f64_f16_m(svfloat64_t inactive, svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_f64_f16_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f16(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f16(<vscale x 2 x double> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f64,_f16,_m,)(inactive, pg, op);
 }
@@ -699,7 +751,8 @@
 svfloat32_t test_svcvt_f32_f16_x(svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_f32_f16_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f16(<vscale x 4 x float> undef, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f16(<vscale x 4 x float> undef, <vscale x 4 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f32,_f16,_x,)(pg, op);
 }
@@ -707,7 +760,8 @@
 svfloat64_t test_svcvt_f64_f16_x(svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvt_f64_f16_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f16(<vscale x 2 x double> undef, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f16(<vscale x 2 x double> undef, <vscale x 2 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f64,_f16,_x,)(pg, op);
 }
@@ -715,7 +769,8 @@
 svfloat64_t test_svcvt_f64_f32_z(svbool_t pg, svfloat32_t op)
 {
   // CHECK-LABEL: test_svcvt_f64_f32_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f32(<vscale x 2 x double> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f32(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 4 x float> %op)
   // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f64,_f32,_z,)(pg, op);
 }
@@ -723,7 +778,8 @@
 svfloat64_t test_svcvt_f64_f32_m(svfloat64_t inactive, svbool_t pg, svfloat32_t op)
 {
   // CHECK-LABEL: test_svcvt_f64_f32_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f32(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f32(<vscale x 2 x double> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 4 x float> %op)
   // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f64,_f32,_m,)(inactive, pg, op);
 }
@@ -731,7 +787,8 @@
 svfloat64_t test_svcvt_f64_f32_x(svbool_t pg, svfloat32_t op)
 {
   // CHECK-LABEL: test_svcvt_f64_f32_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f32(<vscale x 2 x double> undef, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f32(<vscale x 2 x double> undef, <vscale x 2 x i1> %[[PG]], <vscale x 4 x float> %op)
   // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f64,_f32,_x,)(pg, op);
 }
@@ -739,7 +796,8 @@
 svfloat16_t test_svcvt_f16_f32_z(svbool_t pg, svfloat32_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_f32_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f32(<vscale x 8 x half> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f32(<vscale x 8 x half> zeroinitializer, <vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_f32,_z,)(pg, op);
 }
@@ -747,7 +805,8 @@
 svfloat16_t test_svcvt_f16_f64_z(svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_f64_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f64(<vscale x 8 x half> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f64(<vscale x 8 x half> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_f64,_z,)(pg, op);
 }
@@ -755,7 +814,8 @@
 svfloat16_t test_svcvt_f16_f32_m(svfloat16_t inactive, svbool_t pg, svfloat32_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_f32_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f32(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f32(<vscale x 8 x half> %inactive, <vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_f32,_m,)(inactive, pg, op);
 }
@@ -763,7 +823,8 @@
 svfloat16_t test_svcvt_f16_f64_m(svfloat16_t inactive, svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_f64_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f64(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f64(<vscale x 8 x half> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_f64,_m,)(inactive, pg, op);
 }
@@ -771,7 +832,8 @@
 svfloat16_t test_svcvt_f16_f32_x(svbool_t pg, svfloat32_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_f32_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f32(<vscale x 8 x half> undef, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f32(<vscale x 8 x half> undef, <vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_f32,_x,)(pg, op);
 }
@@ -779,7 +841,8 @@
 svfloat16_t test_svcvt_f16_f64_x(svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvt_f16_f64_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f64(<vscale x 8 x half> undef, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f64(<vscale x 8 x half> undef, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f16,_f64,_x,)(pg, op);
 }
@@ -787,7 +850,8 @@
 svfloat32_t test_svcvt_f32_f64_z(svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvt_f32_f64_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f64(<vscale x 4 x float> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f64(<vscale x 4 x float> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f32,_f64,_z,)(pg, op);
 }
@@ -795,7 +859,8 @@
 svfloat32_t test_svcvt_f32_f64_m(svfloat32_t inactive, svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvt_f32_f64_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f64(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f64(<vscale x 4 x float> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f32,_f64,_m,)(inactive, pg, op);
 }
@@ -803,7 +868,8 @@
 svfloat32_t test_svcvt_f32_f64_x(svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvt_f32_f64_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f64(<vscale x 4 x float> undef, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f64(<vscale x 4 x float> undef, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svcvt_f32,_f64,_x,)(pg, op);
 }
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtlt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtlt.c
--- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtlt.c
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtlt.c
@@ -15,7 +15,8 @@
 svfloat32_t test_svcvtlt_f32_f16_m(svfloat32_t inactive, svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvtlt_f32_f16_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float> %inactive, <vscale x 4 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   // overload-warning@+2 {{implicit declaration of function 'svcvtlt_f32_m'}}
   // expected-warning@+1 {{implicit declaration of function 'svcvtlt_f32_f16_m'}}
@@ -25,7 +26,8 @@
 svfloat64_t test_svcvtlt_f64_f32_m(svfloat64_t inactive, svbool_t pg, svfloat32_t op)
 {
   // CHECK-LABEL: test_svcvtlt_f64_f32_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 4 x float> %op)
   // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
   // overload-warning@+2 {{implicit declaration of function 'svcvtlt_f64_m'}}
   // expected-warning@+1 {{implicit declaration of function 'svcvtlt_f64_f32_m'}}
@@ -35,7 +37,8 @@
 svfloat32_t test_svcvtlt_f32_f16_x(svbool_t pg, svfloat16_t op)
 {
   // CHECK-LABEL: test_svcvtlt_f32_f16_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float> undef, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float> undef, <vscale x 4 x i1> %[[PG]], <vscale x 8 x half> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   // overload-warning@+2 {{implicit declaration of function 'svcvtlt_f32_x'}}
   // expected-warning@+1 {{implicit declaration of function 'svcvtlt_f32_f16_x'}}
@@ -45,7 +48,8 @@
 svfloat64_t test_svcvtlt_f64_f32_x(svbool_t pg, svfloat32_t op)
 {
   // CHECK-LABEL: test_svcvtlt_f64_f32_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double> undef, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double> undef, <vscale x 2 x i1> %[[PG]], <vscale x 4 x float> %op)
   // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
   // overload-warning@+2 {{implicit declaration of function 'svcvtlt_f64_x'}}
   // expected-warning@+1 {{implicit declaration of function 'svcvtlt_f64_f32_x'}}
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtnt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtnt.c
--- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtnt.c
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtnt.c
@@ -15,7 +15,8 @@
 svfloat16_t test_svcvtnt_f16_f32_m(svfloat16_t inactive, svbool_t pg, svfloat32_t op)
 {
   // CHECK-LABEL: test_svcvtnt_f16_f32_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fcvtnt.f16f32(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fcvtnt.f16f32(<vscale x 8 x half> %inactive, <vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   // overload-warning@+2 {{implicit declaration of function 'svcvtnt_f16_m'}}
   // expected-warning@+1 {{implicit declaration of function 'svcvtnt_f16_f32_m'}}
@@ -25,7 +26,8 @@
 svfloat32_t test_svcvtnt_f32_f64_m(svfloat32_t inactive, svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvtnt_f32_f64_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtnt.f32f64(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtnt.f32f64(<vscale x 4 x float> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   // overload-warning@+2 {{implicit declaration of function 'svcvtnt_f32_m'}}
   // expected-warning@+1 {{implicit declaration of function 'svcvtnt_f32_f64_m'}}
@@ -35,7 +37,8 @@
 svfloat16_t test_svcvtnt_f16_f32_x(svfloat16_t even, svbool_t pg, svfloat32_t op)
 {
   // CHECK-LABEL: test_svcvtnt_f16_f32_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fcvtnt.f16f32(<vscale x 8 x half> %even, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fcvtnt.f16f32(<vscale x 8 x half> %even, <vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op)
   // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
   // overload-warning@+2 {{implicit declaration of function 'svcvtnt_f16_x'}}
   // expected-warning@+1 {{implicit declaration of function 'svcvtnt_f16_f32_x'}}
@@ -45,7 +48,8 @@
 svfloat32_t test_svcvtnt_f32_f64_x(svfloat32_t even, svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvtnt_f32_f64_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtnt.f32f64(<vscale x 4 x float> %even, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtnt.f32f64(<vscale x 4 x float> %even, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   // overload-warning@+2 {{implicit declaration of function 'svcvtnt_f32_x'}}
   // expected-warning@+1 {{implicit declaration of function 'svcvtnt_f32_f64_x'}}
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtx.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtx.c
--- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtx.c
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtx.c
@@ -15,7 +15,8 @@
 svfloat32_t test_svcvtx_f32_f64_z(svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvtx_f32_f64_z
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   // overload-warning@+2 {{implicit declaration of function 'svcvtx_f32_z'}}
   // expected-warning@+1 {{implicit declaration of function 'svcvtx_f32_f64_z'}}
@@ -25,7 +26,8 @@
 svfloat32_t test_svcvtx_f32_f64_m(svfloat32_t inactive, svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvtx_f32_f64_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   // overload-warning@+2 {{implicit declaration of function 'svcvtx_f32_m'}}
   // expected-warning@+1 {{implicit declaration of function 'svcvtx_f32_f64_m'}}
@@ -35,7 +37,8 @@
 svfloat32_t test_svcvtx_f32_f64_x(svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvtx_f32_f64_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float> undef, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float> undef, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   // overload-warning@+2 {{implicit declaration of function 'svcvtx_f32_x'}}
   // expected-warning@+1 {{implicit declaration of function 'svcvtx_f32_f64_x'}}
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtxnt.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtxnt.c
--- a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtxnt.c
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtxnt.c
@@ -15,7 +15,8 @@
 svfloat32_t test_svcvtxnt_f32_f64_m(svfloat32_t inactive, svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvtxnt_f32_f64_m
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtxnt.f32f64(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtxnt.f32f64(<vscale x 4 x float> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   // overload-warning@+2 {{implicit declaration of function 'svcvtxnt_f32_m'}}
   // expected-warning@+1 {{implicit declaration of function 'svcvtxnt_f32_f64_m'}}
@@ -25,7 +26,8 @@
 svfloat32_t test_svcvtxnt_f32_f64_x(svfloat32_t even, svbool_t pg, svfloat64_t op)
 {
   // CHECK-LABEL: test_svcvtxnt_f32_f64_x
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtxnt.f32f64(<vscale x 4 x float> %even, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtxnt.f32f64(<vscale x 4 x float> %even, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
   // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
   // overload-warning@+2 {{implicit declaration of function 'svcvtxnt_f32_x'}}
   // expected-warning@+1 {{implicit declaration of function 'svcvtxnt_f32_f64_x'}}
diff --git a/clang/utils/TableGen/SveEmitter.cpp b/clang/utils/TableGen/SveEmitter.cpp
--- a/clang/utils/TableGen/SveEmitter.cpp
+++ b/clang/utils/TableGen/SveEmitter.cpp
@@ -564,6 +564,16 @@
     ElementBitwidth = Bitwidth = 64;
     NumVectors = 0;
     break;
+  case 't':
+    Signed = true;
+    Float = false;
+    ElementBitwidth = 32;
+    break;
+  case 'z':
+    Signed = false;
+    Float = false;
+    ElementBitwidth = 32;
+    break;
   case 'O':
     Predicate = false;
     Float = true;
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -1193,9 +1193,8 @@
 
   // This class of intrinsics are not intended to be useful within LLVM IR but
   // are instead here to support some of the more regid parts of the ACLE.
-  class Builtin_SVCVT<string name, LLVMType OUT, LLVMType IN>
-  : GCCBuiltin<"__builtin_sve_" # name>,
-    Intrinsic<[OUT], [OUT, llvm_nxv16i1_ty, IN], [IntrNoMem]>;
+  class Builtin_SVCVT<string name, LLVMType OUT, LLVMType PRED, LLVMType IN>
+      : Intrinsic<[OUT], [OUT, PRED, IN], [IntrNoMem]>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -1719,41 +1718,41 @@
 def int_aarch64_sve_fcmpne : AdvSIMD_SVE_Compare_Intrinsic;
 def int_aarch64_sve_fcmpuo : AdvSIMD_SVE_Compare_Intrinsic;
 
-def int_aarch64_sve_fcvtzs_i32f16   : Builtin_SVCVT<"svcvt_s32_f16_m", llvm_nxv4i32_ty, llvm_nxv8f16_ty>;
-def int_aarch64_sve_fcvtzs_i32f64   : Builtin_SVCVT<"svcvt_s32_f64_m", llvm_nxv4i32_ty, llvm_nxv2f64_ty>;
-def int_aarch64_sve_fcvtzs_i64f16   : Builtin_SVCVT<"svcvt_s64_f16_m", llvm_nxv2i64_ty, llvm_nxv8f16_ty>;
-def int_aarch64_sve_fcvtzs_i64f32   : Builtin_SVCVT<"svcvt_s64_f32_m", llvm_nxv2i64_ty, llvm_nxv4f32_ty>;
-
-def int_aarch64_sve_fcvtzu_i32f16   : Builtin_SVCVT<"svcvt_u32_f16_m", llvm_nxv4i32_ty, llvm_nxv8f16_ty>;
-def int_aarch64_sve_fcvtzu_i32f64   : Builtin_SVCVT<"svcvt_u32_f64_m", llvm_nxv4i32_ty, llvm_nxv2f64_ty>;
-def int_aarch64_sve_fcvtzu_i64f16   : Builtin_SVCVT<"svcvt_u64_f16_m", llvm_nxv2i64_ty, llvm_nxv8f16_ty>;
-def int_aarch64_sve_fcvtzu_i64f32   : Builtin_SVCVT<"svcvt_u64_f32_m", llvm_nxv2i64_ty, llvm_nxv4f32_ty>;
-
-def int_aarch64_sve_fcvt_f16f32     : Builtin_SVCVT<"svcvt_f16_f32_m", llvm_nxv8f16_ty, llvm_nxv4f32_ty>;
-def int_aarch64_sve_fcvt_f16f64     : Builtin_SVCVT<"svcvt_f16_f64_m", llvm_nxv8f16_ty, llvm_nxv2f64_ty>;
-def int_aarch64_sve_fcvt_f32f64     : Builtin_SVCVT<"svcvt_f32_f64_m", llvm_nxv4f32_ty, llvm_nxv2f64_ty>;
-
-def int_aarch64_sve_fcvt_f32f16     : Builtin_SVCVT<"svcvt_f32_f16_m", llvm_nxv4f32_ty, llvm_nxv8f16_ty>;
-def int_aarch64_sve_fcvt_f64f16     : Builtin_SVCVT<"svcvt_f64_f16_m", llvm_nxv2f64_ty, llvm_nxv8f16_ty>;
-def int_aarch64_sve_fcvt_f64f32     : Builtin_SVCVT<"svcvt_f64_f32_m", llvm_nxv2f64_ty, llvm_nxv4f32_ty>;
-
-def int_aarch64_sve_fcvtlt_f32f16   : Builtin_SVCVT<"svcvtlt_f32_f16_m", llvm_nxv4f32_ty, llvm_nxv8f16_ty>;
-def int_aarch64_sve_fcvtlt_f64f32   : Builtin_SVCVT<"svcvtlt_f64_f32_m", llvm_nxv2f64_ty, llvm_nxv4f32_ty>;
-def int_aarch64_sve_fcvtnt_f16f32   : Builtin_SVCVT<"svcvtnt_f16_f32_m", llvm_nxv8f16_ty, llvm_nxv4f32_ty>;
-def int_aarch64_sve_fcvtnt_f32f64   : Builtin_SVCVT<"svcvtnt_f32_f64_m", llvm_nxv4f32_ty, llvm_nxv2f64_ty>;
-
-def int_aarch64_sve_fcvtx_f32f64    : Builtin_SVCVT<"svcvtx_f32_f64_m", llvm_nxv4f32_ty, llvm_nxv2f64_ty>;
-def int_aarch64_sve_fcvtxnt_f32f64  : Builtin_SVCVT<"svcvtxnt_f32_f64_m", llvm_nxv4f32_ty, llvm_nxv2f64_ty>;
-
-def int_aarch64_sve_scvtf_f16i32    : Builtin_SVCVT<"svcvt_f16_s32_m", llvm_nxv8f16_ty, llvm_nxv4i32_ty>;
-def int_aarch64_sve_scvtf_f16i64    : Builtin_SVCVT<"svcvt_f16_s64_m", llvm_nxv8f16_ty, llvm_nxv2i64_ty>;
-def int_aarch64_sve_scvtf_f32i64    : Builtin_SVCVT<"svcvt_f32_s64_m", llvm_nxv4f32_ty, llvm_nxv2i64_ty>;
-def int_aarch64_sve_scvtf_f64i32    : Builtin_SVCVT<"svcvt_f64_s32_m", llvm_nxv2f64_ty, llvm_nxv4i32_ty>;
-
-def int_aarch64_sve_ucvtf_f16i32    : Builtin_SVCVT<"svcvt_f16_u32_m", llvm_nxv8f16_ty, llvm_nxv4i32_ty>;
-def int_aarch64_sve_ucvtf_f16i64    : Builtin_SVCVT<"svcvt_f16_u64_m", llvm_nxv8f16_ty, llvm_nxv2i64_ty>;
-def int_aarch64_sve_ucvtf_f32i64    : Builtin_SVCVT<"svcvt_f32_u64_m", llvm_nxv4f32_ty, llvm_nxv2i64_ty>;
-def int_aarch64_sve_ucvtf_f64i32    : Builtin_SVCVT<"svcvt_f64_u32_m", llvm_nxv2f64_ty, llvm_nxv4i32_ty>;
+def int_aarch64_sve_fcvtzs_i32f16   : Builtin_SVCVT<"svcvt_s32_f16_m", llvm_nxv4i32_ty, llvm_nxv4i1_ty, llvm_nxv8f16_ty>;
+def int_aarch64_sve_fcvtzs_i32f64   : Builtin_SVCVT<"svcvt_s32_f64_m", llvm_nxv4i32_ty, llvm_nxv2i1_ty, llvm_nxv2f64_ty>;
+def int_aarch64_sve_fcvtzs_i64f16   : Builtin_SVCVT<"svcvt_s64_f16_m", llvm_nxv2i64_ty, llvm_nxv2i1_ty, llvm_nxv8f16_ty>;
+def int_aarch64_sve_fcvtzs_i64f32   : Builtin_SVCVT<"svcvt_s64_f32_m", llvm_nxv2i64_ty, llvm_nxv2i1_ty, llvm_nxv4f32_ty>;
+
+def int_aarch64_sve_fcvtzu_i32f16   : Builtin_SVCVT<"svcvt_u32_f16_m", llvm_nxv4i32_ty, llvm_nxv4i1_ty, llvm_nxv8f16_ty>;
+def int_aarch64_sve_fcvtzu_i32f64   : Builtin_SVCVT<"svcvt_u32_f64_m", llvm_nxv4i32_ty, llvm_nxv2i1_ty, llvm_nxv2f64_ty>;
+def int_aarch64_sve_fcvtzu_i64f16   : Builtin_SVCVT<"svcvt_u64_f16_m", llvm_nxv2i64_ty, llvm_nxv2i1_ty, llvm_nxv8f16_ty>;
+def int_aarch64_sve_fcvtzu_i64f32   : Builtin_SVCVT<"svcvt_u64_f32_m", llvm_nxv2i64_ty, llvm_nxv2i1_ty, llvm_nxv4f32_ty>;
+
+def int_aarch64_sve_fcvt_f16f32     : Builtin_SVCVT<"svcvt_f16_f32_m", llvm_nxv8f16_ty, llvm_nxv4i1_ty, llvm_nxv4f32_ty>;
+def int_aarch64_sve_fcvt_f16f64     : Builtin_SVCVT<"svcvt_f16_f64_m", llvm_nxv8f16_ty, llvm_nxv2i1_ty, llvm_nxv2f64_ty>;
+def int_aarch64_sve_fcvt_f32f64     : Builtin_SVCVT<"svcvt_f32_f64_m", llvm_nxv4f32_ty, llvm_nxv2i1_ty, llvm_nxv2f64_ty>;
+
+def int_aarch64_sve_fcvt_f32f16     : Builtin_SVCVT<"svcvt_f32_f16_m", llvm_nxv4f32_ty, llvm_nxv4i1_ty, llvm_nxv8f16_ty>;
+def int_aarch64_sve_fcvt_f64f16     : Builtin_SVCVT<"svcvt_f64_f16_m", llvm_nxv2f64_ty, llvm_nxv2i1_ty, llvm_nxv8f16_ty>;
+def int_aarch64_sve_fcvt_f64f32     : Builtin_SVCVT<"svcvt_f64_f32_m", llvm_nxv2f64_ty, llvm_nxv2i1_ty, llvm_nxv4f32_ty>;
+
+def int_aarch64_sve_fcvtlt_f32f16   : Builtin_SVCVT<"svcvtlt_f32_f16_m", llvm_nxv4f32_ty, llvm_nxv4i1_ty, llvm_nxv8f16_ty>;
+def int_aarch64_sve_fcvtlt_f64f32   : Builtin_SVCVT<"svcvtlt_f64_f32_m", llvm_nxv2f64_ty, llvm_nxv2i1_ty, llvm_nxv4f32_ty>;
+def int_aarch64_sve_fcvtnt_f16f32   : Builtin_SVCVT<"svcvtnt_f16_f32_m", llvm_nxv8f16_ty, llvm_nxv4i1_ty, llvm_nxv4f32_ty>;
+def int_aarch64_sve_fcvtnt_f32f64   : Builtin_SVCVT<"svcvtnt_f32_f64_m", llvm_nxv4f32_ty, llvm_nxv2i1_ty, llvm_nxv2f64_ty>;
+
+def int_aarch64_sve_fcvtx_f32f64    : Builtin_SVCVT<"svcvtx_f32_f64_m", llvm_nxv4f32_ty, llvm_nxv2i1_ty, llvm_nxv2f64_ty>;
+def int_aarch64_sve_fcvtxnt_f32f64  : Builtin_SVCVT<"svcvtxnt_f32_f64_m", llvm_nxv4f32_ty, llvm_nxv2i1_ty, llvm_nxv2f64_ty>;
+
+def int_aarch64_sve_scvtf_f16i32    : Builtin_SVCVT<"svcvt_f16_s32_m", llvm_nxv8f16_ty, llvm_nxv4i1_ty, llvm_nxv4i32_ty>;
+def int_aarch64_sve_scvtf_f16i64    : Builtin_SVCVT<"svcvt_f16_s64_m", llvm_nxv8f16_ty, llvm_nxv2i1_ty, llvm_nxv2i64_ty>;
+def int_aarch64_sve_scvtf_f32i64    : Builtin_SVCVT<"svcvt_f32_s64_m", llvm_nxv4f32_ty, llvm_nxv2i1_ty, llvm_nxv2i64_ty>;
+def int_aarch64_sve_scvtf_f64i32    : Builtin_SVCVT<"svcvt_f64_s32_m", llvm_nxv2f64_ty, llvm_nxv2i1_ty, llvm_nxv4i32_ty>;
+
+def int_aarch64_sve_ucvtf_f16i32    : Builtin_SVCVT<"svcvt_f16_u32_m", llvm_nxv8f16_ty, llvm_nxv4i1_ty, llvm_nxv4i32_ty>;
+def int_aarch64_sve_ucvtf_f16i64    : Builtin_SVCVT<"svcvt_f16_u64_m", llvm_nxv8f16_ty, llvm_nxv2i1_ty, llvm_nxv2i64_ty>;
+def int_aarch64_sve_ucvtf_f32i64    : Builtin_SVCVT<"svcvt_f32_u64_m", llvm_nxv4f32_ty, llvm_nxv2i1_ty, llvm_nxv2i64_ty>;
+def int_aarch64_sve_ucvtf_f64i32    : Builtin_SVCVT<"svcvt_f64_u32_m", llvm_nxv2f64_ty, llvm_nxv2i1_ty, llvm_nxv4i32_ty>;
 
 //
 // Predicate creation
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1176,40 +1176,40 @@
   defm LSR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b001, "lsr", int_aarch64_sve_lsr_wide>;
   defm LSL_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b011, "lsl", int_aarch64_sve_lsl_wide>;
 
-  defm FCVT_ZPmZ_StoH   : sve_fp_2op_p_zd<0b1001000, "fcvt",   ZPR32, ZPR16, int_aarch64_sve_fcvt_f16f32,    nxv8f16, nxv16i1, nxv4f32, ElementSizeS>;
-  defm FCVT_ZPmZ_HtoS   : sve_fp_2op_p_zd<0b1001001, "fcvt",   ZPR16, ZPR32, int_aarch64_sve_fcvt_f32f16,    nxv4f32, nxv16i1, nxv8f16, ElementSizeS>;
-  defm SCVTF_ZPmZ_HtoH  : sve_fp_2op_p_zd<0b0110010, "scvtf",  ZPR16, ZPR16, int_aarch64_sve_scvtf,          nxv8f16, nxv8i1,  nxv8i16, ElementSizeH>;
-  defm SCVTF_ZPmZ_StoS  : sve_fp_2op_p_zd<0b1010100, "scvtf",  ZPR32, ZPR32, int_aarch64_sve_scvtf,          nxv4f32, nxv4i1,  nxv4i32, ElementSizeS>;
-  defm UCVTF_ZPmZ_StoS  : sve_fp_2op_p_zd<0b1010101, "ucvtf",  ZPR32, ZPR32, int_aarch64_sve_ucvtf,          nxv4f32, nxv4i1,  nxv4i32, ElementSizeS>;
-  defm UCVTF_ZPmZ_HtoH  : sve_fp_2op_p_zd<0b0110011, "ucvtf",  ZPR16, ZPR16, int_aarch64_sve_ucvtf,          nxv8f16, nxv8i1,  nxv8i16, ElementSizeH>;
-  defm FCVTZS_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0111010, "fcvtzs", ZPR16, ZPR16, int_aarch64_sve_fcvtzs,         nxv8i16, nxv8i1,  nxv8f16, ElementSizeH>;
-  defm FCVTZS_ZPmZ_StoS : sve_fp_2op_p_zd<0b1011100, "fcvtzs", ZPR32, ZPR32, int_aarch64_sve_fcvtzs,         nxv4i32, nxv4i1,  nxv4f32, ElementSizeS>;
-  defm FCVTZU_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0111011, "fcvtzu", ZPR16, ZPR16, int_aarch64_sve_fcvtzu,         nxv8i16, nxv8i1,  nxv8f16, ElementSizeH>;
-  defm FCVTZU_ZPmZ_StoS : sve_fp_2op_p_zd<0b1011101, "fcvtzu", ZPR32, ZPR32, int_aarch64_sve_fcvtzu,         nxv4i32, nxv4i1,  nxv4f32, ElementSizeS>;
-  defm FCVT_ZPmZ_DtoH   : sve_fp_2op_p_zd<0b1101000, "fcvt",   ZPR64, ZPR16, int_aarch64_sve_fcvt_f16f64,    nxv8f16, nxv16i1, nxv2f64, ElementSizeD>;
-  defm FCVT_ZPmZ_HtoD   : sve_fp_2op_p_zd<0b1101001, "fcvt",   ZPR16, ZPR64, int_aarch64_sve_fcvt_f64f16,    nxv2f64, nxv16i1, nxv8f16, ElementSizeD>;
-  defm FCVT_ZPmZ_DtoS   : sve_fp_2op_p_zd<0b1101010, "fcvt",   ZPR64, ZPR32, int_aarch64_sve_fcvt_f32f64,    nxv4f32, nxv16i1, nxv2f64, ElementSizeD>;
-  defm FCVT_ZPmZ_StoD   : sve_fp_2op_p_zd<0b1101011, "fcvt",   ZPR32, ZPR64, int_aarch64_sve_fcvt_f64f32,    nxv2f64, nxv16i1, nxv4f32, ElementSizeD>;
-  defm SCVTF_ZPmZ_StoD  : sve_fp_2op_p_zd<0b1110000, "scvtf",  ZPR32, ZPR64, int_aarch64_sve_scvtf_f64i32,   nxv2f64, nxv16i1, nxv4i32, ElementSizeD>;
-  defm UCVTF_ZPmZ_StoD  : sve_fp_2op_p_zd<0b1110001, "ucvtf",  ZPR32, ZPR64, int_aarch64_sve_ucvtf_f64i32,   nxv2f64, nxv16i1, nxv4i32, ElementSizeD>;
-  defm UCVTF_ZPmZ_StoH  : sve_fp_2op_p_zd<0b0110101, "ucvtf",  ZPR32, ZPR16, int_aarch64_sve_ucvtf_f16i32,   nxv8f16, nxv16i1, nxv4i32, ElementSizeS>;
-  defm SCVTF_ZPmZ_DtoS  : sve_fp_2op_p_zd<0b1110100, "scvtf",  ZPR64, ZPR32, int_aarch64_sve_scvtf_f32i64,   nxv4f32, nxv16i1, nxv2i64, ElementSizeD>;
-  defm SCVTF_ZPmZ_StoH  : sve_fp_2op_p_zd<0b0110100, "scvtf",  ZPR32, ZPR16, int_aarch64_sve_scvtf_f16i32,   nxv8f16, nxv16i1, nxv4i32, ElementSizeS>;
-  defm SCVTF_ZPmZ_DtoH  : sve_fp_2op_p_zd<0b0110110, "scvtf",  ZPR64, ZPR16, int_aarch64_sve_scvtf_f16i64,   nxv8f16, nxv16i1, nxv2i64, ElementSizeD>;
-  defm UCVTF_ZPmZ_DtoS  : sve_fp_2op_p_zd<0b1110101, "ucvtf",  ZPR64, ZPR32, int_aarch64_sve_ucvtf_f32i64,   nxv4f32, nxv16i1, nxv2i64, ElementSizeD>;
-  defm UCVTF_ZPmZ_DtoH  : sve_fp_2op_p_zd<0b0110111, "ucvtf",  ZPR64, ZPR16, int_aarch64_sve_ucvtf_f16i64,   nxv8f16, nxv16i1, nxv2i64, ElementSizeD>;
-  defm SCVTF_ZPmZ_DtoD  : sve_fp_2op_p_zd<0b1110110, "scvtf",  ZPR64, ZPR64, int_aarch64_sve_scvtf,          nxv2f64, nxv2i1,  nxv2i64, ElementSizeD>;
-  defm UCVTF_ZPmZ_DtoD  : sve_fp_2op_p_zd<0b1110111, "ucvtf",  ZPR64, ZPR64, int_aarch64_sve_ucvtf,          nxv2f64, nxv2i1,  nxv2i64, ElementSizeD>;
-  defm FCVTZS_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1111000, "fcvtzs", ZPR64, ZPR32, int_aarch64_sve_fcvtzs_i32f64,  nxv4i32, nxv16i1, nxv2f64, ElementSizeD>;
-  defm FCVTZU_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1111001, "fcvtzu", ZPR64, ZPR32, int_aarch64_sve_fcvtzu_i32f64,  nxv4i32, nxv16i1, nxv2f64, ElementSizeD>;
-  defm FCVTZS_ZPmZ_StoD : sve_fp_2op_p_zd<0b1111100, "fcvtzs", ZPR32, ZPR64, int_aarch64_sve_fcvtzs_i64f32,  nxv2i64, nxv16i1, nxv4f32, ElementSizeD>;
-  defm FCVTZS_ZPmZ_HtoS : sve_fp_2op_p_zd<0b0111100, "fcvtzs", ZPR16, ZPR32, int_aarch64_sve_fcvtzs_i32f16,  nxv4i32, nxv16i1, nxv8f16, ElementSizeS>;
-  defm FCVTZS_ZPmZ_HtoD : sve_fp_2op_p_zd<0b0111110, "fcvtzs", ZPR16, ZPR64, int_aarch64_sve_fcvtzs_i64f16,  nxv2i64, nxv16i1, nxv8f16, ElementSizeD>;
-  defm FCVTZU_ZPmZ_HtoS : sve_fp_2op_p_zd<0b0111101, "fcvtzu", ZPR16, ZPR32, int_aarch64_sve_fcvtzu_i32f16,  nxv4i32, nxv16i1, nxv8f16, ElementSizeS>;
-  defm FCVTZU_ZPmZ_HtoD : sve_fp_2op_p_zd<0b0111111, "fcvtzu", ZPR16, ZPR64, int_aarch64_sve_fcvtzu_i64f16,  nxv2i64, nxv16i1, nxv8f16, ElementSizeD>;
-  defm FCVTZU_ZPmZ_StoD : sve_fp_2op_p_zd<0b1111101, "fcvtzu", ZPR32, ZPR64, int_aarch64_sve_fcvtzu_i64f32,  nxv2i64, nxv16i1, nxv4f32, ElementSizeD>;
-  defm FCVTZS_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1111110, "fcvtzs", ZPR64, ZPR64, int_aarch64_sve_fcvtzs,         nxv2i64, nxv2i1,  nxv2f64, ElementSizeD>;
-  defm FCVTZU_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1111111, "fcvtzu", ZPR64, ZPR64, int_aarch64_sve_fcvtzu,         nxv2i64, nxv2i1,  nxv2f64, ElementSizeD>;
+  defm FCVT_ZPmZ_StoH   : sve_fp_2op_p_zd<0b1001000, "fcvt",   ZPR32, ZPR16, int_aarch64_sve_fcvt_f16f32,    nxv8f16, nxv4i1, nxv4f32, ElementSizeS>;
+  defm FCVT_ZPmZ_HtoS   : sve_fp_2op_p_zd<0b1001001, "fcvt",   ZPR16, ZPR32, int_aarch64_sve_fcvt_f32f16,    nxv4f32, nxv4i1, nxv8f16, ElementSizeS>;
+  defm SCVTF_ZPmZ_HtoH  : sve_fp_2op_p_zd<0b0110010, "scvtf",  ZPR16, ZPR16, int_aarch64_sve_scvtf,          nxv8f16, nxv8i1, nxv8i16, ElementSizeH>;
+  defm SCVTF_ZPmZ_StoS  : sve_fp_2op_p_zd<0b1010100, "scvtf",  ZPR32, ZPR32, int_aarch64_sve_scvtf,          nxv4f32, nxv4i1, nxv4i32, ElementSizeS>;
+  defm UCVTF_ZPmZ_StoS  : sve_fp_2op_p_zd<0b1010101, "ucvtf",  ZPR32, ZPR32, int_aarch64_sve_ucvtf,          nxv4f32, nxv4i1, nxv4i32, ElementSizeS>;
+  defm UCVTF_ZPmZ_HtoH  : sve_fp_2op_p_zd<0b0110011, "ucvtf",  ZPR16, ZPR16, int_aarch64_sve_ucvtf,          nxv8f16, nxv8i1, nxv8i16, ElementSizeH>;
+  defm FCVTZS_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0111010, "fcvtzs", ZPR16, ZPR16, int_aarch64_sve_fcvtzs,         nxv8i16, nxv8i1, nxv8f16, ElementSizeH>;
+  defm FCVTZS_ZPmZ_StoS : sve_fp_2op_p_zd<0b1011100, "fcvtzs", ZPR32, ZPR32, int_aarch64_sve_fcvtzs,         nxv4i32, nxv4i1, nxv4f32, ElementSizeS>;
+  defm FCVTZU_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0111011, "fcvtzu", ZPR16, ZPR16, int_aarch64_sve_fcvtzu,         nxv8i16, nxv8i1, nxv8f16, ElementSizeH>;
+  defm FCVTZU_ZPmZ_StoS : sve_fp_2op_p_zd<0b1011101, "fcvtzu", ZPR32, ZPR32, int_aarch64_sve_fcvtzu,         nxv4i32, nxv4i1, nxv4f32, ElementSizeS>;
+  defm FCVT_ZPmZ_DtoH   : sve_fp_2op_p_zd<0b1101000, "fcvt",   ZPR64, ZPR16, int_aarch64_sve_fcvt_f16f64,    nxv8f16, nxv2i1, nxv2f64, ElementSizeD>;
+  defm FCVT_ZPmZ_HtoD   : sve_fp_2op_p_zd<0b1101001, "fcvt",   ZPR16, ZPR64, int_aarch64_sve_fcvt_f64f16,    nxv2f64, nxv2i1, nxv8f16, ElementSizeD>;
+  defm FCVT_ZPmZ_DtoS   : sve_fp_2op_p_zd<0b1101010, "fcvt",   ZPR64, ZPR32, int_aarch64_sve_fcvt_f32f64,    nxv4f32, nxv2i1, nxv2f64, ElementSizeD>;
+  defm FCVT_ZPmZ_StoD   : sve_fp_2op_p_zd<0b1101011, "fcvt",   ZPR32, ZPR64, int_aarch64_sve_fcvt_f64f32,    nxv2f64, nxv2i1, nxv4f32, ElementSizeD>;
+  defm SCVTF_ZPmZ_StoD  : sve_fp_2op_p_zd<0b1110000, "scvtf",  ZPR32, ZPR64, int_aarch64_sve_scvtf_f64i32,   nxv2f64, nxv2i1, nxv4i32, ElementSizeD>;
+  defm UCVTF_ZPmZ_StoD  : sve_fp_2op_p_zd<0b1110001, "ucvtf",  ZPR32, ZPR64, int_aarch64_sve_ucvtf_f64i32,   nxv2f64, nxv2i1, nxv4i32, ElementSizeD>;
+  defm UCVTF_ZPmZ_StoH  : sve_fp_2op_p_zd<0b0110101, "ucvtf",  ZPR32, ZPR16, int_aarch64_sve_ucvtf_f16i32,   nxv8f16, nxv4i1, nxv4i32, ElementSizeS>;
+  defm SCVTF_ZPmZ_DtoS  : sve_fp_2op_p_zd<0b1110100, "scvtf",  ZPR64, ZPR32, int_aarch64_sve_scvtf_f32i64,   nxv4f32, nxv2i1, nxv2i64, ElementSizeD>;
+  defm SCVTF_ZPmZ_StoH  : sve_fp_2op_p_zd<0b0110100, "scvtf",  ZPR32, ZPR16, int_aarch64_sve_scvtf_f16i32,   nxv8f16, nxv4i1, nxv4i32, ElementSizeS>;
+  defm SCVTF_ZPmZ_DtoH  : sve_fp_2op_p_zd<0b0110110, "scvtf",  ZPR64, ZPR16, int_aarch64_sve_scvtf_f16i64,   nxv8f16, nxv2i1, nxv2i64, ElementSizeD>;
+  defm UCVTF_ZPmZ_DtoS  : sve_fp_2op_p_zd<0b1110101, "ucvtf",  ZPR64, ZPR32, int_aarch64_sve_ucvtf_f32i64,   nxv4f32, nxv2i1, nxv2i64, ElementSizeD>;
+  defm UCVTF_ZPmZ_DtoH  : sve_fp_2op_p_zd<0b0110111, "ucvtf",  ZPR64, ZPR16, int_aarch64_sve_ucvtf_f16i64,   nxv8f16, nxv2i1, nxv2i64, ElementSizeD>;
+  defm SCVTF_ZPmZ_DtoD  : sve_fp_2op_p_zd<0b1110110, "scvtf",  ZPR64, ZPR64, int_aarch64_sve_scvtf,          nxv2f64, nxv2i1, nxv2i64, ElementSizeD>;
+  defm UCVTF_ZPmZ_DtoD  : sve_fp_2op_p_zd<0b1110111, "ucvtf",  ZPR64, ZPR64, int_aarch64_sve_ucvtf,          nxv2f64, nxv2i1, nxv2i64, ElementSizeD>;
+  defm FCVTZS_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1111000, "fcvtzs", ZPR64, ZPR32, int_aarch64_sve_fcvtzs_i32f64,  nxv4i32, nxv2i1, nxv2f64, ElementSizeD>;
+  defm FCVTZU_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1111001, "fcvtzu", ZPR64, ZPR32, int_aarch64_sve_fcvtzu_i32f64,  nxv4i32, nxv2i1, nxv2f64, ElementSizeD>;
+  defm FCVTZS_ZPmZ_StoD : sve_fp_2op_p_zd<0b1111100, "fcvtzs", ZPR32, ZPR64, int_aarch64_sve_fcvtzs_i64f32,  nxv2i64, nxv2i1, nxv4f32, ElementSizeD>;
+  defm FCVTZS_ZPmZ_HtoS : sve_fp_2op_p_zd<0b0111100, "fcvtzs", ZPR16, ZPR32, int_aarch64_sve_fcvtzs_i32f16,  nxv4i32, nxv4i1, nxv8f16, ElementSizeS>;
+  defm FCVTZS_ZPmZ_HtoD : sve_fp_2op_p_zd<0b0111110, "fcvtzs", ZPR16, ZPR64, int_aarch64_sve_fcvtzs_i64f16,  nxv2i64, nxv2i1, nxv8f16, ElementSizeD>;
+  defm FCVTZU_ZPmZ_HtoS : sve_fp_2op_p_zd<0b0111101, "fcvtzu", ZPR16, ZPR32, int_aarch64_sve_fcvtzu_i32f16,  nxv4i32, nxv4i1, nxv8f16, ElementSizeS>;
+  defm FCVTZU_ZPmZ_HtoD : sve_fp_2op_p_zd<0b0111111, "fcvtzu", ZPR16, ZPR64, int_aarch64_sve_fcvtzu_i64f16,  nxv2i64, nxv2i1, nxv8f16, ElementSizeD>;
+  defm FCVTZU_ZPmZ_StoD : sve_fp_2op_p_zd<0b1111101, "fcvtzu", ZPR32, ZPR64, int_aarch64_sve_fcvtzu_i64f32,  nxv2i64, nxv2i1, nxv4f32, ElementSizeD>;
+  defm FCVTZS_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1111110, "fcvtzs", ZPR64, ZPR64, int_aarch64_sve_fcvtzs,         nxv2i64, nxv2i1, nxv2f64, ElementSizeD>;
+  defm FCVTZU_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1111111, "fcvtzu", ZPR64, ZPR64, int_aarch64_sve_fcvtzu,         nxv2i64, nxv2i1, nxv2f64, ElementSizeD>;
 
   defm FRINTN_ZPmZ : sve_fp_2op_p_zd_HSD<0b00000, "frintn", int_aarch64_sve_frintn>;
   defm FRINTP_ZPmZ : sve_fp_2op_p_zd_HSD<0b00001, "frintp", int_aarch64_sve_frintp>;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -2012,22 +2012,22 @@
   def _StoH : sve2_fp_convert_precision<0b1000, asm, ZPR16, ZPR32>;
   def _DtoS : sve2_fp_convert_precision<0b1110, asm, ZPR32, ZPR64>;
 
-  def : SVE_3_Op_Pat<nxv8f16, !cast<SDPatternOperator>(op # _f16f32), nxv8f16, nxv16i1, nxv4f32, !cast<Instruction>(NAME # _StoH)>;
-  def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f64), nxv4f32, nxv16i1, nxv2f64, !cast<Instruction>(NAME # _DtoS)>;
+  def : SVE_3_Op_Pat<nxv8f16, !cast<SDPatternOperator>(op # _f16f32), nxv8f16, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _StoH)>;
+  def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f64), nxv4f32, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _DtoS)>;
 }
 
 multiclass sve2_fp_convert_up_long<string asm, string op> {
   def _HtoS : sve2_fp_convert_precision<0b1001, asm, ZPR32, ZPR16>;
   def _StoD : sve2_fp_convert_precision<0b1111, asm, ZPR64, ZPR32>;
 
-  def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f16), nxv4f32, nxv16i1, nxv8f16, !cast<Instruction>(NAME # _HtoS)>;
-  def : SVE_3_Op_Pat<nxv2f64, !cast<SDPatternOperator>(op # _f64f32), nxv2f64, nxv16i1, nxv4f32, !cast<Instruction>(NAME # _StoD)>;
+  def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f16), nxv4f32, nxv4i1, nxv8f16, !cast<Instruction>(NAME # _HtoS)>;
+  def : SVE_3_Op_Pat<nxv2f64, !cast<SDPatternOperator>(op # _f64f32), nxv2f64, nxv2i1, nxv4f32, !cast<Instruction>(NAME # _StoD)>;
 }
 
 multiclass sve2_fp_convert_down_odd_rounding_top<string asm, string op> {
   def _DtoS : sve2_fp_convert_precision<0b0010, asm, ZPR32, ZPR64>;
 
-  def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f64), nxv4f32, nxv16i1, nxv2f64, !cast<Instruction>(NAME # _DtoS)>;
+  def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f64), nxv4f32, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _DtoS)>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -2271,7 +2271,7 @@
 
 multiclass sve2_fp_convert_down_odd_rounding<string asm, string op> {
   def _DtoS : sve_fp_2op_p_zd<0b0001010, asm, ZPR64, ZPR32, ElementSizeD>;
-  def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f64), nxv4f32, nxv16i1, nxv2f64, !cast<Instruction>(NAME # _DtoS)>;
+  def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f64), nxv4f32, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _DtoS)>;
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-fp-converts.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-fp-converts.ll
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-fp-converts.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-fp-converts.ll
@@ -4,62 +4,62 @@
 ; FCVT
 ;
 
-define <vscale x 8 x half> @fcvt_f16_f32(<vscale x 8 x half> %a, <vscale x 16 x i1> %pg, <vscale x 4 x float> %b) {
+define <vscale x 8 x half> @fcvt_f16_f32(<vscale x 8 x half> %a, <vscale x 4 x i1> %pg, <vscale x 4 x float> %b) {
 ; CHECK-LABEL: fcvt_f16_f32:
 ; CHECK: fcvt z0.h, p0/m, z1.s
 ; CHECK-NEXT: ret
   %out = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f32(<vscale x 8 x half> %a,
-                                                                <vscale x 16 x i1> %pg,
+                                                                <vscale x 4 x i1> %pg,
                                                                 <vscale x 4 x float> %b)
   ret <vscale x 8 x half> %out
 }
 
-define <vscale x 8 x half> @fcvt_f16_f64(<vscale x 8 x half> %a, <vscale x 16 x i1> %pg, <vscale x 2 x double> %b) {
+define <vscale x 8 x half> @fcvt_f16_f64(<vscale x 8 x half> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b) {
 ; CHECK-LABEL: fcvt_f16_f64:
 ; CHECK: fcvt z0.h, p0/m, z1.d
 ; CHECK-NEXT: ret
   %out = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f64(<vscale x 8 x half> %a,
-                                                                <vscale x 16 x i1> %pg,
+                                                                <vscale x 2 x i1> %pg,
                                                                 <vscale x 2 x double> %b)
   ret <vscale x 8 x half> %out
 }
 
-define <vscale x 4 x float> @fcvt_f32_f16(<vscale x 4 x float> %a, <vscale x 16 x i1> %pg, <vscale x 8 x half> %b) {
+define <vscale x 4 x float> @fcvt_f32_f16(<vscale x 4 x float> %a, <vscale x 4 x i1> %pg, <vscale x 8 x half> %b) {
 ; CHECK-LABEL: fcvt_f32_f16:
 ; CHECK: fcvt z0.s, p0/m, z1.h
 ; CHECK-NEXT: ret
   %out = call <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f16(<vscale x 4 x float> %a,
-                                                                 <vscale x 16 x i1> %pg,
+                                                                 <vscale x 4 x i1> %pg,
                                                                  <vscale x 8 x half> %b)
   ret <vscale x 4 x float> %out
 }
 
-define <vscale x 4 x float> @fcvt_f32_f64(<vscale x 4 x float> %a, <vscale x 16 x i1> %pg, <vscale x 2 x double> %b) {
+define <vscale x 4 x float> @fcvt_f32_f64(<vscale x 4 x float> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b) {
 ; CHECK-LABEL: fcvt_f32_f64:
 ; CHECK: fcvt z0.s, p0/m, z1.d
 ; CHECK-NEXT: ret
   %out = call <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f64(<vscale x 4 x float> %a,
-                                                                 <vscale x 16 x i1> %pg,
+                                                                 <vscale x 2 x i1> %pg,
                                                                  <vscale x 2 x double> %b)
   ret <vscale x 4 x float> %out
 }
 
-define <vscale x 2 x double> @fcvt_f64_f16(<vscale x 2 x double> %a, <vscale x 16 x i1> %pg, <vscale x 8 x half> %b) {
+define <vscale x 2 x double> @fcvt_f64_f16(<vscale x 2 x double> %a, <vscale x 2 x i1> %pg, <vscale x 8 x half> %b) {
 ; CHECK-LABEL: fcvt_f64_f16:
 ; CHECK: fcvt z0.d, p0/m, z1.h
 ; CHECK-NEXT: ret
   %out = call <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f16(<vscale x 2 x double> %a,
-                                                                  <vscale x 16 x i1> %pg,
+                                                                  <vscale x 2 x i1> %pg,
                                                                   <vscale x 8 x half> %b)
   ret <vscale x 2 x double> %out
 }
 
-define <vscale x 2 x double> @fcvt_f64_f32(<vscale x 2 x double> %a, <vscale x 16 x i1> %pg, <vscale x 4 x float> %b) {
+define <vscale x 2 x double> @fcvt_f64_f32(<vscale x 2 x double> %a, <vscale x 2 x i1> %pg, <vscale x 4 x float> %b) {
 ; CHECK-LABEL: fcvt_f64_f32:
 ; CHECK: fcvt z0.d, p0/m, z1.s
 ; CHECK-NEXT: ret
   %out = call <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f32(<vscale x 2 x double> %a,
-                                                                  <vscale x 16 x i1> %pg,
+                                                                  <vscale x 2 x i1> %pg,
                                                                   <vscale x 4 x float> %b)
   ret <vscale x 2 x double> %out
 }
@@ -98,42 +98,42 @@
   ret <vscale x 2 x i64> %out
 }
 
-define <vscale x 4 x i32> @fcvtzs_i32_f16(<vscale x 4 x i32> %a, <vscale x 16 x i1> %pg, <vscale x 8 x half> %b) {
+define <vscale x 4 x i32> @fcvtzs_i32_f16(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 8 x half> %b) {
 ; CHECK-LABEL: fcvtzs_i32_f16:
 ; CHECK: fcvtzs z0.s, p0/m, z1.h
 ; CHECK-NEXT: ret
   %out = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> %a,
-                                                                 <vscale x 16 x i1> %pg,
+                                                                 <vscale x 4 x i1> %pg,
                                                                  <vscale x 8 x half> %b)
   ret <vscale x 4 x i32> %out
 }
 
-define <vscale x 4 x i32> @fcvtzs_i32_f64(<vscale x 4 x i32> %a, <vscale x 16 x i1> %pg, <vscale x 2 x double> %b) {
+define <vscale x 4 x i32> @fcvtzs_i32_f64(<vscale x 4 x i32> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b) {
 ; CHECK-LABEL: fcvtzs_i32_f64:
 ; CHECK: fcvtzs z0.s, p0/m, z1.d
 ; CHECK-NEXT: ret
   %out = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> %a,
-                                                                 <vscale x 16 x i1> %pg,
+                                                                 <vscale x 2 x i1> %pg,
                                                                  <vscale x 2 x double> %b)
   ret <vscale x 4 x i32> %out
 }
 
-define <vscale x 2 x i64> @fcvtzs_i64_f16(<vscale x 2 x i64> %a, <vscale x 16 x i1> %pg, <vscale x 8 x half> %b) {
+define <vscale x 2 x i64> @fcvtzs_i64_f16(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 8 x half> %b) {
 ; CHECK-LABEL: fcvtzs_i64_f16:
 ; CHECK: fcvtzs z0.d, p0/m, z1.h
 ; CHECK-NEXT: ret
   %out = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f16(<vscale x 2 x i64> %a,
-                                                                 <vscale x 16 x i1> %pg,
+                                                                 <vscale x 2 x i1> %pg,
                                                                  <vscale x 8 x half> %b)
   ret <vscale x 2 x i64> %out
 }
 
-define <vscale x 2 x i64> @fcvtzs_i64_f32(<vscale x 2 x i64> %a, <vscale x 16 x i1> %pg, <vscale x 4 x float> %b) {
+define <vscale x 2 x i64> @fcvtzs_i64_f32(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 4 x float> %b) {
 ; CHECK-LABEL: fcvtzs_i64_f32:
 ; CHECK: fcvtzs z0.d, p0/m, z1.s
 ; CHECK-NEXT: ret
   %out = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f32(<vscale x 2 x i64> %a,
-                                                                 <vscale x 16 x i1> %pg,
+                                                                 <vscale x 2 x i1> %pg,
                                                                  <vscale x 4 x float> %b)
   ret <vscale x 2 x i64> %out
 }
@@ -172,42 +172,42 @@
   ret <vscale x 2 x i64> %out
 }
 
-define <vscale x 4 x i32> @fcvtzu_i32_f16(<vscale x 4 x i32> %a, <vscale x 16 x i1> %pg, <vscale x 8 x half> %b) {
+define <vscale x 4 x i32> @fcvtzu_i32_f16(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 8 x half> %b) {
 ; CHECK-LABEL: fcvtzu_i32_f16:
 ; CHECK: fcvtzu z0.s, p0/m, z1.h
 ; CHECK-NEXT: ret
   %out = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f16(<vscale x 4 x i32> %a,
-                                                                 <vscale x 16 x i1> %pg,
+                                                                 <vscale x 4 x i1> %pg,
                                                                  <vscale x 8 x half> %b)
   ret <vscale x 4 x i32> %out
 }
 
-define <vscale x 4 x i32> @fcvtzu_i32_f64(<vscale x 4 x i32> %a, <vscale x 16 x i1> %pg, <vscale x 2 x double> %b) {
+define <vscale x 4 x i32> @fcvtzu_i32_f64(<vscale x 4 x i32> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b) {
 ; CHECK-LABEL: fcvtzu_i32_f64:
 ; CHECK: fcvtzu z0.s, p0/m, z1.d
 ; CHECK-NEXT: ret
   %out = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f64(<vscale x 4 x i32> %a,
-                                                                 <vscale x 16 x i1> %pg,
+                                                                 <vscale x 2 x i1> %pg,
                                                                  <vscale x 2 x double> %b)
   ret <vscale x 4 x i32> %out
 }
 
-define <vscale x 2 x i64> @fcvtzu_i64_f16(<vscale x 2 x i64> %a, <vscale x 16 x i1> %pg, <vscale x 8 x half> %b) {
+define <vscale x 2 x i64> @fcvtzu_i64_f16(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 8 x half> %b) {
 ; CHECK-LABEL: fcvtzu_i64_f16:
 ; CHECK: fcvtzu z0.d, p0/m, z1.h
 ; CHECK-NEXT: ret
   %out = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f16(<vscale x 2 x i64> %a,
-                                                                 <vscale x 16 x i1> %pg,
+                                                                 <vscale x 2 x i1> %pg,
                                                                  <vscale x 8 x half> %b)
   ret <vscale x 2 x i64> %out
 }
 
-define <vscale x 2 x i64> @fcvtzu_i64_f32(<vscale x 2 x i64> %a, <vscale x 16 x i1> %pg, <vscale x 4 x float> %b) {
+define <vscale x 2 x i64> @fcvtzu_i64_f32(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 4 x float> %b) {
 ; CHECK-LABEL: fcvtzu_i64_f32:
 ; CHECK: fcvtzu z0.d, p0/m, z1.s
 ; CHECK-NEXT: ret
   %out = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f32(<vscale x 2 x i64> %a,
-                                                                 <vscale x 16 x i1> %pg,
+                                                                 <vscale x 2 x i1> %pg,
                                                                  <vscale x 4 x float> %b)
   ret <vscale x 2 x i64> %out
 }
@@ -246,42 +246,42 @@
   ret <vscale x 2 x double> %out
 }
 
-define <vscale x 8 x half> @scvtf_f16_i32(<vscale x 8 x half> %a, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %b) {
+define <vscale x 8 x half> @scvtf_f16_i32(<vscale x 8 x half> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) {
 ; CHECK-LABEL: scvtf_f16_i32:
 ; CHECK: scvtf z0.h, p0/m, z1.s
 ; CHECK-NEXT: ret
   %out = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i32(<vscale x 8 x half> %a,
-                                                                 <vscale x 16 x i1> %pg,
+                                                                 <vscale x 4 x i1> %pg,
                                                                  <vscale x 4 x i32> %b)
   ret <vscale x 8 x half> %out
 }
 
-define <vscale x 8 x half> @scvtf_f16_i64(<vscale x 8 x half> %a, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %b) {
+define <vscale x 8 x half> @scvtf_f16_i64(<vscale x 8 x half> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) {
 ; CHECK-LABEL: scvtf_f16_i64:
 ; CHECK: scvtf z0.h, p0/m, z1.d
 ; CHECK-NEXT: ret
   %out = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i64(<vscale x 8 x half> %a,
-                                                                 <vscale x 16 x i1> %pg,
+                                                                 <vscale x 2 x i1> %pg,
                                                                  <vscale x 2 x i64> %b)
   ret <vscale x 8 x half> %out
 }
 
-define <vscale x 4 x float> @scvtf_f32_i64(<vscale x 4 x float> %a, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %b) {
+define <vscale x 4 x float> @scvtf_f32_i64(<vscale x 4 x float> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) {
 ; CHECK-LABEL: scvtf_f32_i64:
 ; CHECK: scvtf z0.s, p0/m, z1.d
 ; CHECK-NEXT: ret
   %out = call <vscale x 4 x float> @llvm.aarch64.sve.scvtf.f32i64(<vscale x 4 x float> %a,
-                                                                  <vscale x 16 x i1> %pg,
+                                                                  <vscale x 2 x i1> %pg,
                                                                   <vscale x 2 x i64> %b)
   ret <vscale x 4 x float> %out
 }
 
-define <vscale x 2 x double> @scvtf_f64_i32(<vscale x 2 x double> %a, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %b) {
+define <vscale x 2 x double> @scvtf_f64_i32(<vscale x 2 x double> %a, <vscale x 2 x i1> %pg, <vscale x 4 x i32> %b) {
 ; CHECK-LABEL: scvtf_f64_i32:
 ; CHECK: scvtf z0.d, p0/m, z1.s
 ; CHECK-NEXT: ret
   %out = call <vscale x 2 x double> @llvm.aarch64.sve.scvtf.f64i32(<vscale x 2 x double> %a,
-                                                                   <vscale x 16 x i1> %pg,
+                                                                   <vscale x 2 x i1> %pg,
                                                                    <vscale x 4 x i32> %b)
   ret <vscale x 2 x double> %out
 }
@@ -320,81 +320,81 @@
   ret <vscale x 2 x double> %out
 }
 
-define <vscale x 8 x half> @ucvtf_f16_i32(<vscale x 8 x half> %a, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %b) {
+define <vscale x 8 x half> @ucvtf_f16_i32(<vscale x 8 x half> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) {
 ; CHECK-LABEL: ucvtf_f16_i32:
 ; CHECK: ucvtf z0.h, p0/m, z1.s
 ; CHECK-NEXT: ret
   %out = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i32(<vscale x 8 x half> %a,
-                                                                 <vscale x 16 x i1> %pg,
+                                                                 <vscale x 4 x i1> %pg,
                                                                  <vscale x 4 x i32> %b)
   ret <vscale x 8 x half> %out
 }
 
-define <vscale x 8 x half> @ucvtf_f16_i64(<vscale x 8 x half> %a, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %b) {
+define <vscale x 8 x half> @ucvtf_f16_i64(<vscale x 8 x half> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) {
 ; CHECK-LABEL: ucvtf_f16_i64:
 ; CHECK: ucvtf z0.h, p0/m, z1.d
 ; CHECK-NEXT: ret
   %out = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i64(<vscale x 8 x half> %a,
-                                                                 <vscale x 16 x i1> %pg,
+                                                                 <vscale x 2 x i1> %pg,
                                                                  <vscale x 2 x i64> %b)
   ret <vscale x 8 x half> %out
 }
 
-define <vscale x 4 x float> @ucvtf_f32_i64(<vscale x 4 x float> %a, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %b) {
+define <vscale x 4 x float> @ucvtf_f32_i64(<vscale x 4 x float> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) {
 ; CHECK-LABEL: ucvtf_f32_i64:
 ; CHECK: ucvtf z0.s, p0/m, z1.d
 ; CHECK-NEXT: ret
   %out = call <vscale x 4 x float> @llvm.aarch64.sve.ucvtf.f32i64(<vscale x 4 x float> %a,
-                                                                  <vscale x 16 x i1> %pg,
+                                                                  <vscale x 2 x i1> %pg,
                                                                   <vscale x 2 x i64> %b)
   ret <vscale x 4 x float> %out
 }
 
-define <vscale x 2 x double> @ucvtf_f64_i32(<vscale x 2 x double> %a, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %b) {
+define <vscale x 2 x double> @ucvtf_f64_i32(<vscale x 2 x double> %a, <vscale x 2 x i1> %pg, <vscale x 4 x i32> %b) {
 ; CHECK-LABEL: ucvtf_f64_i32:
 ; CHECK: ucvtf z0.d, p0/m, z1.s
 ; CHECK-NEXT: ret
   %out = call <vscale x 2 x double> @llvm.aarch64.sve.ucvtf.f64i32(<vscale x 2 x double> %a,
-                                                                   <vscale x 16 x i1> %pg,
+                                                                   <vscale x 2 x i1> %pg,
                                                                    <vscale x 4 x i32> %b)
   ret <vscale x 2 x double> %out
 }
 
-declare <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f32(<vscale x 8 x half>, <vscale x 16 x i1>, <vscale x 4 x float>)
-declare <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f64(<vscale x 8 x half>, <vscale x 16 x i1>, <vscale x 2 x double>)
-declare <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f16(<vscale x 4 x float>, <vscale x 16 x i1>, <vscale x 8 x half>)
-declare <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f64(<vscale x 4 x float>, <vscale x 16 x i1>, <vscale x 2 x double>)
-declare <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f16(<vscale x 2 x double>, <vscale x 16 x i1>, <vscale x 8 x half>)
-declare <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f32(<vscale x 2 x double>, <vscale x 16 x i1>, <vscale x 4 x float>)
+declare <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f32(<vscale x 8 x half>, <vscale x 4 x i1>, <vscale x 4 x float>)
+declare <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f64(<vscale x 8 x half>, <vscale x 2 x i1>, <vscale x 2 x double>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f16(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 8 x half>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f64(<vscale x 4 x float>, <vscale x 2 x i1>, <vscale x 2 x double>)
+declare <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f16(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 8 x half>)
+declare <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f32(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 4 x float>)
 
 declare <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>)
 declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x float>)
 declare <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.nxv2i64.nxv2f64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x double>)
-declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32>, <vscale x 16 x i1>, <vscale x 8 x half>)
-declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32>, <vscale x 16 x i1>, <vscale x 2 x double>)
-declare <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f16(<vscale x 2 x i64>, <vscale x 16 x i1>, <vscale x 8 x half>)
-declare <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f32(<vscale x 2 x i64>, <vscale x 16 x i1>, <vscale x 4 x float>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 8 x half>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32>, <vscale x 2 x i1>, <vscale x 2 x double>)
+declare <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f16(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 8 x half>)
+declare <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f32(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 4 x float>)
 
 declare <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>)
 declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.nxv4i32.nxv4f32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x float>)
 declare <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.nxv2i64.nxv2f64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x double>)
-declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f16(<vscale x 4 x i32>, <vscale x 16 x i1>, <vscale x 8 x half>)
-declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f64(<vscale x 4 x i32>, <vscale x 16 x i1>, <vscale x 2 x double>)
-declare <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f16(<vscale x 2 x i64>, <vscale x 16 x i1>, <vscale x 8 x half>)
-declare <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f32(<vscale x 2 x i64>, <vscale x 16 x i1>, <vscale x 4 x float>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f16(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 8 x half>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f64(<vscale x 4 x i32>, <vscale x 2 x i1>, <vscale x 2 x double>)
+declare <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f16(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 8 x half>)
+declare <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f32(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 4 x float>)
 
 declare <vscale x 8 x half> @llvm.aarch64.sve.scvtf.nxv8f16.nxv8i16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x i16>)
 declare <vscale x 4 x float> @llvm.aarch64.sve.scvtf.nxv4f32.nxv4i32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x i32>)
 declare <vscale x 2 x double> @llvm.aarch64.sve.scvtf.nxv2f64.nxv2i64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x i64>)
-declare <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i32(<vscale x 8 x half>, <vscale x 16 x i1>, <vscale x 4 x i32>)
-declare <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i64(<vscale x 8 x half>, <vscale x 16 x i1>, <vscale x 2 x i64>)
-declare <vscale x 4 x float> @llvm.aarch64.sve.scvtf.f32i64(<vscale x 4 x float>, <vscale x 16 x i1>, <vscale x 2 x i64>)
-declare <vscale x 2 x double> @llvm.aarch64.sve.scvtf.f64i32(<vscale x 2 x double>, <vscale x 16 x i1>, <vscale x 4 x i32>)
+declare <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i32(<vscale x 8 x half>, <vscale x 4 x i1>, <vscale x 4 x i32>)
+declare <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i64(<vscale x 8 x half>, <vscale x 2 x i1>, <vscale x 2 x i64>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.scvtf.f32i64(<vscale x 4 x float>, <vscale x 2 x i1>, <vscale x 2 x i64>)
+declare <vscale x 2 x double> @llvm.aarch64.sve.scvtf.f64i32(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 4 x i32>)
 
 declare <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.nxv8f16.nxv8i16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x i16>)
 declare <vscale x 4 x float> @llvm.aarch64.sve.ucvtf.nxv4f32.nxv4i32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x i32>)
 declare <vscale x 2 x double> @llvm.aarch64.sve.ucvtf.nxv2f64.nxv2i64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x i64>)
-declare <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i32(<vscale x 8 x half>, <vscale x 16 x i1>, <vscale x 4 x i32>)
-declare <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i64(<vscale x 8 x half>, <vscale x 16 x i1>, <vscale x 2 x i64>)
-declare <vscale x 4 x float> @llvm.aarch64.sve.ucvtf.f32i64(<vscale x 4 x float>, <vscale x 16 x i1>, <vscale x 2 x i64>)
-declare <vscale x 2 x double> @llvm.aarch64.sve.ucvtf.f64i32(<vscale x 2 x double>, <vscale x 16 x i1>, <vscale x 4 x i32>)
+declare <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i32(<vscale x 8 x half>, <vscale x 4 x i1>, <vscale x 4 x i32>)
+declare <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i64(<vscale x 8 x half>, <vscale x 2 x i1>, <vscale x 2 x i64>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.ucvtf.f32i64(<vscale x 4 x float>, <vscale x 2 x i1>, <vscale x 2 x i64>)
+declare <vscale x 2 x double> @llvm.aarch64.sve.ucvtf.f64i32(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 4 x i32>)
diff --git a/llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-converts.ll b/llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-converts.ll
--- a/llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-converts.ll
+++ b/llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-converts.ll
@@ -4,22 +4,22 @@
 ; FCVTLT
 ;
 
-define <vscale x 4 x float> @fcvtlt_f32_f16(<vscale x 4 x float> %a, <vscale x 16 x i1> %pg, <vscale x 8 x half> %b) {
+define <vscale x 4 x float> @fcvtlt_f32_f16(<vscale x 4 x float> %a, <vscale x 4 x i1> %pg, <vscale x 8 x half> %b) {
 ; CHECK-LABEL: fcvtlt_f32_f16:
 ; CHECK: fcvtlt z0.s, p0/m, z1.h
 ; CHECK-NEXT: ret
   %out = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float> %a,
-                                                                   <vscale x 16 x i1> %pg,
+                                                                   <vscale x 4 x i1> %pg,
                                                                    <vscale x 8 x half> %b)
   ret <vscale x 4 x float> %out
 }
 
-define <vscale x 2 x double> @fcvtlt_f64_f32(<vscale x 2 x double> %a, <vscale x 16 x i1> %pg, <vscale x 4 x float> %b) {
+define <vscale x 2 x double> @fcvtlt_f64_f32(<vscale x 2 x double> %a, <vscale x 2 x i1> %pg, <vscale x 4 x float> %b) {
 ; CHECK-LABEL: fcvtlt_f64_f32:
 ; CHECK: fcvtlt	z0.d, p0/m, z1.s
 ; CHECK-NEXT: ret
   %out = call <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double> %a,
-                                                                    <vscale x 16 x i1> %pg,
+                                                                    <vscale x 2 x i1> %pg,
                                                                     <vscale x 4 x float> %b)
   ret <vscale x 2 x double> %out
 }
@@ -28,22 +28,22 @@
 ; FCVTNT
 ;
 
-define <vscale x 8 x half> @fcvtnt_f16_f32(<vscale x 8 x half> %a, <vscale x 16 x i1> %pg, <vscale x 4 x float> %b) {
+define <vscale x 8 x half> @fcvtnt_f16_f32(<vscale x 8 x half> %a, <vscale x 4 x i1> %pg, <vscale x 4 x float> %b) {
 ; CHECK-LABEL: fcvtnt_f16_f32:
 ; CHECK: fcvtnt z0.h, p0/m, z1.s
 ; CHECK-NEXT: ret
   %out = call <vscale x 8 x half> @llvm.aarch64.sve.fcvtnt.f16f32(<vscale x 8 x half> %a,
-                                                             <vscale x 16 x i1> %pg,
+                                                             <vscale x 4 x i1> %pg,
                                                              <vscale x 4 x float> %b)
   ret <vscale x 8 x half> %out
 }
 
-define <vscale x 4 x float> @fcvtnt_f32_f64(<vscale x 4 x float> %a, <vscale x 16 x i1> %pg, <vscale x 2 x double> %b) {
+define <vscale x 4 x float> @fcvtnt_f32_f64(<vscale x 4 x float> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b) {
 ; CHECK-LABEL: fcvtnt_f32_f64:
 ; CHECK: fcvtnt	z0.s, p0/m, z1.d
 ; CHECK-NEXT: ret
   %out = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtnt.f32f64(<vscale x 4 x float> %a,
-                                                                   <vscale x 16 x i1> %pg,
+                                                                   <vscale x 2 x i1> %pg,
                                                                    <vscale x 2 x double> %b)
   ret <vscale x 4 x float> %out
 }
@@ -52,12 +52,12 @@
 ; FCVTX
 ;
 
-define <vscale x 4 x float> @fcvtx_f32_f64(<vscale x 4 x float> %a, <vscale x 16 x i1> %pg, <vscale x 2 x double> %b) {
+define <vscale x 4 x float> @fcvtx_f32_f64(<vscale x 4 x float> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b) {
 ; CHECK-LABEL: fcvtx_f32_f64:
 ; CHECK: fcvtx z0.s, p0/m, z1.d
 ; CHECK-NEXT: ret
   %out = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float> %a,
-                                                                  <vscale x 16 x i1> %pg,
+                                                                  <vscale x 2 x i1> %pg,
                                                                   <vscale x 2 x double> %b)
   ret <vscale x 4 x float> %out
 }
@@ -66,19 +66,19 @@
 ; FCVTXNT
 ;
 
-define <vscale x 4 x float> @fcvtxnt_f32_f64(<vscale x 4 x float> %a, <vscale x 16 x i1> %pg, <vscale x 2 x double> %b) {
+define <vscale x 4 x float> @fcvtxnt_f32_f64(<vscale x 4 x float> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b) {
 ; CHECK-LABEL: fcvtxnt_f32_f64:
 ; CHECK: fcvtxnt z0.s, p0/m, z1.d
 ; CHECK-NEXT: ret
   %out = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtxnt.f32f64(<vscale x 4 x float> %a,
-                                                                    <vscale x 16 x i1> %pg,
+                                                                    <vscale x 2 x i1> %pg,
                                                                     <vscale x 2 x double> %b)
   ret <vscale x 4 x float> %out
 }
 
-declare <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float>, <vscale x 16 x i1>, <vscale x 8 x half>)
-declare <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double>, <vscale x 16 x i1>, <vscale x 4 x float>)
-declare <vscale x 8 x half> @llvm.aarch64.sve.fcvtnt.f16f32(<vscale x 8 x half>, <vscale x 16 x i1>, <vscale x 4 x float>)
-declare <vscale x 4 x float> @llvm.aarch64.sve.fcvtnt.f32f64(<vscale x 4 x float>, <vscale x 16 x i1>, <vscale x 2 x double>)
-declare <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float>, <vscale x 16 x i1>, <vscale x 2 x double>)
-declare <vscale x 4 x float> @llvm.aarch64.sve.fcvtxnt.f32f64(<vscale x 4 x float>, <vscale x 16 x i1>, <vscale x 2 x double>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 8 x half>)
+declare <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 4 x float>)
+declare <vscale x 8 x half> @llvm.aarch64.sve.fcvtnt.f16f32(<vscale x 8 x half>, <vscale x 4 x i1>, <vscale x 4 x float>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fcvtnt.f32f64(<vscale x 4 x float>, <vscale x 2 x i1>, <vscale x 2 x double>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float>, <vscale x 2 x i1>, <vscale x 2 x double>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fcvtxnt.f32f64(<vscale x 4 x float>, <vscale x 2 x i1>, <vscale x 2 x double>)
diff --git a/llvm/unittests/IR/IRBuilderTest.cpp b/llvm/unittests/IR/IRBuilderTest.cpp
--- a/llvm/unittests/IR/IRBuilderTest.cpp
+++ b/llvm/unittests/IR/IRBuilderTest.cpp
@@ -132,7 +132,7 @@
   // with scalable vectors, e.g. LLVMType<nxv4i32>.
   Type *SrcVecTy = VectorType::get(Builder.getHalfTy(), 8, true);
   Type *DstVecTy = VectorType::get(Builder.getInt32Ty(), 4, true);
-  Type *PredTy = VectorType::get(Builder.getInt1Ty(), 16, true);
+  Type *PredTy = VectorType::get(Builder.getInt1Ty(), 4, true);
 
   SmallVector<Value*, 3> ArgTys;
   ArgTys.push_back(UndefValue::get(DstVecTy));