diff --git a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp --- a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp +++ b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp @@ -126,7 +126,9 @@ for (MachineBasicBlock::succ_iterator S = MBB.succ_begin(), E = MBB.succ_end(); S != E; S++) for (const auto &LI : (*S)->liveins()) - LivePhysRegs.set(LI.PhysReg); + for (MCSubRegIterator SR(LI.PhysReg, TRI, /*IncludeSelf=*/true); + SR.isValid(); ++SR) + LivePhysRegs.set(*SR); // Now scan the instructions and delete dead ones, tracking physreg // liveness as we go. diff --git a/llvm/test/CodeGen/Hexagon/dead-code-elim-sub-reg-livein.mir b/llvm/test/CodeGen/Hexagon/dead-code-elim-sub-reg-livein.mir new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/dead-code-elim-sub-reg-livein.mir @@ -0,0 +1,35 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=hexagon -run-pass dead-mi-elimination -verify-machineinstrs %s -o - | FileCheck %s + +# DeadMachineCodeElimination needs to add the subregisters of the live-ins of a block to avoid +# deleting instructions writing to parts of a super register. +# This test is making sure that this happens. + +--- +name: livein_sub_reg_not_preserved +tracksRegLiveness: true + +body: | + ; CHECK-LABEL: name: livein_sub_reg_not_preserved + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: liveins: $d0, $r2 + ; CHECK: bb.1: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: liveins: $d0, $r2 + ; CHECK: $r0 = A2_tfrsi 1 + ; CHECK: A2_nop implicit-def $p0 + ; CHECK: J2_jumpt killed $p0, %bb.1, implicit-def dead $pc + ; CHECK: J2_jumpr $r31, implicit-def dead $pc + bb.0: + liveins: $d0, $r2 + successors: %bb.1 + + bb.1: + successors: %bb.1 + liveins: $d0, $r2 + $r0 = A2_tfrsi 1 + A2_nop implicit-def $p0 + J2_jumpt killed $p0, %bb.1, implicit-def dead $pc + J2_jumpr $r31, implicit-def dead $pc +...