diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -1512,7 +1512,8 @@
 
   /// Copy implicit register operands from specified
   /// instruction to this instruction.
-  void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
+  void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI,
+                       bool SkipDuplicated = false);
 
   /// Debugging support
   /// @{
diff --git a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
--- a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -300,8 +300,9 @@
 
   /// Copy all the implicit operands from OtherMI onto this one.
   const MachineInstrBuilder &
-  copyImplicitOps(const MachineInstr &OtherMI) const {
-    MI->copyImplicitOps(*MF, OtherMI);
+  copyImplicitOps(const MachineInstr &OtherMI,
+                  bool SkipDuplicated = false) const {
+    MI->copyImplicitOps(*MF, OtherMI, SkipDuplicated);
     return *this;
   }
 
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1416,13 +1416,17 @@
 
 /// copyImplicitOps - Copy implicit register operands from specified
 /// instruction to this instruction.
-void MachineInstr::copyImplicitOps(MachineFunction &MF,
-                                   const MachineInstr &MI) {
+void MachineInstr::copyImplicitOps(MachineFunction &MF, const MachineInstr &MI,
+                                   bool SkipDuplicated) {
   for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
        i != e; ++i) {
     const MachineOperand &MO = MI.getOperand(i);
-    if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
+    if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) {
+      if (SkipDuplicated && (findRegisterUseOperandIdx(MO.getReg()) != -1 ||
+                             findRegisterDefOperandIdx(MO.getReg()) != -1))
+        continue;
       addOperand(MF, MO);
+    }
   }
 }
 
diff --git a/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp b/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
--- a/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
+++ b/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
@@ -78,7 +78,7 @@
               // This is an unconditional branch to the return. Replace the
               // branch with a blr.
               BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode()))
-                  .copyImplicitOps(*I);
+                  .copyImplicitOps(*I, true);
               MachineBasicBlock::iterator K = J--;
               K->eraseFromParent();
               BlockChanged = true;
@@ -92,7 +92,7 @@
               BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCCLR))
                   .addImm(J->getOperand(0).getImm())
                   .addReg(J->getOperand(1).getReg())
-                  .copyImplicitOps(*I);
+                  .copyImplicitOps(*I, true);
               MachineBasicBlock::iterator K = J--;
               K->eraseFromParent();
               BlockChanged = true;
@@ -107,7 +107,7 @@
                   **PI, J, J->getDebugLoc(),
                   TII->get(J->getOpcode() == PPC::BC ? PPC::BCLR : PPC::BCLRn))
                   .addReg(J->getOperand(0).getReg())
-                  .copyImplicitOps(*I);
+                  .copyImplicitOps(*I, true);
               MachineBasicBlock::iterator K = J--;
               K->eraseFromParent();
               BlockChanged = true;
diff --git a/llvm/test/CodeGen/PowerPC/early-ret-verify.mir b/llvm/test/CodeGen/PowerPC/early-ret-verify.mir
--- a/llvm/test/CodeGen/PowerPC/early-ret-verify.mir
+++ b/llvm/test/CodeGen/PowerPC/early-ret-verify.mir
@@ -40,7 +40,7 @@
 
   ; CHECK-LABEL: testEarlyRet
   ; CHECK: bb.0.entry:
-  ; CHECK:   BCLR $cr5lt, implicit $lr, implicit $rm, implicit $lr, implicit $rm
+  ; CHECK:   BCLR $cr5lt, implicit $lr, implicit $rm
   ; CHECK: bb.1:
   ; CHECK:   renamable $r3 = IMPLICIT_DEF
   ; CHECK:   renamable $r4 = IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/PowerPC/early-ret.mir b/llvm/test/CodeGen/PowerPC/early-ret.mir
--- a/llvm/test/CodeGen/PowerPC/early-ret.mir
+++ b/llvm/test/CodeGen/PowerPC/early-ret.mir
@@ -27,7 +27,7 @@
   ; CHECK: bb.0.entry:
   ; CHECK:   renamable $cr0 = CMPWI renamable $r3, 0
   ; CHECK:   BC killed renamable $cr0gt, %bb.1
-  ; CHECK:   BLR implicit $lr, implicit $rm, implicit $lr, implicit $rm, implicit killed $r3
+  ; CHECK:   BLR implicit $lr, implicit $rm, implicit killed $r3
   ; CHECK: bb.1.entry:
   ; CHECK:   renamable $r3 = ADDI killed renamable $r4, 0
   ; CHECK:   BLR implicit $lr, implicit $rm, implicit killed $r3
@@ -106,7 +106,7 @@
   ; CHECK-LABEL: name: testBCLR
   ; CHECK: bb.0.entry:
   ; CHECK:   renamable $cr0 = FCMPUS killed renamable $f3, killed renamable $f4
-  ; CHECK:   BCLR $cr0eq, implicit $lr, implicit $rm, implicit $lr, implicit $rm, implicit killed $v2
+  ; CHECK:   BCLR $cr0eq, implicit $lr, implicit $rm, implicit killed $v2
   ; CHECK: bb.1.entry:
   ; CHECK:   renamable $cr0 = FCMPUS killed renamable $f1, killed renamable $f2
   ; CHECK:   BCLRn killed renamable $cr0eq, implicit $lr, implicit $rm, implicit killed $v2
@@ -139,8 +139,8 @@
   ; CHECK: bb.0.entry:
   ; CHECK: renamable $r4 = LI 0
   ; CHECK: renamable $cr0 = CMPLWI killed renamable $r4, 0
-  ; CHECK: BCCLR 68, $cr0, implicit $lr, implicit $rm, implicit $lr, implicit $rm
+  ; CHECK: BCCLR 68, $cr0, implicit $lr, implicit $rm
   ; CHECK: bb.1:
-  ; CHECK: BCCLR 68, $cr0, implicit $lr, implicit $rm, implicit $lr, implicit $rm
+  ; CHECK: BCCLR 68, $cr0, implicit $lr, implicit $rm
   ; CHECK: BLR implicit $lr, implicit $rm
 ...