Index: llvm/include/llvm/CodeGen/TargetLowering.h =================================================================== --- llvm/include/llvm/CodeGen/TargetLowering.h +++ llvm/include/llvm/CodeGen/TargetLowering.h @@ -3597,7 +3597,7 @@ ArgListTy Args; SelectionDAG &DAG; SDLoc DL; - ImmutableCallSite CS; + const CallBase *CB = nullptr; SmallVector Outs; SmallVector OutVals; SmallVector Ins; @@ -3644,16 +3644,15 @@ CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy, SDValue Target, ArgListTy &&ArgsList, - ImmutableCallSite Call) { + const CallBase &Call) { RetTy = ResultType; IsInReg = Call.hasRetAttr(Attribute::InReg); DoesNotReturn = Call.doesNotReturn() || - (!Call.isInvoke() && - isa(Call.getInstruction()->getNextNode())); + (!isa(Call) && isa(Call.getNextNode())); IsVarArg = FTy->isVarArg(); - IsReturnValueUsed = !Call.getInstruction()->use_empty(); + IsReturnValueUsed = !Call.use_empty(); RetSExt = Call.hasRetAttr(Attribute::SExt); RetZExt = Call.hasRetAttr(Attribute::ZExt); @@ -3663,7 +3662,7 @@ NumFixedArgs = FTy->getNumParams(); Args = std::move(ArgsList); - CS = Call; + CB = &Call; return *this; } Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h =================================================================== --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h @@ -557,7 +557,7 @@ bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB); void CopyToExportRegsIfNeeded(const Value *V); void ExportFromCurrentBlock(const Value *V); - void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall, + void LowerCallTo(const CallBase &CB, SDValue Callee, bool IsTailCall, const BasicBlock *EHPadBB = nullptr); // Lower range metadata from 0 to N to assert zext to an integer of nearest Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp =================================================================== --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -2817,7 +2817,7 @@ // with deopt state. LowerCallSiteWithDeoptBundle(&I, getValue(Callee), EHPadBB); } else { - LowerCallTo(&I, getValue(Callee), false, EHPadBB); + LowerCallTo(I, getValue(Callee), false, EHPadBB); } // If the value of the invoke is used outside of its defining block, make it @@ -5622,7 +5622,7 @@ SDValue Callee = DAG.getExternalSymbol( FunctionName, DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout())); - LowerCallTo(&I, Callee, I.isTailCall()); + LowerCallTo(I, Callee, I.isTailCall()); } /// Lower the call to the specified intrinsic function. @@ -7039,10 +7039,9 @@ // There is a platform (e.g. wasm) that uses funclet style IR but does not // actually use outlined funclets and their LSDA info style. if (MF.hasEHFunclets() && isFuncletEHPersonality(Pers)) { - assert(CLI.CS); + assert(CLI.CB); WinEHFuncInfo *EHInfo = DAG.getMachineFunction().getWinEHFuncInfo(); - EHInfo->addIPToStateRange(cast(CLI.CS.getInstruction()), - BeginLabel, EndLabel); + EHInfo->addIPToStateRange(cast(CLI.CB), BeginLabel, EndLabel); } else if (!isScopedEHPersonality(Pers)) { MF.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel); } @@ -7051,15 +7050,15 @@ return Result; } -void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, +void SelectionDAGBuilder::LowerCallTo(const CallBase &CB, SDValue Callee, bool isTailCall, const BasicBlock *EHPadBB) { auto &DL = DAG.getDataLayout(); - FunctionType *FTy = CS.getFunctionType(); - Type *RetTy = CS.getType(); + FunctionType *FTy = CB.getFunctionType(); + Type *RetTy = CB.getType(); TargetLowering::ArgListTy Args; - Args.reserve(CS.arg_size()); + Args.reserve(CB.arg_size()); const Value *SwiftErrorVal = nullptr; const TargetLowering &TLI = DAG.getTargetLoweringInfo(); @@ -7067,7 +7066,7 @@ if (isTailCall) { // Avoid emitting tail calls in functions with the disable-tail-calls // attribute. - auto *Caller = CS.getInstruction()->getParent()->getParent(); + auto *Caller = CB.getParent()->getParent(); if (Caller->getFnAttribute("disable-tail-calls").getValueAsString() == "true") isTailCall = false; @@ -7080,10 +7079,9 @@ isTailCall = false; } - for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); - i != e; ++i) { + for (auto I = CB.arg_begin(), E = CB.arg_end(); I != E; ++I) { TargetLowering::ArgListEntry Entry; - const Value *V = *i; + const Value *V = *I; // Skip empty types if (V->getType()->isEmptyTy()) @@ -7092,16 +7090,16 @@ SDValue ArgNode = getValue(V); Entry.Node = ArgNode; Entry.Ty = V->getType(); - Entry.setAttributes(&CS, i - CS.arg_begin()); + Entry.setAttributes(&CB, I - CB.arg_begin()); // Use swifterror virtual register as input to the call. if (Entry.IsSwiftError && TLI.supportSwiftError()) { SwiftErrorVal = V; // We find the virtual register for the actual swifterror argument. // Instead of using the Value, we use the virtual register instead. - Entry.Node = DAG.getRegister( - SwiftError.getOrCreateVRegUseAt(CS.getInstruction(), FuncInfo.MBB, V), - EVT(TLI.getPointerTy(DL))); + Entry.Node = + DAG.getRegister(SwiftError.getOrCreateVRegUseAt(&CB, FuncInfo.MBB, V), + EVT(TLI.getPointerTy(DL))); } Args.push_back(Entry); @@ -7114,7 +7112,7 @@ // If call site has a cfguardtarget operand bundle, create and add an // additional ArgListEntry. - if (auto Bundle = CS.getOperandBundle(LLVMContext::OB_cfguardtarget)) { + if (auto Bundle = CB.getOperandBundle(LLVMContext::OB_cfguardtarget)) { TargetLowering::ArgListEntry Entry; Value *V = Bundle->Inputs[0]; SDValue ArgNode = getValue(V); @@ -7126,7 +7124,8 @@ // Check if target-independent constraints permit a tail call here. // Target-dependent constraints are checked within TLI->LowerCallTo. - if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget())) + if (isTailCall && + !isInTailCallPosition(ImmutableCallSite(&CB), DAG.getTarget())) isTailCall = false; // Disable tail calls if there is an swifterror argument. Targets have not @@ -7137,15 +7136,14 @@ TargetLowering::CallLoweringInfo CLI(DAG); CLI.setDebugLoc(getCurSDLoc()) .setChain(getRoot()) - .setCallee(RetTy, FTy, Callee, std::move(Args), CS) + .setCallee(RetTy, FTy, Callee, std::move(Args), CB) .setTailCall(isTailCall) - .setConvergent(CS.isConvergent()); + .setConvergent(CB.isConvergent()); std::pair Result = lowerInvokable(CLI, EHPadBB); if (Result.first.getNode()) { - const Instruction *Inst = CS.getInstruction(); - Result.first = lowerRangeToAssertZExt(DAG, *Inst, Result.first); - setValue(Inst, Result.first); + Result.first = lowerRangeToAssertZExt(DAG, CB, Result.first); + setValue(&CB, Result.first); } // The last element of CLI.InVals has the SDValue for swifterror return. @@ -7154,8 +7152,8 @@ if (SwiftErrorVal && TLI.supportSwiftError()) { // Get the last element of InVals. SDValue Src = CLI.InVals.back(); - Register VReg = SwiftError.getOrCreateVRegDefAt( - CS.getInstruction(), FuncInfo.MBB, SwiftErrorVal); + Register VReg = + SwiftError.getOrCreateVRegDefAt(&CB, FuncInfo.MBB, SwiftErrorVal); SDValue CopyNode = CLI.DAG.getCopyToReg(Result.second, CLI.DL, VReg, Src); DAG.setRoot(CopyNode); } @@ -7679,7 +7677,7 @@ // Check if we can potentially perform a tail call. More detailed checking // is be done within LowerCallTo, after more information about the call is // known. - LowerCallTo(&I, Callee, I.isTailCall()); + LowerCallTo(I, Callee, I.isTailCall()); } namespace { @@ -9196,8 +9194,8 @@ Flags.setReturned(); } - getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT, - CLI.CS.getInstruction(), CLI.CallConv, ExtendKind); + getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT, CLI.CB, + CLI.CallConv, ExtendKind); for (unsigned j = 0; j != NumParts; ++j) { // if it isn't first piece, alignment must be 1 Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -4069,7 +4069,7 @@ // Check if it's really possible to do a tail call. IsTailCall = isEligibleForTailCallOptimization( Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG); - if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall()) + if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall()) report_fatal_error("failed to perform tail call elimination on a call " "site marked musttail"); @@ -4179,7 +4179,7 @@ SmallVector MemOpChains; auto PtrVT = getPointerTy(DAG.getDataLayout()); - if (IsVarArg && CLI.CS && CLI.CS.isMustTailCall()) { + if (IsVarArg && CLI.CB && CLI.CB->isMustTailCall()) { const auto &Forwards = FuncInfo->getForwardedMustTailRegParms(); for (const auto &F : Forwards) { SDValue Val = DAG.getCopyFromReg(Chain, DL, F.VReg, F.VT); Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp =================================================================== --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -2464,7 +2464,7 @@ SDValue Chain) const { // If we don't have a call site, this was a call inserted by // legalization. These can never use special inputs. - if (!CLI.CS) + if (!CLI.CB) return; SelectionDAG &DAG = CLI.DAG; @@ -2475,7 +2475,7 @@ const AMDGPUFunctionArgInfo *CalleeArgInfo = &AMDGPUArgumentUsageInfo::FixedABIFunctionInfo; - if (const Function *CalleeFunc = CLI.CS.getCalledFunction()) { + if (const Function *CalleeFunc = CLI.CB->getCalledFunction()) { auto &ArgUsageInfo = DAG.getPass()->getAnalysis(); CalleeArgInfo = &ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc); @@ -2726,10 +2726,11 @@ "unsupported call to variadic function "); } - if (!CLI.CS.getInstruction()) + if (!CLI.CB) report_fatal_error("unsupported libcall legalization"); - if (!AMDGPUTargetMachine::EnableFixedFunctionABI && !CLI.CS.getCalledFunction()) { + if (!AMDGPUTargetMachine::EnableFixedFunctionABI && + !CLI.CB->getCalledFunction()) { return lowerUnhandledCall(CLI, InVals, "unsupported indirect call to function "); } @@ -2749,7 +2750,7 @@ if (IsTailCall) { IsTailCall = isEligibleForTailCallOptimization( Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG); - if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall()) { + if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall()) { report_fatal_error("failed to perform tail call elimination on a call " "site marked musttail"); } Index: llvm/lib/Target/ARM/ARMISelLowering.cpp =================================================================== --- llvm/lib/Target/ARM/ARMISelLowering.cpp +++ llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -2139,8 +2139,8 @@ // more times in this block, we can improve codesize by calling indirectly // as BLXr has a 16-bit encoding. auto *GV = cast(Callee)->getGlobal(); - if (CLI.CS) { - auto *BB = CLI.CS.getParent(); + if (CLI.CB) { + auto *BB = CLI.CB->getParent(); PreferIndirect = Subtarget->isThumb() && Subtarget->hasMinSize() && count_if(GV->users(), [&BB](const User *U) { return isa(U) && @@ -2154,7 +2154,7 @@ Callee, CallConv, isVarArg, isStructRet, MF.getFunction().hasStructRetAttr(), Outs, OutVals, Ins, DAG, PreferIndirect); - if (!isTailCall && CLI.CS && CLI.CS.isMustTailCall()) + if (!isTailCall && CLI.CB && CLI.CB->isMustTailCall()) report_fatal_error("failed to perform tail call elimination on a call " "site marked musttail"); // We don't support GuaranteedTailCallOpt for ARM, only automatically Index: llvm/lib/Target/Hexagon/HexagonISelLowering.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -387,9 +387,7 @@ MachineFrameInfo &MFI = MF.getFrameInfo(); auto PtrVT = getPointerTy(MF.getDataLayout()); - unsigned NumParams = CLI.CS.getInstruction() - ? CLI.CS.getFunctionType()->getNumParams() - : 0; + unsigned NumParams = CLI.CB ? CLI.CB->getFunctionType()->getNumParams() : 0; if (GlobalAddressSDNode *GAN = dyn_cast(Callee)) Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32); Index: llvm/lib/Target/Mips/MipsISelLowering.cpp =================================================================== --- llvm/lib/Target/Mips/MipsISelLowering.cpp +++ llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -3231,7 +3231,7 @@ G->getGlobal()->hasProtectedVisibility()); } } - if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall()) + if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall()) report_fatal_error("failed to perform tail call elimination on a call " "site marked musttail"); Index: llvm/lib/Target/NVPTX/NVPTXISelLowering.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXISelLowering.h +++ llvm/lib/Target/NVPTX/NVPTXISelLowering.h @@ -491,7 +491,7 @@ std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &, const SmallVectorImpl &, - MaybeAlign retAlignment, ImmutableCallSite CS) const; + MaybeAlign retAlignment, const CallBase &CB) const; SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl &Outs, @@ -578,7 +578,7 @@ SelectionDAG &DAG) const override; SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; - Align getArgumentAlignment(SDValue Callee, ImmutableCallSite CS, Type *Ty, + Align getArgumentAlignment(SDValue Callee, const CallBase *CB, Type *Ty, unsigned Idx, const DataLayout &DL) const; }; } // namespace llvm Index: llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -1243,7 +1243,7 @@ std::string NVPTXTargetLowering::getPrototype( const DataLayout &DL, Type *retTy, const ArgListTy &Args, const SmallVectorImpl &Outs, MaybeAlign retAlignment, - ImmutableCallSite CS) const { + const CallBase &CB) const { auto PtrVT = getPointerTy(DL); bool isABI = (STI.getSmVersion() >= 20); @@ -1300,7 +1300,7 @@ if (!Outs[OIdx].Flags.isByVal()) { if (Ty->isAggregateType() || Ty->isVectorTy() || Ty->isIntegerTy(128)) { unsigned align = 0; - const CallInst *CallI = cast(CS.getInstruction()); + const CallInst *CallI = cast(&CB); // +1 because index 0 is reserved for return type alignment if (!getAlign(*CallI, i + 1, align)) align = DL.getABITypeAlignment(Ty); @@ -1353,30 +1353,28 @@ } Align NVPTXTargetLowering::getArgumentAlignment(SDValue Callee, - ImmutableCallSite CS, Type *Ty, + const CallBase *CB, Type *Ty, unsigned Idx, const DataLayout &DL) const { - if (!CS) { + if (!CB) { // CallSite is zero, fallback to ABI type alignment return DL.getABITypeAlign(Ty); } unsigned Alignment = 0; - const Value *DirectCallee = CS.getCalledFunction(); + const Value *DirectCallee = CB->getCalledFunction(); if (!DirectCallee) { // We don't have a direct function symbol, but that may be because of // constant cast instructions in the call. - const Instruction *CalleeI = CS.getInstruction(); - assert(CalleeI && "Call target is not a function or derived value?"); // With bitcast'd call targets, the instruction will be the call - if (isa(CalleeI)) { + if (isa(CB)) { // Check if we have call alignment metadata - if (getAlign(*cast(CalleeI), Idx, Alignment)) + if (getAlign(*cast(CB), Idx, Alignment)) return Align(Alignment); - const Value *CalleeV = cast(CalleeI)->getCalledValue(); + const Value *CalleeV = cast(CB)->getCalledValue(); // Ignore any bitcast instructions while (isa(CalleeV)) { const ConstantExpr *CE = cast(CalleeV); @@ -1416,7 +1414,7 @@ bool &isTailCall = CLI.IsTailCall; ArgListTy &Args = CLI.getArgs(); Type *RetTy = CLI.RetTy; - ImmutableCallSite CS = CLI.CS; + const CallBase *CB = CLI.CB; const DataLayout &DL = DAG.getDataLayout(); bool isABI = (STI.getSmVersion() >= 20); @@ -1449,7 +1447,7 @@ SmallVector VTs; SmallVector Offsets; ComputePTXValueVTs(*this, DL, Ty, VTs, &Offsets); - Align ArgAlign = getArgumentAlignment(Callee, CS, Ty, paramCount + 1, DL); + Align ArgAlign = getArgumentAlignment(Callee, CB, Ty, paramCount + 1, DL); unsigned AllocSize = DL.getTypeAllocSize(Ty); SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue); bool NeedAlign; // Does argument declaration specify alignment? @@ -1641,7 +1639,7 @@ DeclareRetOps); InFlag = Chain.getValue(1); } else { - retAlignment = getArgumentAlignment(Callee, CS, RetTy, 0, DL); + retAlignment = getArgumentAlignment(Callee, CB, RetTy, 0, DL); assert(retAlignment && "retAlignment is guaranteed to be set"); SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDValue DeclareRetOps[] = { @@ -1657,7 +1655,7 @@ // Both indirect calls and libcalls have nullptr Func. In order to distinguish // between them we must rely on the call site value which is valid for // indirect calls but is always null for libcalls. - bool isIndirectCall = !Func && CS; + bool isIndirectCall = !Func && CB; if (isa(Callee)) { Function* CalleeFunc = nullptr; @@ -1680,7 +1678,7 @@ // The prototype is embedded in a string and put as the operand for a // CallPrototype SDNode which will print out to the value of the string. SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue); - std::string Proto = getPrototype(DL, RetTy, Args, Outs, retAlignment, CS); + std::string Proto = getPrototype(DL, RetTy, Args, Outs, retAlignment, *CB); const char *ProtoStr = nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str(); SDValue ProtoOps[] = { @@ -1753,7 +1751,7 @@ ComputePTXValueVTs(*this, DL, RetTy, VTs, &Offsets, 0); assert(VTs.size() == Ins.size() && "Bad value decomposition"); - Align RetAlign = getArgumentAlignment(Callee, CS, RetTy, 0, DL); + Align RetAlign = getArgumentAlignment(Callee, CB, RetTy, 0, DL); auto VectorInfo = VectorizePTXValueVTs(VTs, Offsets, RetAlign); SmallVector LoadVTs; Index: llvm/lib/Target/PowerPC/PPCISelLowering.h =================================================================== --- llvm/lib/Target/PowerPC/PPCISelLowering.h +++ llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -1053,15 +1053,10 @@ const SmallVectorImpl &Ins, SelectionDAG& DAG) const; - bool - IsEligibleForTailCallOptimization_64SVR4( - SDValue Callee, - CallingConv::ID CalleeCC, - ImmutableCallSite CS, - bool isVarArg, - const SmallVectorImpl &Outs, - const SmallVectorImpl &Ins, - SelectionDAG& DAG) const; + bool IsEligibleForTailCallOptimization_64SVR4( + SDValue Callee, CallingConv::ID CalleeCC, const CallBase *CB, + bool isVarArg, const SmallVectorImpl &Outs, + const SmallVectorImpl &Ins, SelectionDAG &DAG) const; SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut, @@ -1128,7 +1123,7 @@ SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl &Ins, SmallVectorImpl &InVals, - ImmutableCallSite CS) const; + const CallBase *CB) const; SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, @@ -1181,28 +1176,28 @@ const SmallVectorImpl &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl &InVals, - ImmutableCallSite CS) const; + const CallBase *CB) const; SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags, const SmallVectorImpl &Outs, const SmallVectorImpl &OutVals, const SmallVectorImpl &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl &InVals, - ImmutableCallSite CS) const; + const CallBase *CB) const; SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags, const SmallVectorImpl &Outs, const SmallVectorImpl &OutVals, const SmallVectorImpl &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl &InVals, - ImmutableCallSite CS) const; + const CallBase *CB) const; SDValue LowerCall_AIX(SDValue Chain, SDValue Callee, CallFlags CFlags, const SmallVectorImpl &Outs, const SmallVectorImpl &OutVals, const SmallVectorImpl &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl &InVals, - ImmutableCallSite CS) const; + const CallBase *CB) const; SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -4684,13 +4684,12 @@ return false; } -static bool -hasSameArgumentList(const Function *CallerFn, ImmutableCallSite CS) { - if (CS.arg_size() != CallerFn->arg_size()) +static bool hasSameArgumentList(const Function *CallerFn, const CallBase *CB) { + if (CB->arg_size() != CallerFn->arg_size()) return false; - ImmutableCallSite::arg_iterator CalleeArgIter = CS.arg_begin(); - ImmutableCallSite::arg_iterator CalleeArgEnd = CS.arg_end(); + auto CalleeArgIter = CB->arg_begin(); + auto CalleeArgEnd = CB->arg_end(); Function::const_arg_iterator CallerArgIter = CallerFn->arg_begin(); for (; CalleeArgIter != CalleeArgEnd; ++CalleeArgIter, ++CallerArgIter) { @@ -4732,15 +4731,10 @@ return CallerCC == CallingConv::C || CallerCC == CalleeCC; } -bool -PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4( - SDValue Callee, - CallingConv::ID CalleeCC, - ImmutableCallSite CS, - bool isVarArg, - const SmallVectorImpl &Outs, - const SmallVectorImpl &Ins, - SelectionDAG& DAG) const { +bool PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4( + SDValue Callee, CallingConv::ID CalleeCC, const CallBase *CB, bool isVarArg, + const SmallVectorImpl &Outs, + const SmallVectorImpl &Ins, SelectionDAG &DAG) const { bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt; // FIXME: Tail calls are currently disabled when using PC Relative addressing. @@ -4812,7 +4806,7 @@ // If callee use the same argument list that caller is using, then we can // apply SCO on this case. If it is not, then we need to check if callee needs // stack for passing arguments. - if (!hasSameArgumentList(&Caller, CS) && + if (!hasSameArgumentList(&Caller, CB) && needStackSlotPassParameters(Subtarget, Outs)) { return false; } @@ -5296,7 +5290,7 @@ static void prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, SDValue CallSeqStart, - ImmutableCallSite CS, const SDLoc &dl, + const CallBase *CB, const SDLoc &dl, bool hasNest, const PPCSubtarget &Subtarget) { // Function pointers in the 64-bit SVR4 ABI do not point to the function @@ -5332,7 +5326,7 @@ MachineMemOperand::MOInvariant) : MachineMemOperand::MONone; - MachinePointerInfo MPI(CS ? CS.getCalledValue() : nullptr); + MachinePointerInfo MPI(CB ? CB->getCalledValue() : nullptr); // Registers used in building the DAG. const MCRegister EnvPtrReg = Subtarget.getEnvironmentPointerRegister(); @@ -5471,7 +5465,7 @@ SmallVector, 8> &RegsToPass, SDValue Glue, SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl &Ins, - SmallVectorImpl &InVals, ImmutableCallSite CS) const { + SmallVectorImpl &InVals, const CallBase *CB) const { if ((Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()) || Subtarget.isAIXABI()) @@ -5484,7 +5478,7 @@ if (!CFlags.IsIndirect) Callee = transformCallee(Callee, DAG, dl, Subtarget); else if (Subtarget.usesFunctionDescriptors()) - prepareDescriptorIndirectCall(DAG, Callee, Glue, Chain, CallSeqStart, CS, + prepareDescriptorIndirectCall(DAG, Callee, Glue, Chain, CallSeqStart, CB, dl, CFlags.HasNest, Subtarget); else prepareIndirectCall(DAG, Callee, Glue, Chain, dl); @@ -5544,15 +5538,14 @@ CallingConv::ID CallConv = CLI.CallConv; bool isVarArg = CLI.IsVarArg; bool isPatchPoint = CLI.IsPatchPoint; - ImmutableCallSite CS = CLI.CS; + const CallBase *CB = CLI.CB; if (isTailCall) { - if (Subtarget.useLongCalls() && !(CS && CS.isMustTailCall())) + if (Subtarget.useLongCalls() && !(CB && CB->isMustTailCall())) isTailCall = false; else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) - isTailCall = - IsEligibleForTailCallOptimization_64SVR4(Callee, CallConv, CS, - isVarArg, Outs, Ins, DAG); + isTailCall = IsEligibleForTailCallOptimization_64SVR4( + Callee, CallConv, CB, isVarArg, Outs, Ins, DAG); else isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, Ins, DAG); @@ -5575,7 +5568,7 @@ } } - if (!isTailCall && CS && CS.isMustTailCall()) + if (!isTailCall && CB && CB->isMustTailCall()) report_fatal_error("failed to perform tail call elimination on a call " "site marked musttail"); @@ -5595,18 +5588,18 @@ if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) return LowerCall_64SVR4(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG, - InVals, CS); + InVals, CB); if (Subtarget.isSVR4ABI()) return LowerCall_32SVR4(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG, - InVals, CS); + InVals, CB); if (Subtarget.isAIXABI()) return LowerCall_AIX(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG, - InVals, CS); + InVals, CB); return LowerCall_Darwin(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG, - InVals, CS); + InVals, CB); } SDValue PPCTargetLowering::LowerCall_32SVR4( @@ -5615,7 +5608,7 @@ const SmallVectorImpl &OutVals, const SmallVectorImpl &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl &InVals, - ImmutableCallSite CS) const { + const CallBase *CB) const { // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description // of the 32-bit SVR4 ABI stack frame layout. @@ -5843,7 +5836,7 @@ TailCallArguments); return FinishCall(CFlags, dl, DAG, RegsToPass, InFlag, Chain, CallSeqStart, - Callee, SPDiff, NumBytes, Ins, InVals, CS); + Callee, SPDiff, NumBytes, Ins, InVals, CB); } // Copy an argument into memory, being careful to do this outside the @@ -5869,7 +5862,7 @@ const SmallVectorImpl &OutVals, const SmallVectorImpl &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl &InVals, - ImmutableCallSite CS) const { + const CallBase *CB) const { bool isELFv2ABI = Subtarget.isELFv2ABI(); bool isLittleEndian = Subtarget.isLittleEndian(); unsigned NumOps = Outs.size(); @@ -6515,7 +6508,7 @@ TailCallArguments); return FinishCall(CFlags, dl, DAG, RegsToPass, InFlag, Chain, CallSeqStart, - Callee, SPDiff, NumBytes, Ins, InVals, CS); + Callee, SPDiff, NumBytes, Ins, InVals, CB); } SDValue PPCTargetLowering::LowerCall_Darwin( @@ -6524,7 +6517,7 @@ const SmallVectorImpl &OutVals, const SmallVectorImpl &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl &InVals, - ImmutableCallSite CS) const { + const CallBase *CB) const { unsigned NumOps = Outs.size(); EVT PtrVT = getPointerTy(DAG.getDataLayout()); @@ -6893,7 +6886,7 @@ TailCallArguments); return FinishCall(CFlags, dl, DAG, RegsToPass, InFlag, Chain, CallSeqStart, - Callee, SPDiff, NumBytes, Ins, InVals, CS); + Callee, SPDiff, NumBytes, Ins, InVals, CB); } static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT, @@ -7294,7 +7287,7 @@ const SmallVectorImpl &OutVals, const SmallVectorImpl &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl &InVals, - ImmutableCallSite CS) const { + const CallBase *CB) const { assert((CFlags.CallConv == CallingConv::C || CFlags.CallConv == CallingConv::Cold || @@ -7540,7 +7533,7 @@ const int SPDiff = 0; return FinishCall(CFlags, dl, DAG, RegsToPass, InFlag, Chain, CallSeqStart, - Callee, SPDiff, NumBytes, Ins, InVals, CS); + Callee, SPDiff, NumBytes, Ins, InVals, CB); } bool Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -2152,7 +2152,7 @@ if (IsTailCall) ++NumTailCalls; - else if (CLI.CS && CLI.CS.isMustTailCall()) + else if (CLI.CB && CLI.CB->isMustTailCall()) report_fatal_error("failed to perform tail call elimination on a call " "site marked musttail"); Index: llvm/lib/Target/Sparc/SparcISelLowering.cpp =================================================================== --- llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -692,9 +692,9 @@ } static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, - ImmutableCallSite CS) { - if (CS) - return CS.hasFnAttr(Attribute::ReturnsTwice); + const CallBase *Call) { + if (Call) + return Call->hasFnAttr(Attribute::ReturnsTwice); const Function *CalleeFn = nullptr; if (GlobalAddressSDNode *G = dyn_cast(Callee)) { @@ -936,7 +936,7 @@ InFlag = Chain.getValue(1); } - bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS); + bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CB); // If the callee is a GlobalAddress node (quite common, every direct call is) // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. @@ -1243,7 +1243,7 @@ // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. // Likewise ExternalSymbol -> TargetExternalSymbol. SDValue Callee = CLI.Callee; - bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS); + bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CB); unsigned TF = isPositionIndependent() ? SparcMCExpr::VK_Sparc_WPLT30 : 0; if (GlobalAddressSDNode *G = dyn_cast(Callee)) Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT, 0, TF); @@ -1292,7 +1292,7 @@ // Set inreg flag manually for codegen generated library calls that // return float. - if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CS) + if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CB) CLI.Ins[0].Flags.setInReg(); RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64); Index: llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -707,7 +707,7 @@ if (CLI.IsTailCall) { auto NoTail = [&](const char *Msg) { - if (CLI.CS && CLI.CS.isMustTailCall()) + if (CLI.CB && CLI.CB->isMustTailCall()) fail(DL, DAG, Msg); CLI.IsTailCall = false; }; @@ -735,8 +735,8 @@ "match"); // If pointers to local stack values are passed, we cannot tail call - if (CLI.CS) { - for (auto &Arg : CLI.CS.args()) { + if (CLI.CB) { + for (auto &Arg : CLI.CB->args()) { Value *Val = Arg.get(); // Trace the value back through pointer operations while (true) { Index: llvm/lib/Target/X86/X86ISelLowering.cpp =================================================================== --- llvm/lib/Target/X86/X86ISelLowering.cpp +++ llvm/lib/Target/X86/X86ISelLowering.cpp @@ -3838,11 +3838,11 @@ bool IsGuaranteeTCO = MF.getTarget().Options.GuaranteedTailCallOpt || CallConv == CallingConv::Tail; X86MachineFunctionInfo *X86Info = MF.getInfo(); - const auto *CI = dyn_cast_or_null(CLI.CS.getInstruction()); + const auto *CI = dyn_cast_or_null(CLI.CB); const Function *Fn = CI ? CI->getCalledFunction() : nullptr; bool HasNCSR = (CI && CI->hasFnAttr("no_caller_saved_registers")) || (Fn && Fn->hasFnAttribute("no_caller_saved_registers")); - const auto *II = dyn_cast_or_null(CLI.CS.getInstruction()); + const auto *II = dyn_cast_or_null(CLI.CB); bool HasNoCfCheck = (CI && CI->doesNoCfCheck()) || (II && II->doesNoCfCheck()); const Module *M = MF.getMMI().getModule(); @@ -3865,7 +3865,7 @@ isTailCall = false; } - bool IsMustTail = CLI.CS && CLI.CS.isMustTailCall(); + bool IsMustTail = CLI.CB && CLI.CB->isMustTailCall(); if (IsMustTail) { // Force this to be a tail call. The verifier rules are enough to ensure // that we can lower this successfully without moving the return address @@ -4261,7 +4261,7 @@ // is thrown, the runtime will not restore CSRs. // FIXME: Model this more precisely so that we can register allocate across // the normal edge and spill and fill across the exceptional edge. - if (!Is64Bit && CLI.CS && CLI.CS.isInvoke()) { + if (!Is64Bit && CLI.CB && isa(CLI.CB)) { const Function &CallerFn = MF.getFunction(); EHPersonality Pers = CallerFn.hasPersonalityFn() @@ -4323,8 +4323,8 @@ DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo)); // Save heapallocsite metadata. - if (CLI.CS) - if (MDNode *HeapAlloc = CLI.CS->getMetadata("heapallocsite")) + if (CLI.CB) + if (MDNode *HeapAlloc = CLI.CB->getMetadata("heapallocsite")) DAG.addHeapAllocSite(Chain.getNode(), HeapAlloc); // Create the CALLSEQ_END node.