Index: include/llvm/Target/TargetLowering.h
===================================================================
--- include/llvm/Target/TargetLowering.h
+++ include/llvm/Target/TargetLowering.h
@@ -1071,6 +1071,10 @@
     return false;
   }
 
+ virtual bool shouldSignExtendFloat32InAbiCall() const {
+  return false;
+ }
+
   /// Returns true if the given (atomic) load should be expanded by the
   /// IR-level AtomicExpand pass into a load-linked instruction
   /// (through emitLoadLinked()).
Index: lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -491,13 +491,14 @@
 SDValue DAGTypeLegalizer::SoftenFloatRes_FRINT(SDNode *N) {
   EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   SDValue Op = GetSoftenedFloat(N->getOperand(0));
+  bool shouldSignExtend = TLI.shouldSignExtendFloat32InAbiCall();
   return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
                                            RTLIB::RINT_F32,
                                            RTLIB::RINT_F64,
                                            RTLIB::RINT_F80,
                                            RTLIB::RINT_F128,
                                            RTLIB::RINT_PPCF128),
-                         NVT, &Op, 1, false, SDLoc(N)).first;
+                         NVT, &Op, 1, shouldSignExtend, SDLoc(N)).first;
 }
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FROUND(SDNode *N) {
Index: lib/Target/Mips/MipsISelLowering.h
===================================================================
--- lib/Target/Mips/MipsISelLowering.h
+++ lib/Target/Mips/MipsISelLowering.h
@@ -474,6 +474,7 @@
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
                         const SmallVectorImpl<SDValue> &OutVals,
                         SDLoc dl, SelectionDAG &DAG) const override;
+    bool shouldSignExtendFloat32InAbiCall() const override;
 
     // Inline asm support
     ConstraintType
Index: lib/Target/Mips/MipsISelLowering.cpp
===================================================================
--- lib/Target/Mips/MipsISelLowering.cpp
+++ lib/Target/Mips/MipsISelLowering.cpp
@@ -3030,6 +3030,11 @@
   MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
   return CCInfo.CheckReturn(Outs, RetCC_Mips);
 }
+bool MipsTargetLowering::shouldSignExtendFloat32InAbiCall() const {
+  
+  return Subtarget.hasMips64();
+    
+}
 
 SDValue
 MipsTargetLowering::LowerReturn(SDValue Chain,
Index: test/CodeGen/Mips/mips64rintfsf.ll
===================================================================
--- test/CodeGen/Mips/mips64rintfsf.ll
+++ test/CodeGen/Mips/mips64rintfsf.ll
@@ -0,0 +1,22 @@
+; RUN: llc -march=mips64 -mcpu=mips64r2 -soft-float -O2 < %s | FileCheck %s
+
+define void @foo() #0 {
+entry:
+  %in = alloca float, align 4
+  %out = alloca float, align 4
+  store volatile float 0xBFD59E1380000000, float* %in, align 4
+  %in.0.in.0. = load volatile float* %in, align 4
+  %rintf = tail call float @rintf(float %in.0.in.0.) #1
+  store volatile float %rintf, float* %out, align 4
+  ret void
+
+; CHECK:            rintf
+; CHECK-NOT:        dsll
+; CHECK-NOT:        dsrl
+}
+
+declare float @rintf(float)
+
+attributes #0 = { nounwind "use-soft-float"="true" }
+attributes #1 = { nounwind readnone "use-soft-float"="true" }
+