diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -3854,6 +3854,23 @@
 }
 
 bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
+  LLVM_DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
+                    << "********** Function: " << fn.getName() << '\n');
+
+  // Variables changed between a setjmp and a longjump can have undefined value
+  // after the longjmp. This behaviour can be observed if such a variable is
+  // spilled, so longjmp won't restore the value in the spill slot.
+  // RegisterCoalescer should not run in functions with a setjmp to avoid
+  // merging such undefined variables with predictable ones.
+  //
+  // TODO: Could specifically disable coalescing registers live across setjmp
+  // calls
+  if (fn.exposesReturnsTwice()) {
+    LLVM_DEBUG(
+        dbgs() << "* Skipped as it exposes funcions that returns twice.\n");
+    return false;
+  }
+
   MF = &fn;
   MRI = &fn.getRegInfo();
   const TargetSubtargetInfo &STI = fn.getSubtarget();
@@ -3872,9 +3889,6 @@
   // splitting optimization.
   JoinSplitEdges = EnableJoinSplits;
 
-  LLVM_DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
-                    << "********** Function: " << MF->getName() << '\n');
-
   if (VerifyCoalescing)
     MF->verify(this, "Before register coalescing");
 
diff --git a/llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir b/llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir
@@ -0,0 +1,420 @@
+# RUN: llc -O3 --start-before=stack-coloring -o - %s | FileCheck %s
+# pr45489
+# Coalescing variables across a setjmp call can add a undefined
+# variable value when longjmp if such variables are spilled and
+# altered between the setjmp and longjmp.
+
+# This file tests a very particular case for
+# no spilling a stack pointer live across the
+# setjmp call.
+# CHECK: =>This Inner Loop Header: Depth=1
+# CHECK-NOT: 4-byte Reload
+# CHECK: subs	[[R:r[0-9]]], [[R]], #8
+# CHECK-NOT: 4-byte Spill
+# CHECK: bl	_Z3barPx3S37
+
+--- |
+  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "armv8-arm-none-eabi"
+
+  %struct.S37 = type <{ i8, [7 x i8], %struct.S38, [4 x i64], i32, [4 x i8], i64, i32, [4 x i8] }>
+  %struct.S38 = type { i64, i8 }
+  %struct.S18 = type <{ i32, [4 x i8], i64, i64, i64, i32, [4 x i8], %struct.S23, i32, [4 x i8] }>
+  %struct.S23 = type { [2 x i64], half }
+
+  @__ARM_use_no_argv = global i32 1, section ".ARM.use_no_argv", align 4
+  @llvm.used = appending global [1 x i8*] [i8* bitcast (i32* @__ARM_use_no_argv to i8*)], section "llvm.metadata"
+
+  ; Function Attrs: norecurse
+  define hidden i32 @main() local_unnamed_addr #0 {
+  entry:
+    %P0 = alloca %struct.S37, align 8
+    %jb1 = alloca [20 x i64], align 8
+    %V7 = alloca [16 x i8], align 16
+    %P1 = alloca %struct.S18, align 8
+    %jb2 = alloca [20 x i64], align 8
+    %0 = bitcast %struct.S37* %P0 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 80, i8* nonnull %0) #6
+    %M2.i = getelementptr inbounds %struct.S37, %struct.S37* %P0, i32 0, i32 2
+    %M6.i = getelementptr inbounds %struct.S37, %struct.S37* %P0, i32 0, i32 7
+    store i32 0, i32* %M6.i, align 8, !tbaa !6
+    %1 = bitcast %struct.S38* %M2.i to i8*
+    call void @llvm.memset.p0i8.i64(i8* nonnull align 8 dereferenceable(48) %1, i8 0, i64 48, i1 false) #6
+    %2 = bitcast [20 x i64]* %jb1 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 160, i8* nonnull %2) #6
+    %arraydecay1 = bitcast [20 x i64]* %jb1 to i64*
+    %call1 = call i32 @setjmp(i64* nonnull %arraydecay1) #7
+    %tobool = icmp eq i32 %call1, 0
+    br i1 %tobool, label %if.then, label %if.end
+
+  if.then:                                          ; preds = %entry
+    %3 = bitcast [20 x i64]* %jb1 to i64*
+    call void @_Z3barPx3S37(i64* nonnull %3, %struct.S37* nonnull byval(%struct.S37) align 8 %P0) #8
+    unreachable
+
+  if.end:                                           ; preds = %entry
+    %4 = bitcast [20 x i64]* %jb1 to i8*
+    %5 = bitcast %struct.S37* %P0 to i8*
+    call void @llvm.lifetime.end.p0i8(i64 160, i8* nonnull %4) #6
+    call void @llvm.lifetime.end.p0i8(i64 80, i8* nonnull %5) #6
+    %6 = alloca [128 x i8], align 8
+    %.sub2 = bitcast [128 x i8]* %6 to i8*
+    call void asm sideeffect "", "r"(i8* nonnull %.sub2) #6, !srcloc !14
+    %7 = bitcast [16 x i8]* %V7 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %7) #6
+    call void asm sideeffect "", "r"(i8* nonnull %7) #6, !srcloc !15
+    call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %7) #6
+    %8 = call i8* @llvm.returnaddress(i32 0)
+    call void asm sideeffect "", "r"(i8* %8) #6, !srcloc !16
+    %9 = bitcast %struct.S18* %P1 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 72, i8* nonnull %9) #6
+    %BM0.i = getelementptr inbounds %struct.S18, %struct.S18* %P1, i32 0, i32 2
+    store i64 0, i64* %BM0.i, align 8, !tbaa !17
+    %M0.i = getelementptr inbounds %struct.S18, %struct.S18* %P1, i32 0, i32 5
+    store i32 42, i32* %M0.i, align 8, !tbaa !22
+    %M3.i = getelementptr inbounds %struct.S18, %struct.S18* %P1, i32 0, i32 7
+    %10 = bitcast %struct.S23* %M3.i to i8*
+    call void @llvm.memset.p0i8.i64(i8* nonnull align 8 dereferenceable(28) %10, i8 0, i64 28, i1 false) #6
+    %11 = bitcast [20 x i64]* %jb2 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 160, i8* nonnull %11) #6
+    %arraydecay43 = bitcast [20 x i64]* %jb2 to i64*
+    %call5 = call i32 @setjmp(i64* nonnull %arraydecay43) #7
+    %tobool6 = icmp eq i32 %call5, 0
+    br i1 %tobool6, label %if.then7, label %if.end10
+
+  if.then7:                                         ; preds = %if.end
+    %12 = bitcast [20 x i64]* %jb2 to i64*
+    call void @_Z3fooPx3S18(i64* nonnull %12, %struct.S18* nonnull byval(%struct.S18) align 8 %P1) #8
+    unreachable
+
+  if.end10:                                         ; preds = %if.end
+    %13 = bitcast [20 x i64]* %jb2 to i8*
+    %14 = bitcast %struct.S18* %P1 to i8*
+    call void @llvm.lifetime.end.p0i8(i64 160, i8* nonnull %13) #6
+    call void @llvm.lifetime.end.p0i8(i64 72, i8* nonnull %14) #6
+    ret i32 0
+  }
+
+  ; Function Attrs: argmemonly nounwind willreturn
+  declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1
+
+  ; Function Attrs: nounwind returns_twice
+  declare dso_local i32 @setjmp(i64*) local_unnamed_addr #2
+
+  ; Function Attrs: noreturn
+  declare dso_local void @_Z3barPx3S37(i64*, %struct.S37* byval(%struct.S37) align 8) local_unnamed_addr #3
+
+  ; Function Attrs: argmemonly nounwind willreturn
+  declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1
+
+  ; Function Attrs: nounwind readnone
+  declare i8* @llvm.returnaddress(i32 immarg) #4
+
+  ; Function Attrs: noreturn
+  declare dso_local void @_Z3fooPx3S18(i64*, %struct.S18* byval(%struct.S18) align 8) local_unnamed_addr #3
+
+  ; Function Attrs: argmemonly nounwind willreturn writeonly
+  declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1 immarg) #5
+
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**) #6
+
+  attributes #0 = { norecurse "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+aes,+armv8-a,+crc,+crypto,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp,-thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
+  attributes #1 = { argmemonly nounwind willreturn }
+  attributes #2 = { nounwind returns_twice "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+aes,+armv8-a,+crc,+crypto,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp,-thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
+  attributes #3 = { noreturn "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+aes,+armv8-a,+crc,+crypto,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp,-thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
+  attributes #4 = { nounwind readnone }
+  attributes #5 = { argmemonly nounwind willreturn writeonly }
+  attributes #6 = { nounwind }
+  attributes #7 = { nounwind returns_twice }
+  attributes #8 = { noreturn }
+
+  !llvm.ident = !{!0}
+  !llvm.module.flags = !{!1, !2, !3, !4, !5}
+
+  !0 = !{!""}
+  !1 = !{i32 1, !"wchar_size", i32 4}
+  !2 = !{i32 1, !"static_rwdata", i32 1}
+  !3 = !{i32 1, !"enumsize_buildattr", i32 2}
+  !4 = !{i32 1, !"armlib_unavailable", i32 0}
+  !5 = !{i32 1, !"LTOPostLink", i32 1}
+  !6 = !{!7, !13, i64 72}
+  !7 = !{!"_ZTS3S37", !8, i64 0, !10, i64 8, !8, i64 24, !13, i64 56, !11, i64 64, !13, i64 72}
+  !8 = !{!"omnipotent char", !9, i64 0}
+  !9 = !{!"Simple C++ TBAA"}
+  !10 = !{!"_ZTS3S38", !11, i64 0, !12, i64 8}
+  !11 = !{!"long long", !8, i64 0}
+  !12 = !{!"bool", !8, i64 0}
+  !13 = !{!"int", !8, i64 0}
+  !14 = !{i32 237}
+  !15 = !{i32 326}
+  !16 = !{i32 369}
+  !17 = !{!18, !11, i64 8}
+  !18 = !{!"_ZTS3S18", !13, i64 0, !11, i64 8, !11, i64 16, !11, i64 24, !19, i64 32, !20, i64 40, !13, i64 64}
+  !19 = !{!"long", !8, i64 0}
+  !20 = !{!"_ZTS3S23", !8, i64 0, !21, i64 16}
+  !21 = !{!"__fp16", !8, i64 0}
+  !22 = !{!18, !19, i64 32}
+
+...
+---
+name:            main
+alignment:       4
+exposesReturnsTwice: true
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:
+  - { id: 0, class: qpr, preferred-register: '' }
+  - { id: 1, class: gpr, preferred-register: '' }
+  - { id: 2, class: gpr, preferred-register: '' }
+  - { id: 3, class: gpr, preferred-register: '' }
+  - { id: 4, class: gpr, preferred-register: '' }
+  - { id: 5, class: gpr, preferred-register: '' }
+  - { id: 6, class: gpr, preferred-register: '' }
+  - { id: 7, class: gpr, preferred-register: '' }
+  - { id: 8, class: gpr, preferred-register: '' }
+  - { id: 9, class: gpr, preferred-register: '' }
+  - { id: 10, class: gpr, preferred-register: '' }
+  - { id: 11, class: gpr, preferred-register: '' }
+  - { id: 12, class: qpr, preferred-register: '' }
+  - { id: 13, class: gpr, preferred-register: '' }
+  - { id: 14, class: gpr, preferred-register: '' }
+  - { id: 15, class: gpr, preferred-register: '' }
+  - { id: 16, class: gpr, preferred-register: '' }
+  - { id: 17, class: gpr, preferred-register: '' }
+  - { id: 18, class: gpr, preferred-register: '' }
+  - { id: 19, class: gpr, preferred-register: '' }
+  - { id: 20, class: gpr, preferred-register: '' }
+  - { id: 21, class: gpr, preferred-register: '' }
+  - { id: 22, class: gpr, preferred-register: '' }
+  - { id: 23, class: gpr, preferred-register: '' }
+  - { id: 24, class: gpr, preferred-register: '' }
+  - { id: 25, class: gpr, preferred-register: '' }
+  - { id: 26, class: gpr, preferred-register: '' }
+  - { id: 27, class: gpr, preferred-register: '' }
+  - { id: 28, class: gpr, preferred-register: '' }
+  - { id: 29, class: gpr, preferred-register: '' }
+  - { id: 30, class: gpr, preferred-register: '' }
+  - { id: 31, class: gpr, preferred-register: '' }
+  - { id: 32, class: gpr, preferred-register: '' }
+  - { id: 33, class: gpr, preferred-register: '' }
+  - { id: 34, class: gpr, preferred-register: '' }
+  - { id: 35, class: gpr, preferred-register: '' }
+  - { id: 36, class: gpr, preferred-register: '' }
+  - { id: 37, class: gpr, preferred-register: '' }
+  - { id: 38, class: gpr, preferred-register: '' }
+  - { id: 39, class: gpr, preferred-register: '' }
+  - { id: 40, class: gpr, preferred-register: '' }
+  - { id: 41, class: dpr, preferred-register: '' }
+  - { id: 42, class: gpr, preferred-register: '' }
+  - { id: 43, class: gpr, preferred-register: '' }
+  - { id: 44, class: dpr, preferred-register: '' }
+  - { id: 45, class: gpr, preferred-register: '' }
+  - { id: 46, class: gpr, preferred-register: '' }
+  - { id: 47, class: dpr, preferred-register: '' }
+  - { id: 48, class: gpr, preferred-register: '' }
+  - { id: 49, class: gpr, preferred-register: '' }
+  - { id: 50, class: dpr, preferred-register: '' }
+  - { id: 51, class: gpr, preferred-register: '' }
+  - { id: 52, class: gpr, preferred-register: '' }
+  - { id: 53, class: dpr, preferred-register: '' }
+  - { id: 54, class: gpr, preferred-register: '' }
+  - { id: 55, class: gpr, preferred-register: '' }
+  - { id: 56, class: dpr, preferred-register: '' }
+  - { id: 57, class: gpr, preferred-register: '' }
+  - { id: 58, class: gpr, preferred-register: '' }
+  - { id: 59, class: dpr, preferred-register: '' }
+  - { id: 60, class: gpr, preferred-register: '' }
+  - { id: 61, class: gpr, preferred-register: '' }
+  - { id: 62, class: dpr, preferred-register: '' }
+  - { id: 63, class: gpr, preferred-register: '' }
+  - { id: 64, class: gpr, preferred-register: '' }
+  - { id: 65, class: dpr, preferred-register: '' }
+liveins:
+  - { reg: '$lr', virtual-reg: '%11' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: true
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    16
+  adjustsStack:    true
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 72
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:
+  - { id: 0, name: P0, type: default, offset: 0, size: 80, alignment: 8, 
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: jb1, type: default, offset: 0, size: 160, alignment: 8, 
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 2, name: V7, type: default, offset: 0, size: 16, alignment: 16, 
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 3, name: P1, type: default, offset: 0, size: 72, alignment: 8, 
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 4, name: jb2, type: default, offset: 0, size: 160, alignment: 8, 
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 5, type: variable-sized, offset: 0, 
+      alignment: 1, stack-id: default, callee-saved-register: '', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites:       []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    successors: %bb.1(0x00000001), %bb.2(0x7fffffff)
+    liveins: $lr
+
+    %11:gpr = COPY $lr
+    %0:qpr = VMOVv4i32 0, 14 /* CC::al */, $noreg
+    LIFETIME_START %stack.0.P0
+    %1:gpr = ADDri %stack.0.P0, 0, 14 /* CC::al */, $noreg, $noreg
+    %2:gpr = nuw ADDri %1, 8, 14 /* CC::al */, $noreg, $noreg
+    VST1q64 killed %2, 0, %0, 14 /* CC::al */, $noreg :: (store 16 into %ir.1, align 8)
+    %3:gpr = ADDri %1, 24, 14 /* CC::al */, $noreg, $noreg
+    VST1q64 killed %3, 0, %0, 14 /* CC::al */, $noreg :: (store 16 into %ir.1 + 16, align 8)
+    %4:gpr = ADDri %1, 40, 14 /* CC::al */, $noreg, $noreg
+    VST1q64 killed %4, 0, %0, 14 /* CC::al */, $noreg :: (store 16 into %ir.1 + 32, align 8)
+    %5:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
+    STRi12 killed %5, %stack.0.P0, 72, 14 /* CC::al */, $noreg :: (store 4 into %ir.M6.i, align 8, !tbaa !6)
+    LIFETIME_START %stack.1.jb1
+    ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp
+    %6:gpr = ADDri %stack.1.jb1, 0, 14 /* CC::al */, $noreg, $noreg
+    $r0 = COPY %6
+    BL @setjmp, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def $r0
+    ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp
+    %7:gpr = COPY $r0
+    CMPri %7, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+    Bcc %bb.2, 1 /* CC::ne */, $cpsr
+    B %bb.1
+
+  bb.1.if.then:
+    successors: %bb.5(0x80000000)
+
+    ADJCALLSTACKDOWN 72, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp
+    %28:gpr = ADDri %stack.0.P0, 0, 14 /* CC::al */, $noreg, $noreg
+    %29:gpr = LDRi12 %stack.0.P0, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0.P0, align 8)
+    %30:gpr = LDRi12 %stack.0.P0, 4, 14 /* CC::al */, $noreg :: (load 4 from %stack.0.P0 + 4)
+    %31:gpr = ADDri killed %28, 8, 14 /* CC::al */, $noreg, $noreg
+    %32:gpr = COPY $sp
+    %34:gpr = MOVi16 72, 14 /* CC::al */, $noreg
+
+  bb.5.if.then:
+    successors: %bb.5(0x40000000), %bb.6(0x40000000)
+
+    %36:gpr = PHI %35, %bb.5, %34, %bb.1
+    %38:gpr = PHI %37, %bb.5, %31, %bb.1
+    %40:gpr = PHI %39, %bb.5, %32, %bb.1
+    %41:dpr, %37:gpr = VLD1d32wb_fixed %38, 0, 14 /* CC::al */, $noreg
+    %39:gpr = VST1d32wb_fixed %40, 0, %41, 14 /* CC::al */, $noreg
+    %35:gpr = SUBri %36, 8, 14 /* CC::al */, $noreg, def $cpsr
+    Bcc %bb.5, 1 /* CC::ne */, $cpsr
+
+  bb.6.if.then:
+    successors: 
+
+    %33:gpr = ADDri %stack.1.jb1, 0, 14 /* CC::al */, $noreg, $noreg
+    $r0 = COPY %33
+    $r2 = COPY %29
+    $r3 = COPY %30
+    BL @_Z3barPx3S37, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $sp
+    ADJCALLSTACKUP 72, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp
+
+  bb.2.if.end:
+    successors: %bb.3(0x00000001), %bb.4(0x7fffffff)
+
+    %12:qpr = VMOVv4i32 0, 14 /* CC::al */, $noreg
+    LIFETIME_END %stack.1.jb1
+    LIFETIME_END %stack.0.P0
+    ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp
+    %13:gpr = COPY $sp
+    %8:gpr = SUBri %13, 128, 14 /* CC::al */, $noreg, $noreg
+    $sp = COPY %8
+    ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp
+    INLINEASM &"", 1, 327689, %8, !14
+    LIFETIME_START %stack.2.V7
+    %9:gpr = ADDri %stack.2.V7, 0, 14 /* CC::al */, $noreg, $noreg
+    INLINEASM &"", 1, 327689, %9, !15
+    LIFETIME_END %stack.2.V7
+    %10:gpr = COPY %11
+    INLINEASM &"", 1, 327689, %10, !16
+    LIFETIME_START %stack.3.P1
+    %14:gpr = ADDri %stack.3.P1, 0, 14 /* CC::al */, $noreg, $noreg
+    %15:gpr = nuw ADDri %14, 40, 14 /* CC::al */, $noreg, $noreg
+    VST1q64 killed %15, 0, %12, 14 /* CC::al */, $noreg :: (store 16 into %ir.10, align 8)
+    %16:gpr = ADDri %14, 52, 14 /* CC::al */, $noreg, $noreg
+    VST1q32 killed %16, 0, %12, 14 /* CC::al */, $noreg :: (store 16 into %ir.10 + 12, align 8)
+    %17:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
+    STRi12 %17, %stack.3.P1, 12, 14 /* CC::al */, $noreg :: (store 4 into %ir.BM0.i + 4, !tbaa !17)
+    STRi12 %17, %stack.3.P1, 8, 14 /* CC::al */, $noreg :: (store 4 into %ir.BM0.i, align 8, !tbaa !17)
+    %18:gpr = MOVi 42, 14 /* CC::al */, $noreg, $noreg
+    STRi12 killed %18, %stack.3.P1, 32, 14 /* CC::al */, $noreg :: (store 4 into %ir.M0.i, align 8, !tbaa !22)
+    LIFETIME_START %stack.4.jb2
+    ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp
+    %19:gpr = ADDri %stack.4.jb2, 0, 14 /* CC::al */, $noreg, $noreg
+    $r0 = COPY %19
+    BL @setjmp, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def $r0
+    ADJCALLSTACKUP 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp
+    %20:gpr = COPY $r0
+    CMPri %20, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+    Bcc %bb.4, 1 /* CC::ne */, $cpsr
+    B %bb.3
+
+  bb.3.if.then7:
+    successors: 
+
+    ADJCALLSTACKDOWN 64, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp
+    %22:gpr = ADDri %stack.3.P1, 0, 14 /* CC::al */, $noreg, $noreg
+    %23:gpr = LDRi12 %stack.3.P1, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.3.P1, align 8)
+    %24:gpr = LDRi12 %stack.3.P1, 4, 14 /* CC::al */, $noreg :: (load 4 from %stack.3.P1 + 4)
+    %25:gpr = ADDri killed %22, 8, 14 /* CC::al */, $noreg, $noreg
+    %26:gpr = COPY $sp
+    %44:dpr, %42:gpr = VLD1d32wb_fixed %25, 0, 14 /* CC::al */, $noreg
+    %43:gpr = VST1d32wb_fixed %26, 0, %44, 14 /* CC::al */, $noreg
+    %47:dpr, %45:gpr = VLD1d32wb_fixed %42, 0, 14 /* CC::al */, $noreg
+    %46:gpr = VST1d32wb_fixed %43, 0, %47, 14 /* CC::al */, $noreg
+    %50:dpr, %48:gpr = VLD1d32wb_fixed %45, 0, 14 /* CC::al */, $noreg
+    %49:gpr = VST1d32wb_fixed %46, 0, %50, 14 /* CC::al */, $noreg
+    %53:dpr, %51:gpr = VLD1d32wb_fixed %48, 0, 14 /* CC::al */, $noreg
+    %52:gpr = VST1d32wb_fixed %49, 0, %53, 14 /* CC::al */, $noreg
+    %56:dpr, %54:gpr = VLD1d32wb_fixed %51, 0, 14 /* CC::al */, $noreg
+    %55:gpr = VST1d32wb_fixed %52, 0, %56, 14 /* CC::al */, $noreg
+    %59:dpr, %57:gpr = VLD1d32wb_fixed %54, 0, 14 /* CC::al */, $noreg
+    %58:gpr = VST1d32wb_fixed %55, 0, %59, 14 /* CC::al */, $noreg
+    %62:dpr, %60:gpr = VLD1d32wb_fixed %57, 0, 14 /* CC::al */, $noreg
+    %61:gpr = VST1d32wb_fixed %58, 0, %62, 14 /* CC::al */, $noreg
+    %65:dpr, %63:gpr = VLD1d32wb_fixed %60, 0, 14 /* CC::al */, $noreg
+    %64:gpr = VST1d32wb_fixed %61, 0, %65, 14 /* CC::al */, $noreg
+    %27:gpr = ADDri %stack.4.jb2, 0, 14 /* CC::al */, $noreg, $noreg
+    $r0 = COPY %27
+    $r2 = COPY %23
+    $r3 = COPY %24
+    BL @_Z3fooPx3S18, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $sp
+    ADJCALLSTACKUP 64, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp
+
+  bb.4.if.end10:
+    LIFETIME_END %stack.4.jb2
+    LIFETIME_END %stack.3.P1
+    %21:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
+    $r0 = COPY %21
+    BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
diff --git a/llvm/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll b/llvm/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll
--- a/llvm/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll
+++ b/llvm/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll
@@ -62,7 +62,7 @@
 ; X64-NOPIC-MCM-NEXT:    movq %rsp, %rax
 ; X64-NOPIC-MCM-NEXT:    movq -{{[0-9]+}}(%rsp), %rcx
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rax
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr0(%rip), %rdx
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rdx
 ; X64-NOPIC-MCM-NEXT:    cmpq %rdx, %rcx
 ; X64-NOPIC-MCM-NEXT:    cmovneq %r14, %rax
 ; X64-NOPIC-MCM-NEXT:    movl (%rbx), %ebp
@@ -73,7 +73,7 @@
 ; X64-NOPIC-MCM-NEXT:    movq %rsp, %rcx
 ; X64-NOPIC-MCM-NEXT:    movq -{{[0-9]+}}(%rsp), %rax
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rcx
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr1(%rip), %rdx
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rdx
 ; X64-NOPIC-MCM-NEXT:    cmpq %rdx, %rax
 ; X64-NOPIC-MCM-NEXT:    cmovneq %r14, %rcx
 ; X64-NOPIC-MCM-NEXT:    addl (%rbx), %ebp
@@ -102,7 +102,7 @@
 ; X64-PIC-NEXT:    movq %rsp, %rax
 ; X64-PIC-NEXT:    movq -{{[0-9]+}}(%rsp), %rcx
 ; X64-PIC-NEXT:    sarq $63, %rax
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr0(%rip), %rdx
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rdx
 ; X64-PIC-NEXT:    cmpq %rdx, %rcx
 ; X64-PIC-NEXT:    cmovneq %r14, %rax
 ; X64-PIC-NEXT:    movl (%rbx), %ebp
@@ -113,7 +113,7 @@
 ; X64-PIC-NEXT:    movq %rsp, %rcx
 ; X64-PIC-NEXT:    movq -{{[0-9]+}}(%rsp), %rax
 ; X64-PIC-NEXT:    sarq $63, %rcx
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr1(%rip), %rdx
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rdx
 ; X64-PIC-NEXT:    cmpq %rdx, %rax
 ; X64-PIC-NEXT:    cmovneq %r14, %rcx
 ; X64-PIC-NEXT:    addl (%rbx), %ebp
@@ -190,23 +190,23 @@
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rax
 ; X64-NOPIC-MCM-NEXT:    shlq $47, %rax
 ; X64-NOPIC-MCM-NEXT:    orq %rax, %rsp
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr2(%rip), %rbp
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rbp
 ; X64-NOPIC-MCM-NEXT:    callq f
 ; X64-NOPIC-MCM-NEXT:  .Lslh_ret_addr2:
 ; X64-NOPIC-MCM-NEXT:    movq %rsp, %rax
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rax
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr2(%rip), %rcx
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rcx
 ; X64-NOPIC-MCM-NEXT:    cmpq %rcx, %rbp
 ; X64-NOPIC-MCM-NEXT:    cmovneq %r14, %rax
 ; X64-NOPIC-MCM-NEXT:    movl (%rbx), %ebp
 ; X64-NOPIC-MCM-NEXT:    shlq $47, %rax
 ; X64-NOPIC-MCM-NEXT:    orq %rax, %rsp
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr3(%rip), %r15
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %r15
 ; X64-NOPIC-MCM-NEXT:    callq f
 ; X64-NOPIC-MCM-NEXT:  .Lslh_ret_addr3:
 ; X64-NOPIC-MCM-NEXT:    movq %rsp, %rcx
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rcx
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr3(%rip), %rax
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rax
 ; X64-NOPIC-MCM-NEXT:    cmpq %rax, %r15
 ; X64-NOPIC-MCM-NEXT:    cmovneq %r14, %rcx
 ; X64-NOPIC-MCM-NEXT:    addl (%rbx), %ebp
@@ -234,23 +234,23 @@
 ; X64-PIC-NEXT:    sarq $63, %rax
 ; X64-PIC-NEXT:    shlq $47, %rax
 ; X64-PIC-NEXT:    orq %rax, %rsp
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr2(%rip), %rbp
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rbp
 ; X64-PIC-NEXT:    callq f@PLT
 ; X64-PIC-NEXT:  .Lslh_ret_addr2:
 ; X64-PIC-NEXT:    movq %rsp, %rax
 ; X64-PIC-NEXT:    sarq $63, %rax
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr2(%rip), %rcx
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rcx
 ; X64-PIC-NEXT:    cmpq %rcx, %rbp
 ; X64-PIC-NEXT:    cmovneq %r14, %rax
 ; X64-PIC-NEXT:    movl (%rbx), %ebp
 ; X64-PIC-NEXT:    shlq $47, %rax
 ; X64-PIC-NEXT:    orq %rax, %rsp
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr3(%rip), %r15
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %r15
 ; X64-PIC-NEXT:    callq f@PLT
 ; X64-PIC-NEXT:  .Lslh_ret_addr3:
 ; X64-PIC-NEXT:    movq %rsp, %rcx
 ; X64-PIC-NEXT:    sarq $63, %rcx
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr3(%rip), %rax
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rax
 ; X64-PIC-NEXT:    cmpq %rax, %r15
 ; X64-PIC-NEXT:    cmovneq %r14, %rcx
 ; X64-PIC-NEXT:    addl (%rbx), %ebp
@@ -283,14 +283,15 @@
 ; X64-NOPIC-NEXT:    pushq %rbp
 ; X64-NOPIC-NEXT:    pushq %r15
 ; X64-NOPIC-NEXT:    pushq %r14
+; X64-NOPIC-NEXT:    pushq %r13
 ; X64-NOPIC-NEXT:    pushq %r12
 ; X64-NOPIC-NEXT:    pushq %rbx
-; X64-NOPIC-NEXT:    subq $16, %rsp
+; X64-NOPIC-NEXT:    subq $24, %rsp
 ; X64-NOPIC-NEXT:    movq %rsp, %rax
 ; X64-NOPIC-NEXT:    movq %rdi, %rbx
 ; X64-NOPIC-NEXT:    movq $-1, %r15
 ; X64-NOPIC-NEXT:    sarq $63, %rax
-; X64-NOPIC-NEXT:    movq %rsp, %r14
+; X64-NOPIC-NEXT:    leaq {{[0-9]+}}(%rsp), %r14
 ; X64-NOPIC-NEXT:    shlq $47, %rax
 ; X64-NOPIC-NEXT:    movq %r14, %rdi
 ; X64-NOPIC-NEXT:    orq %rax, %rsp
@@ -302,38 +303,41 @@
 ; X64-NOPIC-NEXT:    cmpq $.Lslh_ret_addr4, %rbp
 ; X64-NOPIC-NEXT:    cmovneq %r15, %rax
 ; X64-NOPIC-NEXT:    movl (%rbx), %ebp
+; X64-NOPIC-NEXT:    movl $42, %r12d
 ; X64-NOPIC-NEXT:    shlq $47, %rax
 ; X64-NOPIC-NEXT:    movq %r14, %rdi
-; X64-NOPIC-NEXT:    movl $42, %esi
+; X64-NOPIC-NEXT:    movl %r12d, %esi
 ; X64-NOPIC-NEXT:    orq %rax, %rsp
-; X64-NOPIC-NEXT:    movq $.Lslh_ret_addr5, %r12
+; X64-NOPIC-NEXT:    movq $.Lslh_ret_addr5, %r13
 ; X64-NOPIC-NEXT:    callq sigsetjmp
 ; X64-NOPIC-NEXT:  .Lslh_ret_addr5:
 ; X64-NOPIC-NEXT:    movq %rsp, %rax
 ; X64-NOPIC-NEXT:    sarq $63, %rax
-; X64-NOPIC-NEXT:    cmpq $.Lslh_ret_addr5, %r12
+; X64-NOPIC-NEXT:    cmpq $.Lslh_ret_addr5, %r13
 ; X64-NOPIC-NEXT:    cmovneq %r15, %rax
 ; X64-NOPIC-NEXT:    addl (%rbx), %ebp
 ; X64-NOPIC-NEXT:    shlq $47, %rax
 ; X64-NOPIC-NEXT:    movq %r14, %rdi
 ; X64-NOPIC-NEXT:    movq %r14, %rsi
-; X64-NOPIC-NEXT:    movl $42, %edx
+; X64-NOPIC-NEXT:    movl %r12d, %edx
 ; X64-NOPIC-NEXT:    orq %rax, %rsp
 ; X64-NOPIC-NEXT:    movq $.Lslh_ret_addr6, %r14
 ; X64-NOPIC-NEXT:    callq __sigsetjmp
 ; X64-NOPIC-NEXT:  .Lslh_ret_addr6:
-; X64-NOPIC-NEXT:    movq %rsp, %rcx
-; X64-NOPIC-NEXT:    sarq $63, %rcx
+; X64-NOPIC-NEXT:    movq %rsp, %rax
+; X64-NOPIC-NEXT:    sarq $63, %rax
 ; X64-NOPIC-NEXT:    cmpq $.Lslh_ret_addr6, %r14
+; X64-NOPIC-NEXT:    movq %rax, %rcx
 ; X64-NOPIC-NEXT:    cmovneq %r15, %rcx
 ; X64-NOPIC-NEXT:    addl (%rbx), %ebp
-; X64-NOPIC-NEXT:    orl %ecx, %ebp
-; X64-NOPIC-NEXT:    shlq $47, %rcx
 ; X64-NOPIC-NEXT:    movl %ebp, %eax
+; X64-NOPIC-NEXT:    orl %ecx, %eax
+; X64-NOPIC-NEXT:    shlq $47, %rcx
 ; X64-NOPIC-NEXT:    orq %rcx, %rsp
-; X64-NOPIC-NEXT:    addq $16, %rsp
+; X64-NOPIC-NEXT:    addq $24, %rsp
 ; X64-NOPIC-NEXT:    popq %rbx
 ; X64-NOPIC-NEXT:    popq %r12
+; X64-NOPIC-NEXT:    popq %r13
 ; X64-NOPIC-NEXT:    popq %r14
 ; X64-NOPIC-NEXT:    popq %r15
 ; X64-NOPIC-NEXT:    popq %rbp
@@ -344,60 +348,64 @@
 ; X64-NOPIC-MCM-NEXT:    pushq %rbp
 ; X64-NOPIC-MCM-NEXT:    pushq %r15
 ; X64-NOPIC-MCM-NEXT:    pushq %r14
+; X64-NOPIC-MCM-NEXT:    pushq %r13
 ; X64-NOPIC-MCM-NEXT:    pushq %r12
 ; X64-NOPIC-MCM-NEXT:    pushq %rbx
-; X64-NOPIC-MCM-NEXT:    subq $16, %rsp
+; X64-NOPIC-MCM-NEXT:    subq $24, %rsp
 ; X64-NOPIC-MCM-NEXT:    movq %rsp, %rax
 ; X64-NOPIC-MCM-NEXT:    movq %rdi, %rbx
 ; X64-NOPIC-MCM-NEXT:    movq $-1, %r15
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rax
-; X64-NOPIC-MCM-NEXT:    movq %rsp, %r14
+; X64-NOPIC-MCM-NEXT:    leaq {{[0-9]+}}(%rsp), %r14
 ; X64-NOPIC-MCM-NEXT:    shlq $47, %rax
 ; X64-NOPIC-MCM-NEXT:    movq %r14, %rdi
 ; X64-NOPIC-MCM-NEXT:    orq %rax, %rsp
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr4(%rip), %rbp
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rbp
 ; X64-NOPIC-MCM-NEXT:    callq setjmp
 ; X64-NOPIC-MCM-NEXT:  .Lslh_ret_addr4:
 ; X64-NOPIC-MCM-NEXT:    movq %rsp, %rax
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rax
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr4(%rip), %rcx
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rcx
 ; X64-NOPIC-MCM-NEXT:    cmpq %rcx, %rbp
 ; X64-NOPIC-MCM-NEXT:    cmovneq %r15, %rax
 ; X64-NOPIC-MCM-NEXT:    movl (%rbx), %ebp
+; X64-NOPIC-MCM-NEXT:    movl $42, %r12d
 ; X64-NOPIC-MCM-NEXT:    shlq $47, %rax
 ; X64-NOPIC-MCM-NEXT:    movq %r14, %rdi
-; X64-NOPIC-MCM-NEXT:    movl $42, %esi
+; X64-NOPIC-MCM-NEXT:    movl %r12d, %esi
 ; X64-NOPIC-MCM-NEXT:    orq %rax, %rsp
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr5(%rip), %r12
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %r13
 ; X64-NOPIC-MCM-NEXT:    callq sigsetjmp
 ; X64-NOPIC-MCM-NEXT:  .Lslh_ret_addr5:
 ; X64-NOPIC-MCM-NEXT:    movq %rsp, %rax
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rax
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr5(%rip), %rcx
-; X64-NOPIC-MCM-NEXT:    cmpq %rcx, %r12
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rcx
+; X64-NOPIC-MCM-NEXT:    cmpq %rcx, %r13
 ; X64-NOPIC-MCM-NEXT:    cmovneq %r15, %rax
 ; X64-NOPIC-MCM-NEXT:    addl (%rbx), %ebp
 ; X64-NOPIC-MCM-NEXT:    shlq $47, %rax
 ; X64-NOPIC-MCM-NEXT:    movq %r14, %rdi
 ; X64-NOPIC-MCM-NEXT:    movq %r14, %rsi
-; X64-NOPIC-MCM-NEXT:    movl $42, %edx
+; X64-NOPIC-MCM-NEXT:    movl %r12d, %edx
 ; X64-NOPIC-MCM-NEXT:    orq %rax, %rsp
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr6(%rip), %r14
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %r14
 ; X64-NOPIC-MCM-NEXT:    callq __sigsetjmp
 ; X64-NOPIC-MCM-NEXT:  .Lslh_ret_addr6:
-; X64-NOPIC-MCM-NEXT:    movq %rsp, %rcx
-; X64-NOPIC-MCM-NEXT:    sarq $63, %rcx
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr6(%rip), %rax
-; X64-NOPIC-MCM-NEXT:    cmpq %rax, %r14
+; X64-NOPIC-MCM-NEXT:    movq %rsp, %rax
+; X64-NOPIC-MCM-NEXT:    sarq $63, %rax
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rcx
+; X64-NOPIC-MCM-NEXT:    cmpq %rcx, %r14
+; X64-NOPIC-MCM-NEXT:    movq %rax, %rcx
 ; X64-NOPIC-MCM-NEXT:    cmovneq %r15, %rcx
 ; X64-NOPIC-MCM-NEXT:    addl (%rbx), %ebp
-; X64-NOPIC-MCM-NEXT:    orl %ecx, %ebp
-; X64-NOPIC-MCM-NEXT:    shlq $47, %rcx
 ; X64-NOPIC-MCM-NEXT:    movl %ebp, %eax
+; X64-NOPIC-MCM-NEXT:    orl %ecx, %eax
+; X64-NOPIC-MCM-NEXT:    shlq $47, %rcx
 ; X64-NOPIC-MCM-NEXT:    orq %rcx, %rsp
-; X64-NOPIC-MCM-NEXT:    addq $16, %rsp
+; X64-NOPIC-MCM-NEXT:    addq $24, %rsp
 ; X64-NOPIC-MCM-NEXT:    popq %rbx
 ; X64-NOPIC-MCM-NEXT:    popq %r12
+; X64-NOPIC-MCM-NEXT:    popq %r13
 ; X64-NOPIC-MCM-NEXT:    popq %r14
 ; X64-NOPIC-MCM-NEXT:    popq %r15
 ; X64-NOPIC-MCM-NEXT:    popq %rbp
@@ -408,60 +416,64 @@
 ; X64-PIC-NEXT:    pushq %rbp
 ; X64-PIC-NEXT:    pushq %r15
 ; X64-PIC-NEXT:    pushq %r14
+; X64-PIC-NEXT:    pushq %r13
 ; X64-PIC-NEXT:    pushq %r12
 ; X64-PIC-NEXT:    pushq %rbx
-; X64-PIC-NEXT:    subq $16, %rsp
+; X64-PIC-NEXT:    subq $24, %rsp
 ; X64-PIC-NEXT:    movq %rsp, %rax
 ; X64-PIC-NEXT:    movq %rdi, %rbx
 ; X64-PIC-NEXT:    movq $-1, %r15
 ; X64-PIC-NEXT:    sarq $63, %rax
-; X64-PIC-NEXT:    movq %rsp, %r14
+; X64-PIC-NEXT:    leaq {{[0-9]+}}(%rsp), %r14
 ; X64-PIC-NEXT:    shlq $47, %rax
 ; X64-PIC-NEXT:    movq %r14, %rdi
 ; X64-PIC-NEXT:    orq %rax, %rsp
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr4(%rip), %rbp
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rbp
 ; X64-PIC-NEXT:    callq setjmp@PLT
 ; X64-PIC-NEXT:  .Lslh_ret_addr4:
 ; X64-PIC-NEXT:    movq %rsp, %rax
 ; X64-PIC-NEXT:    sarq $63, %rax
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr4(%rip), %rcx
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rcx
 ; X64-PIC-NEXT:    cmpq %rcx, %rbp
 ; X64-PIC-NEXT:    cmovneq %r15, %rax
 ; X64-PIC-NEXT:    movl (%rbx), %ebp
+; X64-PIC-NEXT:    movl $42, %r12d
 ; X64-PIC-NEXT:    shlq $47, %rax
 ; X64-PIC-NEXT:    movq %r14, %rdi
-; X64-PIC-NEXT:    movl $42, %esi
+; X64-PIC-NEXT:    movl %r12d, %esi
 ; X64-PIC-NEXT:    orq %rax, %rsp
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr5(%rip), %r12
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %r13
 ; X64-PIC-NEXT:    callq sigsetjmp@PLT
 ; X64-PIC-NEXT:  .Lslh_ret_addr5:
 ; X64-PIC-NEXT:    movq %rsp, %rax
 ; X64-PIC-NEXT:    sarq $63, %rax
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr5(%rip), %rcx
-; X64-PIC-NEXT:    cmpq %rcx, %r12
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rcx
+; X64-PIC-NEXT:    cmpq %rcx, %r13
 ; X64-PIC-NEXT:    cmovneq %r15, %rax
 ; X64-PIC-NEXT:    addl (%rbx), %ebp
 ; X64-PIC-NEXT:    shlq $47, %rax
 ; X64-PIC-NEXT:    movq %r14, %rdi
 ; X64-PIC-NEXT:    movq %r14, %rsi
-; X64-PIC-NEXT:    movl $42, %edx
+; X64-PIC-NEXT:    movl %r12d, %edx
 ; X64-PIC-NEXT:    orq %rax, %rsp
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr6(%rip), %r14
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %r14
 ; X64-PIC-NEXT:    callq __sigsetjmp@PLT
 ; X64-PIC-NEXT:  .Lslh_ret_addr6:
-; X64-PIC-NEXT:    movq %rsp, %rcx
-; X64-PIC-NEXT:    sarq $63, %rcx
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr6(%rip), %rax
-; X64-PIC-NEXT:    cmpq %rax, %r14
+; X64-PIC-NEXT:    movq %rsp, %rax
+; X64-PIC-NEXT:    sarq $63, %rax
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rcx
+; X64-PIC-NEXT:    cmpq %rcx, %r14
+; X64-PIC-NEXT:    movq %rax, %rcx
 ; X64-PIC-NEXT:    cmovneq %r15, %rcx
 ; X64-PIC-NEXT:    addl (%rbx), %ebp
-; X64-PIC-NEXT:    orl %ecx, %ebp
-; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    movl %ebp, %eax
+; X64-PIC-NEXT:    orl %ecx, %eax
+; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    orq %rcx, %rsp
-; X64-PIC-NEXT:    addq $16, %rsp
+; X64-PIC-NEXT:    addq $24, %rsp
 ; X64-PIC-NEXT:    popq %rbx
 ; X64-PIC-NEXT:    popq %r12
+; X64-PIC-NEXT:    popq %r13
 ; X64-PIC-NEXT:    popq %r14
 ; X64-PIC-NEXT:    popq %r15
 ; X64-PIC-NEXT:    popq %rbp