Index: llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp =================================================================== --- llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp +++ llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp @@ -51,6 +51,7 @@ case Sparc::fixup_sparc_tls_ldm_hi22: case Sparc::fixup_sparc_tls_ie_hi22: case Sparc::fixup_sparc_hi22: + case Sparc::fixup_sparc_lm: return (Value >> 10) & 0x3fffff; case Sparc::fixup_sparc_got13: @@ -131,86 +132,86 @@ const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = { - // name offset bits flags - { "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_sparc_br16_2", 10, 2, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_sparc_br16_14", 18, 14, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_sparc_13", 19, 13, 0 }, - { "fixup_sparc_hi22", 10, 22, 0 }, - { "fixup_sparc_lo10", 22, 10, 0 }, - { "fixup_sparc_h44", 10, 22, 0 }, - { "fixup_sparc_m44", 22, 10, 0 }, - { "fixup_sparc_l44", 20, 12, 0 }, - { "fixup_sparc_hh", 10, 22, 0 }, - { "fixup_sparc_hm", 22, 10, 0 }, - { "fixup_sparc_pc22", 10, 22, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_sparc_pc10", 22, 10, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_sparc_got22", 10, 22, 0 }, - { "fixup_sparc_got10", 22, 10, 0 }, - { "fixup_sparc_got13", 19, 13, 0 }, - { "fixup_sparc_wplt30", 2, 30, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_sparc_tls_gd_hi22", 10, 22, 0 }, - { "fixup_sparc_tls_gd_lo10", 22, 10, 0 }, - { "fixup_sparc_tls_gd_add", 0, 0, 0 }, - { "fixup_sparc_tls_gd_call", 0, 0, 0 }, - { "fixup_sparc_tls_ldm_hi22", 10, 22, 0 }, - { "fixup_sparc_tls_ldm_lo10", 22, 10, 0 }, - { "fixup_sparc_tls_ldm_add", 0, 0, 0 }, - { "fixup_sparc_tls_ldm_call", 0, 0, 0 }, - { "fixup_sparc_tls_ldo_hix22", 10, 22, 0 }, - { "fixup_sparc_tls_ldo_lox10", 22, 10, 0 }, - { "fixup_sparc_tls_ldo_add", 0, 0, 0 }, - { "fixup_sparc_tls_ie_hi22", 10, 22, 0 }, - { "fixup_sparc_tls_ie_lo10", 22, 10, 0 }, - { "fixup_sparc_tls_ie_ld", 0, 0, 0 }, - { "fixup_sparc_tls_ie_ldx", 0, 0, 0 }, - { "fixup_sparc_tls_ie_add", 0, 0, 0 }, - { "fixup_sparc_tls_le_hix22", 0, 0, 0 }, - { "fixup_sparc_tls_le_lox10", 0, 0, 0 } - }; + // name offset bits flags + {"fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_sparc_br16_2", 10, 2, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_sparc_br16_14", 18, 14, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_sparc_13", 19, 13, 0}, + {"fixup_sparc_hi22", 10, 22, 0}, + {"fixup_sparc_lo10", 22, 10, 0}, + {"fixup_sparc_h44", 10, 22, 0}, + {"fixup_sparc_m44", 22, 10, 0}, + {"fixup_sparc_l44", 20, 12, 0}, + {"fixup_sparc_hh", 10, 22, 0}, + {"fixup_sparc_hm", 22, 10, 0}, + {"fixup_sparc_lm", 10, 22, 0}, + {"fixup_sparc_pc22", 10, 22, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_sparc_pc10", 22, 10, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_sparc_got22", 10, 22, 0}, + {"fixup_sparc_got10", 22, 10, 0}, + {"fixup_sparc_got13", 19, 13, 0}, + {"fixup_sparc_wplt30", 2, 30, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_sparc_tls_gd_hi22", 10, 22, 0}, + {"fixup_sparc_tls_gd_lo10", 22, 10, 0}, + {"fixup_sparc_tls_gd_add", 0, 0, 0}, + {"fixup_sparc_tls_gd_call", 0, 0, 0}, + {"fixup_sparc_tls_ldm_hi22", 10, 22, 0}, + {"fixup_sparc_tls_ldm_lo10", 22, 10, 0}, + {"fixup_sparc_tls_ldm_add", 0, 0, 0}, + {"fixup_sparc_tls_ldm_call", 0, 0, 0}, + {"fixup_sparc_tls_ldo_hix22", 10, 22, 0}, + {"fixup_sparc_tls_ldo_lox10", 22, 10, 0}, + {"fixup_sparc_tls_ldo_add", 0, 0, 0}, + {"fixup_sparc_tls_ie_hi22", 10, 22, 0}, + {"fixup_sparc_tls_ie_lo10", 22, 10, 0}, + {"fixup_sparc_tls_ie_ld", 0, 0, 0}, + {"fixup_sparc_tls_ie_ldx", 0, 0, 0}, + {"fixup_sparc_tls_ie_add", 0, 0, 0}, + {"fixup_sparc_tls_le_hix22", 0, 0, 0}, + {"fixup_sparc_tls_le_lox10", 0, 0, 0}}; const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = { - // name offset bits flags - { "fixup_sparc_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_sparc_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_sparc_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_sparc_br16_2", 20, 2, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_sparc_br16_14", 0, 14, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_sparc_13", 0, 13, 0 }, - { "fixup_sparc_hi22", 0, 22, 0 }, - { "fixup_sparc_lo10", 0, 10, 0 }, - { "fixup_sparc_h44", 0, 22, 0 }, - { "fixup_sparc_m44", 0, 10, 0 }, - { "fixup_sparc_l44", 0, 12, 0 }, - { "fixup_sparc_hh", 0, 22, 0 }, - { "fixup_sparc_hm", 0, 10, 0 }, - { "fixup_sparc_pc22", 0, 22, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_sparc_pc10", 0, 10, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_sparc_got22", 0, 22, 0 }, - { "fixup_sparc_got10", 0, 10, 0 }, - { "fixup_sparc_got13", 0, 13, 0 }, - { "fixup_sparc_wplt30", 0, 30, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_sparc_tls_gd_hi22", 0, 22, 0 }, - { "fixup_sparc_tls_gd_lo10", 0, 10, 0 }, - { "fixup_sparc_tls_gd_add", 0, 0, 0 }, - { "fixup_sparc_tls_gd_call", 0, 0, 0 }, - { "fixup_sparc_tls_ldm_hi22", 0, 22, 0 }, - { "fixup_sparc_tls_ldm_lo10", 0, 10, 0 }, - { "fixup_sparc_tls_ldm_add", 0, 0, 0 }, - { "fixup_sparc_tls_ldm_call", 0, 0, 0 }, - { "fixup_sparc_tls_ldo_hix22", 0, 22, 0 }, - { "fixup_sparc_tls_ldo_lox10", 0, 10, 0 }, - { "fixup_sparc_tls_ldo_add", 0, 0, 0 }, - { "fixup_sparc_tls_ie_hi22", 0, 22, 0 }, - { "fixup_sparc_tls_ie_lo10", 0, 10, 0 }, - { "fixup_sparc_tls_ie_ld", 0, 0, 0 }, - { "fixup_sparc_tls_ie_ldx", 0, 0, 0 }, - { "fixup_sparc_tls_ie_add", 0, 0, 0 }, - { "fixup_sparc_tls_le_hix22", 0, 0, 0 }, - { "fixup_sparc_tls_le_lox10", 0, 0, 0 } - }; + // name offset bits flags + {"fixup_sparc_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_sparc_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_sparc_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_sparc_br16_2", 20, 2, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_sparc_br16_14", 0, 14, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_sparc_13", 0, 13, 0}, + {"fixup_sparc_hi22", 0, 22, 0}, + {"fixup_sparc_lo10", 0, 10, 0}, + {"fixup_sparc_h44", 0, 22, 0}, + {"fixup_sparc_m44", 0, 10, 0}, + {"fixup_sparc_l44", 0, 12, 0}, + {"fixup_sparc_hh", 0, 22, 0}, + {"fixup_sparc_hm", 0, 10, 0}, + {"fixup_sparc_lm", 0, 22, 0}, + {"fixup_sparc_pc22", 0, 22, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_sparc_pc10", 0, 10, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_sparc_got22", 0, 22, 0}, + {"fixup_sparc_got10", 0, 10, 0}, + {"fixup_sparc_got13", 0, 13, 0}, + {"fixup_sparc_wplt30", 0, 30, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_sparc_tls_gd_hi22", 0, 22, 0}, + {"fixup_sparc_tls_gd_lo10", 0, 10, 0}, + {"fixup_sparc_tls_gd_add", 0, 0, 0}, + {"fixup_sparc_tls_gd_call", 0, 0, 0}, + {"fixup_sparc_tls_ldm_hi22", 0, 22, 0}, + {"fixup_sparc_tls_ldm_lo10", 0, 10, 0}, + {"fixup_sparc_tls_ldm_add", 0, 0, 0}, + {"fixup_sparc_tls_ldm_call", 0, 0, 0}, + {"fixup_sparc_tls_ldo_hix22", 0, 22, 0}, + {"fixup_sparc_tls_ldo_lox10", 0, 10, 0}, + {"fixup_sparc_tls_ldo_add", 0, 0, 0}, + {"fixup_sparc_tls_ie_hi22", 0, 22, 0}, + {"fixup_sparc_tls_ie_lo10", 0, 10, 0}, + {"fixup_sparc_tls_ie_ld", 0, 0, 0}, + {"fixup_sparc_tls_ie_ldx", 0, 0, 0}, + {"fixup_sparc_tls_ie_add", 0, 0, 0}, + {"fixup_sparc_tls_le_hix22", 0, 0, 0}, + {"fixup_sparc_tls_le_lox10", 0, 0, 0}}; if (Kind < FirstTargetFixupKind) return MCAsmBackend::getFixupKindInfo(Kind); Index: llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp =================================================================== --- llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp +++ llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp @@ -86,6 +86,8 @@ case Sparc::fixup_sparc_l44: return ELF::R_SPARC_L44; case Sparc::fixup_sparc_hh: return ELF::R_SPARC_HH22; case Sparc::fixup_sparc_hm: return ELF::R_SPARC_HM10; + case Sparc::fixup_sparc_lm: + return ELF::R_SPARC_LM22; case Sparc::fixup_sparc_got22: return ELF::R_SPARC_GOT22; case Sparc::fixup_sparc_got10: return ELF::R_SPARC_GOT10; case Sparc::fixup_sparc_got13: return ELF::R_SPARC_GOT13; Index: llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h =================================================================== --- llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h +++ llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h @@ -13,89 +13,92 @@ namespace llvm { namespace Sparc { - enum Fixups { - // fixup_sparc_call30 - 30-bit PC relative relocation for call - fixup_sparc_call30 = FirstTargetFixupKind, - - /// fixup_sparc_br22 - 22-bit PC relative relocation for - /// branches - fixup_sparc_br22, - - /// fixup_sparc_br19 - 19-bit PC relative relocation for - /// branches on icc/xcc - fixup_sparc_br19, - - /// fixup_sparc_bpr - 16-bit fixup for bpr - fixup_sparc_br16_2, - fixup_sparc_br16_14, - - /// fixup_sparc_13 - 13-bit fixup - fixup_sparc_13, - - /// fixup_sparc_hi22 - 22-bit fixup corresponding to %hi(foo) - /// for sethi - fixup_sparc_hi22, - - /// fixup_sparc_lo10 - 10-bit fixup corresponding to %lo(foo) - fixup_sparc_lo10, - - /// fixup_sparc_h44 - 22-bit fixup corresponding to %h44(foo) - fixup_sparc_h44, - - /// fixup_sparc_m44 - 10-bit fixup corresponding to %m44(foo) - fixup_sparc_m44, - - /// fixup_sparc_l44 - 12-bit fixup corresponding to %l44(foo) - fixup_sparc_l44, - - /// fixup_sparc_hh - 22-bit fixup corresponding to %hh(foo) - fixup_sparc_hh, - - /// fixup_sparc_hm - 10-bit fixup corresponding to %hm(foo) - fixup_sparc_hm, - - /// fixup_sparc_pc22 - 22-bit fixup corresponding to %pc22(foo) - fixup_sparc_pc22, - - /// fixup_sparc_pc10 - 10-bit fixup corresponding to %pc10(foo) - fixup_sparc_pc10, - - /// fixup_sparc_got22 - 22-bit fixup corresponding to %got22(foo) - fixup_sparc_got22, - - /// fixup_sparc_got10 - 10-bit fixup corresponding to %got10(foo) - fixup_sparc_got10, - - /// fixup_sparc_got13 - 13-bit fixup corresponding to %got13(foo) - fixup_sparc_got13, - - /// fixup_sparc_wplt30 - fixup_sparc_wplt30, - - /// fixups for Thread Local Storage - fixup_sparc_tls_gd_hi22, - fixup_sparc_tls_gd_lo10, - fixup_sparc_tls_gd_add, - fixup_sparc_tls_gd_call, - fixup_sparc_tls_ldm_hi22, - fixup_sparc_tls_ldm_lo10, - fixup_sparc_tls_ldm_add, - fixup_sparc_tls_ldm_call, - fixup_sparc_tls_ldo_hix22, - fixup_sparc_tls_ldo_lox10, - fixup_sparc_tls_ldo_add, - fixup_sparc_tls_ie_hi22, - fixup_sparc_tls_ie_lo10, - fixup_sparc_tls_ie_ld, - fixup_sparc_tls_ie_ldx, - fixup_sparc_tls_ie_add, - fixup_sparc_tls_le_hix22, - fixup_sparc_tls_le_lox10, - - // Marker - LastTargetFixupKind, - NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind - }; + enum Fixups { + // fixup_sparc_call30 - 30-bit PC relative relocation for call + fixup_sparc_call30 = FirstTargetFixupKind, + + /// fixup_sparc_br22 - 22-bit PC relative relocation for + /// branches + fixup_sparc_br22, + + /// fixup_sparc_br19 - 19-bit PC relative relocation for + /// branches on icc/xcc + fixup_sparc_br19, + + /// fixup_sparc_bpr - 16-bit fixup for bpr + fixup_sparc_br16_2, + fixup_sparc_br16_14, + + /// fixup_sparc_13 - 13-bit fixup + fixup_sparc_13, + + /// fixup_sparc_hi22 - 22-bit fixup corresponding to %hi(foo) + /// for sethi + fixup_sparc_hi22, + + /// fixup_sparc_lo10 - 10-bit fixup corresponding to %lo(foo) + fixup_sparc_lo10, + + /// fixup_sparc_h44 - 22-bit fixup corresponding to %h44(foo) + fixup_sparc_h44, + + /// fixup_sparc_m44 - 10-bit fixup corresponding to %m44(foo) + fixup_sparc_m44, + + /// fixup_sparc_l44 - 12-bit fixup corresponding to %l44(foo) + fixup_sparc_l44, + + /// fixup_sparc_hh - 22-bit fixup corresponding to %hh(foo) + fixup_sparc_hh, + + /// fixup_sparc_hm - 10-bit fixup corresponding to %hm(foo) + fixup_sparc_hm, + + /// fixup_sparc_lm - 22-bit fixup corresponding to %lm(foo) + fixup_sparc_lm, + + /// fixup_sparc_pc22 - 22-bit fixup corresponding to %pc22(foo) + fixup_sparc_pc22, + + /// fixup_sparc_pc10 - 10-bit fixup corresponding to %pc10(foo) + fixup_sparc_pc10, + + /// fixup_sparc_got22 - 22-bit fixup corresponding to %got22(foo) + fixup_sparc_got22, + + /// fixup_sparc_got10 - 10-bit fixup corresponding to %got10(foo) + fixup_sparc_got10, + + /// fixup_sparc_got13 - 13-bit fixup corresponding to %got13(foo) + fixup_sparc_got13, + + /// fixup_sparc_wplt30 + fixup_sparc_wplt30, + + /// fixups for Thread Local Storage + fixup_sparc_tls_gd_hi22, + fixup_sparc_tls_gd_lo10, + fixup_sparc_tls_gd_add, + fixup_sparc_tls_gd_call, + fixup_sparc_tls_ldm_hi22, + fixup_sparc_tls_ldm_lo10, + fixup_sparc_tls_ldm_add, + fixup_sparc_tls_ldm_call, + fixup_sparc_tls_ldo_hix22, + fixup_sparc_tls_ldo_lox10, + fixup_sparc_tls_ldo_add, + fixup_sparc_tls_ie_hi22, + fixup_sparc_tls_ie_lo10, + fixup_sparc_tls_ie_ld, + fixup_sparc_tls_ie_ldx, + fixup_sparc_tls_ie_add, + fixup_sparc_tls_le_hix22, + fixup_sparc_tls_le_lox10, + + // Marker + LastTargetFixupKind, + NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind + }; } } Index: llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h =================================================================== --- llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h +++ llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h @@ -31,6 +31,7 @@ VK_Sparc_L44, VK_Sparc_HH, VK_Sparc_HM, + VK_Sparc_LM, VK_Sparc_PC22, VK_Sparc_PC10, VK_Sparc_GOT22, Index: llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp =================================================================== --- llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp +++ llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp @@ -51,6 +51,9 @@ case VK_Sparc_L44: OS << "%l44("; break; case VK_Sparc_HH: OS << "%hh("; break; case VK_Sparc_HM: OS << "%hm("; break; + case VK_Sparc_LM: + OS << "%lm("; + break; // FIXME: use %pc22/%pc10, if system assembler supports them. case VK_Sparc_PC22: OS << "%hi("; break; case VK_Sparc_PC10: OS << "%lo("; break; @@ -86,38 +89,39 @@ SparcMCExpr::VariantKind SparcMCExpr::parseVariantKind(StringRef name) { return StringSwitch(name) - .Case("lo", VK_Sparc_LO) - .Case("hi", VK_Sparc_HI) - .Case("h44", VK_Sparc_H44) - .Case("m44", VK_Sparc_M44) - .Case("l44", VK_Sparc_L44) - .Case("hh", VK_Sparc_HH) - .Case("hm", VK_Sparc_HM) - .Case("pc22", VK_Sparc_PC22) - .Case("pc10", VK_Sparc_PC10) - .Case("got22", VK_Sparc_GOT22) - .Case("got10", VK_Sparc_GOT10) - .Case("got13", VK_Sparc_GOT13) - .Case("r_disp32", VK_Sparc_R_DISP32) - .Case("tgd_hi22", VK_Sparc_TLS_GD_HI22) - .Case("tgd_lo10", VK_Sparc_TLS_GD_LO10) - .Case("tgd_add", VK_Sparc_TLS_GD_ADD) - .Case("tgd_call", VK_Sparc_TLS_GD_CALL) - .Case("tldm_hi22", VK_Sparc_TLS_LDM_HI22) - .Case("tldm_lo10", VK_Sparc_TLS_LDM_LO10) - .Case("tldm_add", VK_Sparc_TLS_LDM_ADD) - .Case("tldm_call", VK_Sparc_TLS_LDM_CALL) - .Case("tldo_hix22", VK_Sparc_TLS_LDO_HIX22) - .Case("tldo_lox10", VK_Sparc_TLS_LDO_LOX10) - .Case("tldo_add", VK_Sparc_TLS_LDO_ADD) - .Case("tie_hi22", VK_Sparc_TLS_IE_HI22) - .Case("tie_lo10", VK_Sparc_TLS_IE_LO10) - .Case("tie_ld", VK_Sparc_TLS_IE_LD) - .Case("tie_ldx", VK_Sparc_TLS_IE_LDX) - .Case("tie_add", VK_Sparc_TLS_IE_ADD) - .Case("tle_hix22", VK_Sparc_TLS_LE_HIX22) - .Case("tle_lox10", VK_Sparc_TLS_LE_LOX10) - .Default(VK_Sparc_None); + .Case("lo", VK_Sparc_LO) + .Case("hi", VK_Sparc_HI) + .Case("h44", VK_Sparc_H44) + .Case("m44", VK_Sparc_M44) + .Case("l44", VK_Sparc_L44) + .Case("hh", VK_Sparc_HH) + .Case("hm", VK_Sparc_HM) + .Case("lm", VK_Sparc_LM) + .Case("pc22", VK_Sparc_PC22) + .Case("pc10", VK_Sparc_PC10) + .Case("got22", VK_Sparc_GOT22) + .Case("got10", VK_Sparc_GOT10) + .Case("got13", VK_Sparc_GOT13) + .Case("r_disp32", VK_Sparc_R_DISP32) + .Case("tgd_hi22", VK_Sparc_TLS_GD_HI22) + .Case("tgd_lo10", VK_Sparc_TLS_GD_LO10) + .Case("tgd_add", VK_Sparc_TLS_GD_ADD) + .Case("tgd_call", VK_Sparc_TLS_GD_CALL) + .Case("tldm_hi22", VK_Sparc_TLS_LDM_HI22) + .Case("tldm_lo10", VK_Sparc_TLS_LDM_LO10) + .Case("tldm_add", VK_Sparc_TLS_LDM_ADD) + .Case("tldm_call", VK_Sparc_TLS_LDM_CALL) + .Case("tldo_hix22", VK_Sparc_TLS_LDO_HIX22) + .Case("tldo_lox10", VK_Sparc_TLS_LDO_LOX10) + .Case("tldo_add", VK_Sparc_TLS_LDO_ADD) + .Case("tie_hi22", VK_Sparc_TLS_IE_HI22) + .Case("tie_lo10", VK_Sparc_TLS_IE_LO10) + .Case("tie_ld", VK_Sparc_TLS_IE_LD) + .Case("tie_ldx", VK_Sparc_TLS_IE_LDX) + .Case("tie_add", VK_Sparc_TLS_IE_ADD) + .Case("tle_hix22", VK_Sparc_TLS_LE_HIX22) + .Case("tle_lox10", VK_Sparc_TLS_LE_LOX10) + .Default(VK_Sparc_None); } Sparc::Fixups SparcMCExpr::getFixupKind(SparcMCExpr::VariantKind Kind) { @@ -130,6 +134,8 @@ case VK_Sparc_L44: return Sparc::fixup_sparc_l44; case VK_Sparc_HH: return Sparc::fixup_sparc_hh; case VK_Sparc_HM: return Sparc::fixup_sparc_hm; + case VK_Sparc_LM: + return Sparc::fixup_sparc_lm; case VK_Sparc_PC22: return Sparc::fixup_sparc_pc22; case VK_Sparc_PC10: return Sparc::fixup_sparc_pc10; case VK_Sparc_GOT22: return Sparc::fixup_sparc_got22; Index: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp =================================================================== --- llvm/lib/Target/Sparc/SparcAsmPrinter.cpp +++ llvm/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -210,9 +210,8 @@ EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI); // Use register %o7 to load the lower 32 bits. MCOperand RegO7 = MCOperand::createReg(SP::O7); - EmitHiLo(*OutStreamer, GOTLabel, - SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO, - RegO7, OutContext, STI); + EmitHiLo(*OutStreamer, GOTLabel, SparcMCExpr::VK_Sparc_LM, + SparcMCExpr::VK_Sparc_LO, RegO7, OutContext, STI); EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI); } } @@ -300,15 +299,15 @@ assert(TF == SparcMCExpr::VK_Sparc_None && "Cannot handle target flags on call address"); else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi) - assert((TF == SparcMCExpr::VK_Sparc_HI - || TF == SparcMCExpr::VK_Sparc_H44 - || TF == SparcMCExpr::VK_Sparc_HH - || TF == SparcMCExpr::VK_Sparc_TLS_GD_HI22 - || TF == SparcMCExpr::VK_Sparc_TLS_LDM_HI22 - || TF == SparcMCExpr::VK_Sparc_TLS_LDO_HIX22 - || TF == SparcMCExpr::VK_Sparc_TLS_IE_HI22 - || TF == SparcMCExpr::VK_Sparc_TLS_LE_HIX22) && - "Invalid target flags for address operand on sethi"); + assert( + (TF == SparcMCExpr::VK_Sparc_HI || TF == SparcMCExpr::VK_Sparc_H44 || + TF == SparcMCExpr::VK_Sparc_HH || TF == SparcMCExpr::VK_Sparc_LM || + TF == SparcMCExpr::VK_Sparc_TLS_GD_HI22 || + TF == SparcMCExpr::VK_Sparc_TLS_LDM_HI22 || + TF == SparcMCExpr::VK_Sparc_TLS_LDO_HIX22 || + TF == SparcMCExpr::VK_Sparc_TLS_IE_HI22 || + TF == SparcMCExpr::VK_Sparc_TLS_LE_HIX22) && + "Invalid target flags for address operand on sethi"); else if (MI->getOpcode() == SP::TLS_CALL) assert((TF == SparcMCExpr::VK_Sparc_None || TF == SparcMCExpr::VK_Sparc_TLS_GD_CALL Index: llvm/test/MC/Sparc/sparc-relocations.s =================================================================== --- llvm/test/MC/Sparc/sparc-relocations.s +++ llvm/test/MC/Sparc/sparc-relocations.s @@ -11,6 +11,7 @@ ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_L44 sym ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_HH22 sym ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_HM10 sym + ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_LM22 sym ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_13 sym ! CHECK-ELF: ] @@ -46,6 +47,10 @@ ! CHECK-NEXT: ! fixup A - offset: 0, value: %hm(sym), kind: fixup_sparc_hm or %g1, %hm(sym), %g3 + ! CHECK: sethi %lm(sym), %l0 ! encoding: [0x21,0b00AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: %lm(sym), kind: fixup_sparc_lm + sethi %lm(sym), %l0 + ! CHECK: or %g1, sym, %g3 ! encoding: [0x86,0x10,0b011AAAAA,A] ! CHECK-NEXT: ! fixup A - offset: 0, value: sym, kind: fixup_sparc_13 or %g1, sym, %g3