Index: llvm/lib/Target/ARM/ARMInstrMVE.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrMVE.td
+++ llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -4671,6 +4671,24 @@
             (v16i8 (MVE_VQMOVNu16bh (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm)))>;
   def : Pat<(v16i8 (MVEvqmovnu (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), (i32 1))),
             (v16i8 (MVE_VQMOVNu16th (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm)))>;
+
+  def : Pat<(v8i16 (MVEvqmovns (v8i16 MQPR:$Qd_src), (v4i32 (ARMvshrsImm (v4i32 MQPR:$Qm), imm0_31:$imm)), (i32 0))),
+            (v8i16 (MVE_VQSHRNbhs32 (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), imm0_31:$imm))>;
+  def : Pat<(v16i8 (MVEvqmovns (v16i8 MQPR:$Qd_src), (v8i16 (ARMvshrsImm (v8i16 MQPR:$Qm), imm0_15:$imm)), (i32 0))),
+            (v16i8 (MVE_VQSHRNbhs16 (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), imm0_15:$imm))>;
+  def : Pat<(v8i16 (MVEvqmovns (v8i16 MQPR:$Qd_src), (v4i32 (ARMvshrsImm (v4i32 MQPR:$Qm), imm0_31:$imm)), (i32 1))),
+            (v8i16 (MVE_VQSHRNths32 (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), imm0_31:$imm))>;
+  def : Pat<(v16i8 (MVEvqmovns (v16i8 MQPR:$Qd_src), (v8i16 (ARMvshrsImm (v8i16 MQPR:$Qm), imm0_15:$imm)), (i32 1))),
+            (v16i8 (MVE_VQSHRNths16 (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), imm0_15:$imm))>;
+
+  def : Pat<(v8i16 (MVEvqmovnu (v8i16 MQPR:$Qd_src), (v4i32 (ARMvshruImm (v4i32 MQPR:$Qm), imm0_31:$imm)), (i32 0))),
+            (v8i16 (MVE_VQSHRNbhu32 (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), imm0_31:$imm))>;
+  def : Pat<(v16i8 (MVEvqmovnu (v16i8 MQPR:$Qd_src), (v8i16 (ARMvshruImm (v8i16 MQPR:$Qm), imm0_15:$imm)), (i32 0))),
+            (v16i8 (MVE_VQSHRNbhu16 (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), imm0_15:$imm))>;
+  def : Pat<(v8i16 (MVEvqmovnu (v8i16 MQPR:$Qd_src), (v4i32 (ARMvshruImm (v4i32 MQPR:$Qm), imm0_31:$imm)), (i32 1))),
+            (v8i16 (MVE_VQSHRNthu32 (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), imm0_31:$imm))>;
+  def : Pat<(v16i8 (MVEvqmovnu (v16i8 MQPR:$Qd_src), (v8i16 (ARMvshruImm (v8i16 MQPR:$Qm), imm0_15:$imm)), (i32 1))),
+            (v16i8 (MVE_VQSHRNthu16 (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), imm0_15:$imm))>;
 }
 
 class MVE_VCVT_ff<string iname, string suffix, bit op, bit T,
Index: llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
+++ llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
@@ -1135,8 +1135,7 @@
 ; CHECK-NEXT:    vldrh.s32 q0, [r0], #8
 ; CHECK-NEXT:    vldrh.s32 q1, [r1], #8
 ; CHECK-NEXT:    vmul.i32 q0, q1, q0
-; CHECK-NEXT:    vshr.s32 q0, q0, #15
-; CHECK-NEXT:    vqmovnb.s32 q0, q0
+; CHECK-NEXT:    vqshrnb.s32 q0, q0, #15
 ; CHECK-NEXT:    vstrh.32 q0, [r2], #8
 ; CHECK-NEXT:    le lr, .LBB5_4
 ; CHECK-NEXT:  @ %bb.5: @ %middle.block
@@ -1274,15 +1273,13 @@
 ; CHECK-NEXT:    vldrh.s32 q1, [r1, #8]
 ; CHECK-NEXT:    vmul.i32 q0, q1, q0
 ; CHECK-NEXT:    vldrh.s32 q1, [r1]
-; CHECK-NEXT:    vshr.s32 q0, q0, #15
+; CHECK-NEXT:    vqshrnb.s32 q0, q0, #15
 ; CHECK-NEXT:    adds r1, #16
-; CHECK-NEXT:    vqmovnb.s32 q0, q0
 ; CHECK-NEXT:    vstrh.32 q0, [r2, #8]
 ; CHECK-NEXT:    vldrh.s32 q0, [r0]
 ; CHECK-NEXT:    adds r0, #16
 ; CHECK-NEXT:    vmul.i32 q0, q1, q0
-; CHECK-NEXT:    vshr.s32 q0, q0, #15
-; CHECK-NEXT:    vqmovnb.s32 q0, q0
+; CHECK-NEXT:    vqshrnb.s32 q0, q0, #15
 ; CHECK-NEXT:    vstrh.32 q0, [r2]
 ; CHECK-NEXT:    adds r2, #16
 ; CHECK-NEXT:    le lr, .LBB6_4
@@ -1421,10 +1418,8 @@
 ; CHECK-NEXT:    vldrh.u16 q1, [r1], #16
 ; CHECK-NEXT:    vmullt.s16 q2, q1, q0
 ; CHECK-NEXT:    vmullb.s16 q0, q1, q0
-; CHECK-NEXT:    vshr.s32 q2, q2, #15
-; CHECK-NEXT:    vshr.s32 q0, q0, #15
-; CHECK-NEXT:    vqmovnb.s32 q2, q2
-; CHECK-NEXT:    vqmovnb.s32 q0, q0
+; CHECK-NEXT:    vqshrnb.s32 q2, q2, #15
+; CHECK-NEXT:    vqshrnb.s32 q0, q0, #15
 ; CHECK-NEXT:    vmovlb.s16 q2, q2
 ; CHECK-NEXT:    vmovlb.s16 q0, q0
 ; CHECK-NEXT:    vmovnt.i32 q0, q2
@@ -1575,8 +1570,7 @@
 ; CHECK-NEXT:    vldrht.s32 q2, [r0], #8
 ; CHECK-NEXT:    vldrht.s32 q3, [r1], #8
 ; CHECK-NEXT:    vmul.i32 q2, q3, q2
-; CHECK-NEXT:    vshr.s32 q2, q2, #15
-; CHECK-NEXT:    vqmovnb.s32 q2, q2
+; CHECK-NEXT:    vqshrnb.s32 q2, q2, #15
 ; CHECK-NEXT:    vmovlb.s16 q2, q2
 ; CHECK-NEXT:    vpst
 ; CHECK-NEXT:    vstrht.32 q2, [r2], #8
@@ -1710,8 +1704,7 @@
 ; CHECK-NEXT:    vmov.u16 r4, q7[3]
 ; CHECK-NEXT:    vmov.32 q0[3], r4
 ; CHECK-NEXT:    vmullb.s16 q0, q0, q5
-; CHECK-NEXT:    vshr.s32 q0, q0, #15
-; CHECK-NEXT:    vqmovnb.s32 q0, q0
+; CHECK-NEXT:    vqshrnb.s32 q0, q0, #15
 ; CHECK-NEXT:    vmovlb.s16 q0, q0
 ; CHECK-NEXT:    vmov r4, s0
 ; CHECK-NEXT:    vmov.16 q5[0], r4
@@ -1738,8 +1731,7 @@
 ; CHECK-NEXT:    vmov.u16 r4, q7[7]
 ; CHECK-NEXT:    vmov.32 q6[3], r4
 ; CHECK-NEXT:    vmullb.s16 q0, q6, q0
-; CHECK-NEXT:    vshr.s32 q0, q0, #15
-; CHECK-NEXT:    vqmovnb.s32 q0, q0
+; CHECK-NEXT:    vqshrnb.s32 q0, q0, #15
 ; CHECK-NEXT:    vmovlb.s16 q0, q0
 ; CHECK-NEXT:    vmov r4, s0
 ; CHECK-NEXT:    vmov.16 q5[4], r4
@@ -1868,10 +1860,8 @@
 ; CHECK-NEXT:    vldrht.u16 q6, [r1], #16
 ; CHECK-NEXT:    vmullt.s16 q7, q6, q5
 ; CHECK-NEXT:    vmullb.s16 q5, q6, q5
-; CHECK-NEXT:    vshr.s32 q7, q7, #15
-; CHECK-NEXT:    vshr.s32 q5, q5, #15
-; CHECK-NEXT:    vqmovnb.s32 q7, q7
-; CHECK-NEXT:    vqmovnb.s32 q5, q5
+; CHECK-NEXT:    vqshrnb.s32 q7, q7, #15
+; CHECK-NEXT:    vqshrnb.s32 q5, q5, #15
 ; CHECK-NEXT:    vmovlb.s16 q7, q7
 ; CHECK-NEXT:    vmovlb.s16 q5, q5
 ; CHECK-NEXT:    vmovnt.i32 q5, q7
@@ -1980,8 +1970,7 @@
 ; CHECK-NEXT:    vldrh.u32 q0, [r0], #8
 ; CHECK-NEXT:    vldrh.u32 q1, [r1], #8
 ; CHECK-NEXT:    vmul.i32 q0, q1, q0
-; CHECK-NEXT:    vshr.u32 q0, q0, #15
-; CHECK-NEXT:    vqmovnb.u32 q0, q0
+; CHECK-NEXT:    vqshrnb.u32 q0, q0, #15
 ; CHECK-NEXT:    vstrh.32 q0, [r2], #8
 ; CHECK-NEXT:    le lr, .LBB11_4
 ; CHECK-NEXT:  @ %bb.5: @ %middle.block
@@ -2111,15 +2100,13 @@
 ; CHECK-NEXT:    vldrh.u32 q1, [r1, #8]
 ; CHECK-NEXT:    vmul.i32 q0, q1, q0
 ; CHECK-NEXT:    vldrh.u32 q1, [r1]
-; CHECK-NEXT:    vshr.u32 q0, q0, #15
+; CHECK-NEXT:    vqshrnb.u32 q0, q0, #15
 ; CHECK-NEXT:    adds r1, #16
-; CHECK-NEXT:    vqmovnb.u32 q0, q0
 ; CHECK-NEXT:    vstrh.32 q0, [r2, #8]
 ; CHECK-NEXT:    vldrh.u32 q0, [r0]
 ; CHECK-NEXT:    adds r0, #16
 ; CHECK-NEXT:    vmul.i32 q0, q1, q0
-; CHECK-NEXT:    vshr.u32 q0, q0, #15
-; CHECK-NEXT:    vqmovnb.u32 q0, q0
+; CHECK-NEXT:    vqshrnb.u32 q0, q0, #15
 ; CHECK-NEXT:    vstrh.32 q0, [r2]
 ; CHECK-NEXT:    adds r2, #16
 ; CHECK-NEXT:    le lr, .LBB12_4
@@ -2391,8 +2378,7 @@
 ; CHECK-NEXT:    vldrb.s16 q0, [r0], #8
 ; CHECK-NEXT:    vldrb.s16 q1, [r1], #8
 ; CHECK-NEXT:    vmul.i16 q0, q1, q0
-; CHECK-NEXT:    vshr.s16 q0, q0, #7
-; CHECK-NEXT:    vqmovnb.s16 q0, q0
+; CHECK-NEXT:    vqshrnb.s16 q0, q0, #7
 ; CHECK-NEXT:    vstrb.16 q0, [r2], #8
 ; CHECK-NEXT:    le lr, .LBB14_4
 ; CHECK-NEXT:  @ %bb.5: @ %middle.block
@@ -2528,15 +2514,13 @@
 ; CHECK-NEXT:    vldrb.s16 q1, [r1, #8]
 ; CHECK-NEXT:    vmul.i16 q0, q1, q0
 ; CHECK-NEXT:    vldrb.s16 q1, [r1]
-; CHECK-NEXT:    vshr.s16 q0, q0, #7
+; CHECK-NEXT:    vqshrnb.s16 q0, q0, #7
 ; CHECK-NEXT:    adds r1, #16
-; CHECK-NEXT:    vqmovnb.s16 q0, q0
 ; CHECK-NEXT:    vstrb.16 q0, [r2, #8]
 ; CHECK-NEXT:    vldrb.s16 q0, [r0]
 ; CHECK-NEXT:    adds r0, #16
 ; CHECK-NEXT:    vmul.i16 q0, q1, q0
-; CHECK-NEXT:    vshr.s16 q0, q0, #7
-; CHECK-NEXT:    vqmovnb.s16 q0, q0
+; CHECK-NEXT:    vqshrnb.s16 q0, q0, #7
 ; CHECK-NEXT:    vstrb.16 q0, [r2]
 ; CHECK-NEXT:    adds r2, #16
 ; CHECK-NEXT:    le lr, .LBB15_4
@@ -2673,10 +2657,8 @@
 ; CHECK-NEXT:    vldrb.u8 q1, [r1], #16
 ; CHECK-NEXT:    vmullt.s8 q2, q1, q0
 ; CHECK-NEXT:    vmullb.s8 q0, q1, q0
-; CHECK-NEXT:    vshr.s16 q2, q2, #7
-; CHECK-NEXT:    vshr.s16 q0, q0, #7
-; CHECK-NEXT:    vqmovnb.s16 q2, q2
-; CHECK-NEXT:    vqmovnb.s16 q0, q0
+; CHECK-NEXT:    vqshrnb.s16 q2, q2, #7
+; CHECK-NEXT:    vqshrnb.s16 q0, q0, #7
 ; CHECK-NEXT:    vmovlb.s8 q2, q2
 ; CHECK-NEXT:    vmovlb.s8 q0, q0
 ; CHECK-NEXT:    vmovnt.i16 q0, q2
@@ -2852,8 +2834,7 @@
 ; CHECK-NEXT:    vldrbt.s16 q5, [r0], #8
 ; CHECK-NEXT:    vldrbt.s16 q6, [r1], #8
 ; CHECK-NEXT:    vmul.i16 q5, q6, q5
-; CHECK-NEXT:    vshr.s16 q5, q5, #7
-; CHECK-NEXT:    vqmovnb.s16 q5, q5
+; CHECK-NEXT:    vqshrnb.s16 q5, q5, #7
 ; CHECK-NEXT:    vmovlb.s8 q5, q5
 ; CHECK-NEXT:    vpst
 ; CHECK-NEXT:    vstrbt.16 q5, [r2], #8
@@ -3075,8 +3056,7 @@
 ; CHECK-NEXT:    vmov.u8 r4, q4[7]
 ; CHECK-NEXT:    vmov.16 q5[7], r4
 ; CHECK-NEXT:    vmullb.s8 q5, q5, q7
-; CHECK-NEXT:    vshr.s16 q5, q5, #7
-; CHECK-NEXT:    vqmovnb.s16 q5, q5
+; CHECK-NEXT:    vqshrnb.s16 q5, q5, #7
 ; CHECK-NEXT:    vmovlb.s8 q5, q5
 ; CHECK-NEXT:    vmov.u16 r4, q5[0]
 ; CHECK-NEXT:    vmov.8 q7[0], r4
@@ -3127,8 +3107,7 @@
 ; CHECK-NEXT:    vmov.u8 r4, q4[15]
 ; CHECK-NEXT:    vmov.16 q0[7], r4
 ; CHECK-NEXT:    vmullb.s8 q0, q0, q5
-; CHECK-NEXT:    vshr.s16 q0, q0, #7
-; CHECK-NEXT:    vqmovnb.s16 q0, q0
+; CHECK-NEXT:    vqshrnb.s16 q0, q0, #7
 ; CHECK-NEXT:    vmovlb.s8 q0, q0
 ; CHECK-NEXT:    vmov.u16 r4, q0[0]
 ; CHECK-NEXT:    vmov.8 q7[8], r4
@@ -3345,10 +3324,8 @@
 ; CHECK-NEXT:    vldrbt.u8 q4, [r1], #16
 ; CHECK-NEXT:    vmullt.s8 q5, q4, q0
 ; CHECK-NEXT:    vmullb.s8 q0, q4, q0
-; CHECK-NEXT:    vshr.s16 q5, q5, #7
-; CHECK-NEXT:    vshr.s16 q0, q0, #7
-; CHECK-NEXT:    vqmovnb.s16 q5, q5
-; CHECK-NEXT:    vqmovnb.s16 q0, q0
+; CHECK-NEXT:    vqshrnb.s16 q5, q5, #7
+; CHECK-NEXT:    vqshrnb.s16 q0, q0, #7
 ; CHECK-NEXT:    vmovlb.s8 q5, q5
 ; CHECK-NEXT:    vmovlb.s8 q0, q0
 ; CHECK-NEXT:    vmovnt.i16 q0, q5
@@ -3468,8 +3445,7 @@
 ; CHECK-NEXT:    vldrb.u16 q0, [r0], #8
 ; CHECK-NEXT:    vldrb.u16 q1, [r1], #8
 ; CHECK-NEXT:    vmul.i16 q0, q1, q0
-; CHECK-NEXT:    vshr.u16 q0, q0, #7
-; CHECK-NEXT:    vqmovnb.u16 q0, q0
+; CHECK-NEXT:    vqshrnb.u16 q0, q0, #7
 ; CHECK-NEXT:    vstrb.16 q0, [r2], #8
 ; CHECK-NEXT:    le lr, .LBB20_4
 ; CHECK-NEXT:  @ %bb.5: @ %middle.block
@@ -3598,16 +3574,14 @@
 ; CHECK-NEXT:    vldrb.u16 q1, [r1, #8]
 ; CHECK-NEXT:    vmul.i16 q0, q1, q0
 ; CHECK-NEXT:    vldrb.u16 q1, [r1]
-; CHECK-NEXT:    vshr.u16 q0, q0, #7
+; CHECK-NEXT:    vqshrnb.u16 q0, q0, #7
 ; CHECK-NEXT:    adds r1, #16
-; CHECK-NEXT:    vqmovnb.u16 q0, q0
 ; CHECK-NEXT:    vmovlb.u8 q0, q0
 ; CHECK-NEXT:    vstrb.16 q0, [r2, #8]
 ; CHECK-NEXT:    vldrb.u16 q0, [r0]
 ; CHECK-NEXT:    adds r0, #16
 ; CHECK-NEXT:    vmul.i16 q0, q1, q0
-; CHECK-NEXT:    vshr.u16 q0, q0, #7
-; CHECK-NEXT:    vqmovnb.u16 q0, q0
+; CHECK-NEXT:    vqshrnb.u16 q0, q0, #7
 ; CHECK-NEXT:    vmovlb.u8 q0, q0
 ; CHECK-NEXT:    vstrb.16 q0, [r2]
 ; CHECK-NEXT:    adds r2, #16
Index: llvm/test/CodeGen/Thumb2/mve-vqshrn.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-vqshrn.ll
+++ llvm/test/CodeGen/Thumb2/mve-vqshrn.ll
@@ -4,8 +4,7 @@
 define arm_aapcs_vfpcc <4 x i32> @vqmovni32_smaxmin(<4 x i32> %so) {
 ; CHECK-LABEL: vqmovni32_smaxmin:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshr.s32 q0, q0, #3
-; CHECK-NEXT:    vqmovnb.s32 q0, q0
+; CHECK-NEXT:    vqshrnb.s32 q0, q0, #3
 ; CHECK-NEXT:    vmovlb.s16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
@@ -20,8 +19,7 @@
 define arm_aapcs_vfpcc <4 x i32> @vqmovni32_sminmax(<4 x i32> %so) {
 ; CHECK-LABEL: vqmovni32_sminmax:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshr.s32 q0, q0, #3
-; CHECK-NEXT:    vqmovnb.s32 q0, q0
+; CHECK-NEXT:    vqshrnb.s32 q0, q0, #3
 ; CHECK-NEXT:    vmovlb.s16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
@@ -36,8 +34,7 @@
 define arm_aapcs_vfpcc <4 x i32> @vqmovni32_umaxmin(<4 x i32> %so) {
 ; CHECK-LABEL: vqmovni32_umaxmin:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshr.u32 q0, q0, #3
-; CHECK-NEXT:    vqmovnb.u32 q0, q0
+; CHECK-NEXT:    vqshrnb.u32 q0, q0, #3
 ; CHECK-NEXT:    vmovlb.u16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
@@ -50,8 +47,7 @@
 define arm_aapcs_vfpcc <4 x i32> @vqmovni32_uminmax(<4 x i32> %so) {
 ; CHECK-LABEL: vqmovni32_uminmax:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshr.u32 q0, q0, #3
-; CHECK-NEXT:    vqmovnb.u32 q0, q0
+; CHECK-NEXT:    vqshrnb.u32 q0, q0, #3
 ; CHECK-NEXT:    vmovlb.u16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
@@ -64,8 +60,7 @@
 define arm_aapcs_vfpcc <8 x i16> @vqmovni16_smaxmin(<8 x i16> %so) {
 ; CHECK-LABEL: vqmovni16_smaxmin:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshr.s16 q0, q0, #3
-; CHECK-NEXT:    vqmovnb.s16 q0, q0
+; CHECK-NEXT:    vqshrnb.s16 q0, q0, #3
 ; CHECK-NEXT:    vmovlb.s8 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
@@ -80,8 +75,7 @@
 define arm_aapcs_vfpcc <8 x i16> @vqmovni16_sminmax(<8 x i16> %so) {
 ; CHECK-LABEL: vqmovni16_sminmax:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshr.s16 q0, q0, #3
-; CHECK-NEXT:    vqmovnb.s16 q0, q0
+; CHECK-NEXT:    vqshrnb.s16 q0, q0, #3
 ; CHECK-NEXT:    vmovlb.s8 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
@@ -96,8 +90,7 @@
 define arm_aapcs_vfpcc <8 x i16> @vqmovni16_umaxmin(<8 x i16> %so) {
 ; CHECK-LABEL: vqmovni16_umaxmin:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshr.u16 q0, q0, #3
-; CHECK-NEXT:    vqmovnb.u16 q0, q0
+; CHECK-NEXT:    vqshrnb.u16 q0, q0, #3
 ; CHECK-NEXT:    vmovlb.u8 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
@@ -110,8 +103,7 @@
 define arm_aapcs_vfpcc <8 x i16> @vqmovni16_uminmax(<8 x i16> %so) {
 ; CHECK-LABEL: vqmovni16_uminmax:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vshr.u16 q0, q0, #3
-; CHECK-NEXT:    vqmovnb.u16 q0, q0
+; CHECK-NEXT:    vqshrnb.u16 q0, q0, #3
 ; CHECK-NEXT:    vmovlb.u8 q0, q0
 ; CHECK-NEXT:    bx lr
 entry: