[RISCV] Implement evaluateBranch

[simoncook]

Summary

This implements the instruction analysis required to print branch
targets as part of llvm-objdump's disassembly.

Note, this only handles those branches which be analyzed in a single instruction, I'm working on a patch which handles multiple-instruction patterns where GNU objdump prints addresses (loads, stores, AUIPC/LUI+JALR pairs) which I will submit separately.

[simoncook]

Resolve issue found by clang-tidy

[apazos]

Thanks, Simon for pushing this patch, it does help when debugging code and removes the dependence on binutils.

In the future patch for other instructionsm are you including lui/addi combo and addi with gp?

[simoncook]

In D77567#1970868, @apazos wrote:

Thanks, Simon for pushing this patch, it does help when debugging code and removes the dependence on binutils.

In the future patch for other instructionsm are you including lui/addi combo and addi with gp?

Yes, my current WIP patch currently handles lui/addi. I need to work out how to feed in the value of GP into MIA, after which gp-relative addresses will work aswell. When that's a bit more polished I'll submit it here as a WIP patch even if its not feature complete

[lenary]

This is a good first step. I'm happy with how well it is tested, and that it solves some common cases of the issue.

Happy for the follow-up supporting multiple instructions to land later, I don't think it should block this patch.

[asb]

Thanks Simon, LGTM. I noted a tiny nit re the test file.

llvm/test/MC/Disassembler/RISCV/branch-targets.txt

2

Even though it's fairly redundant, we tend to err on the side of testing both rv32 and rv64 at the same time. It would be nice to do so here.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp

 #include "RISCVInstPrinter.h"
 #include "RISCVMCAsmInfo.h"
 #include "RISCVTargetStreamer.h"
 #include "TargetInfo/RISCVTargetInfo.h"
 #include "Utils/RISCVBaseInfo.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/CodeGen/Register.h"
 #include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 #define GET_INSTRINFO_MC_DESC

 
 static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S,
                                                       formatted_raw_ostream &OS,
                                                       MCInstPrinter *InstPrint,
                                                       bool isVerboseAsm) {
   return new RISCVTargetAsmStreamer(S, OS);
 }
 
+namespace {
+
+class RISCVMCInstrAnalysis : public MCInstrAnalysis {
+public:
+  explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
+      : MCInstrAnalysis(Info) {}
+
+  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
+                      uint64_t &Target) const override {
+    if (isConditionalBranch(Inst)) {
+      int64_t Imm;
+      if (Size == 2)
+        Imm = Inst.getOperand(1).getImm();
+      else
+        Imm = Inst.getOperand(2).getImm();
+      Target = Addr + Imm;
+      return true;
+    }
+
+    if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) {
+      Target = Addr + Inst.getOperand(0).getImm();
+      return true;
+    }
+
+    if (Inst.getOpcode() == RISCV::JAL) {
+      Target = Addr + Inst.getOperand(1).getImm();
+      return true;
+    }
+
+    return false;
+  }
+};
+
+} // end anonymous namespace
+
+static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) {
+  return new RISCVMCInstrAnalysis(Info);
+}
+
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
   for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
     TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
     TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
     TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
     TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
     TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
     TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
     TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
     TargetRegistry::RegisterObjectTargetStreamer(
         *T, createRISCVObjectTargetStreamer);
+    TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis);
 
     // Register the asm target streamer.
     TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
   }
 }

llvm/test/MC/Disassembler/RISCV/branch-targets.txt

+# RUN: llvm-mc -assemble -triple riscv32 -mattr=+c -filetype=obj %s -o - 2>&1 | \
+# RUN:   llvm-objdump -d --mattr=+c -M no-aliases - | FileCheck %s
+# RUN: llvm-mc -assemble -triple riscv64 -mattr=+c -filetype=obj %s -o - 2>&1 | \
+# RUN:   llvm-objdump -d --mattr=+c -M no-aliases - | FileCheck %s
+
+label1:
+.option norvc
+  j label1
+  j label2
+  bnez a0, label1
+  bnez a0, label2
+.option rvc
+  j label1
+  j label2
+  bnez a0, label1
+  bnez a0, label2
+# CHECK-LABEL: <label1>:
+# CHECK-NEXT: jal zero, 0 <label1>
+# CHECK-NEXT: jal zero, 20 <label2>
+# CHECK-NEXT: bne a0, zero, -8 <label1>
+# CHECK-NEXT: bne a0, zero, 12 <label2>
+# CHECK-NEXT: c.j -16 <label1>
+# CHECK-NEXT: c.j 6 <label2>
+# CHECK-NEXT: c.bnez a0, -20 <label1>
+# CHECK-NEXT: c.bnez a0, 2 <label2>
+
+label2: