diff --git a/lld/test/ELF/ppc32-call-stub-pic.s b/lld/test/ELF/ppc32-call-stub-pic.s
--- a/lld/test/ELF/ppc32-call-stub-pic.s
+++ b/lld/test/ELF/ppc32-call-stub-pic.s
@@ -121,7 +121,7 @@
 
 # CHECK-NEXT: mflr 12
 # CHECK-NEXT: mtlr 0
-# CHECK-NEXT: subf 11, 12, 11
+# CHECK-NEXT: sub 11, 11, 12
 
 ## Operand of lwz in -pie mode: &.got[1] - 0x100a8 = 0x20088+4 - 0x100a8 = 65536*1-28
 # CHECK-NEXT:  addis 12, 12, 1
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -909,6 +909,9 @@
 }  // hasSideEffects = 0
 }  // End FXU Operations.
 
+def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>;
+def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>;
+
 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
 def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
 
@@ -926,6 +929,21 @@
 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>;
 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;
 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;
+def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>;
+def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>;
+
+def : InstAlias<"isellt $rT, $rA, $rB",
+                (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>;
+def : InstAlias<"iselgt $rT, $rA, $rB",
+                (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>;
+def : InstAlias<"iseleq $rT, $rA, $rB",
+                (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>;
+
+def : InstAlias<"nop", (ORI8 X0, X0, 0)>;
+def : InstAlias<"xnop", (XORI8 X0, X0, 0)>;
+
+def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>;
+def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>;
 
 //===----------------------------------------------------------------------===//
 // Load/Store instructions.
diff --git a/llvm/lib/Target/PowerPC/PPCInstrHTM.td b/llvm/lib/Target/PowerPC/PPCInstrHTM.td
--- a/llvm/lib/Target/PowerPC/PPCInstrHTM.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrHTM.td
@@ -169,3 +169,8 @@
                    36, 28)>;
 
 } // [HasHTM]
+
+def : InstAlias<"tend.", (TEND 0)>, Requires<[HasHTM]>;
+def : InstAlias<"tendall.", (TEND 1)>, Requires<[HasHTM]>;
+def : InstAlias<"tsuspend.", (TSR 0)>, Requires<[HasHTM]>;
+def : InstAlias<"tresume.", (TSR 1)>, Requires<[HasHTM]>;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1769,6 +1769,8 @@
                      IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>,
                      PPC970_DGroup_Single;
 
+def : InstAlias<"rfebb", (RFEBB 1)>;
+
 // DCB* instructions.
 def DCBA   : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
                       IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
@@ -2381,6 +2383,9 @@
 }
 }
 
+def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>;
+def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>;
+
 let PPC970_Unit = 1 in {  // FXU Operations.
 let Defs = [CR0] in {
 def ANDI_rec : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
@@ -2469,6 +2474,14 @@
                       [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
 }
 
+def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>;
+def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>;
+
+def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>;
+def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>;
+
+def : InstAlias<"nop", (ORI R0, R0, 0)>;
+
 let PPC970_Unit = 1 in {  // FXU Operations.
 let hasSideEffects = 0 in {
 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
@@ -2836,6 +2849,8 @@
                    "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>;
 } // hasSideEffects = 0
 
+def : InstAlias<"mtcr $rA", (MTCRF 255, gprc:$rA)>;
+
 let Predicates = [HasFPU] in {
 // Custom inserter instruction to perform FADD in round-to-zero mode.
 let Uses = [RM] in {
@@ -2981,6 +2996,11 @@
 }
 }
 
+def : InstAlias<"sub $rA, $rB, $rC", (SUBF gprc:$rA, gprc:$rC, gprc:$rB)>;
+def : InstAlias<"sub. $rA, $rB, $rC", (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB)>;
+def : InstAlias<"subc $rA, $rB, $rC", (SUBFC gprc:$rA, gprc:$rC, gprc:$rB)>;
+def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB)>;
+
 // A-Form instructions.  Most of the instructions executed in the FPU are of
 // this type.
 //
@@ -4678,6 +4698,13 @@
 def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
                              (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
 
+def : InstAlias<"isellt $rT, $rA, $rB",
+                (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT)>;
+def : InstAlias<"iselgt $rT, $rA, $rB",
+                (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT)>;
+def : InstAlias<"iseleq $rT, $rA, $rB",
+                (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ)>;
+
 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
@@ -4726,6 +4753,8 @@
 def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>;
 
 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
+def : InstAlias<"rotldi $rA, $rS, $n",
+                (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0)>;
 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
@@ -4924,6 +4953,8 @@
 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
 
+def : InstAlias<"trap", (TW 31, R0, R0)>;
+
 multiclass TrapExtendedMnemonic<string name, int to> {
   def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
   def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
diff --git a/llvm/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll b/llvm/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
--- a/llvm/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
+++ b/llvm/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
@@ -3,7 +3,7 @@
 ; The first argument of subfc must not be the same as any other register.
 
 ; CHECK: APP
-; CHECK: subfc [[REG:[0-9]+]],
+; CHECK: subc [[REG:[0-9]+]],
 ; CHECK-NOT: [[REG]]
 ; CHECK: NO_APP
 ; PR1357
diff --git a/llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
--- a/llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
+++ b/llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
@@ -7,7 +7,7 @@
 entry:
 ; Note that part of what is being checked here is proper register reuse.
 ; CHECK: mfcr [[T1:[0-9]+]]
-; CHECK-DAG: subf 0, 0, 1
+; CHECK-DAG: sub 0, 1, 0
 ; CHECK-DAG: ori [[T2:[0-9]+]], [[T2]], 34492
 ; CHECK-DAG: stwx [[T1]], 1, [[T2]]
 ; CHECK-DAG: addi 3, 1, 28
diff --git a/llvm/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll b/llvm/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll
--- a/llvm/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll
+++ b/llvm/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll
@@ -32,7 +32,7 @@
   %conv1 = zext i1 %cmp to i32
   ret i32 %conv1
 ; CHECK-LABEL: test
-; CHECK: subf r3,
+; CHECK: sub r3,
 ; CHECK: extsw r3,
 ; CHECK: bl call
 ; CHECK: sub r3,
diff --git a/llvm/test/CodeGen/PowerPC/atomics-regression.ll b/llvm/test/CodeGen/PowerPC/atomics-regression.ll
--- a/llvm/test/CodeGen/PowerPC/atomics-regression.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics-regression.ll
@@ -2734,7 +2734,7 @@
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB160_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB160_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2750,7 +2750,7 @@
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB161_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB161_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2766,7 +2766,7 @@
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB162_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB162_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2782,7 +2782,7 @@
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB163_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB163_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2799,7 +2799,7 @@
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB164_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB164_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2815,7 +2815,7 @@
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB165_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB165_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2831,7 +2831,7 @@
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB166_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB166_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2847,7 +2847,7 @@
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB167_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB167_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2863,7 +2863,7 @@
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB168_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB168_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2880,7 +2880,7 @@
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB169_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB169_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2896,7 +2896,7 @@
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB170_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB170_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2912,7 +2912,7 @@
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB171_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB171_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2928,7 +2928,7 @@
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB172_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB172_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2944,7 +2944,7 @@
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB173_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB173_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2961,7 +2961,7 @@
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB174_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB174_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6458,7 +6458,7 @@
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB380_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB380_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6474,7 +6474,7 @@
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB381_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB381_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6490,7 +6490,7 @@
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB382_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB382_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6506,7 +6506,7 @@
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB383_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB383_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6523,7 +6523,7 @@
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB384_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB384_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6539,7 +6539,7 @@
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB385_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB385_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6555,7 +6555,7 @@
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB386_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB386_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6571,7 +6571,7 @@
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB387_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB387_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6587,7 +6587,7 @@
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB388_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB388_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6604,7 +6604,7 @@
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB389_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB389_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6620,7 +6620,7 @@
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB390_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB390_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6636,7 +6636,7 @@
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB391_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB391_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6652,7 +6652,7 @@
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB392_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB392_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6668,7 +6668,7 @@
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB393_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB393_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6685,7 +6685,7 @@
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB394_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB394_1
 ; PPC64LE-NEXT:  # %bb.2:
diff --git a/llvm/test/CodeGen/PowerPC/crbits.ll b/llvm/test/CodeGen/PowerPC/crbits.ll
--- a/llvm/test/CodeGen/PowerPC/crbits.ll
+++ b/llvm/test/CodeGen/PowerPC/crbits.ll
@@ -24,7 +24,7 @@
 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: li 3, 0
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
@@ -134,7 +134,7 @@
 
 ; CHECK-LABEL: @test7
 ; CHECK: andi. {{[0-9]+}}, 3, 1
-; CHECK: isel 3, 4, 5, 1
+; CHECK: iselgt 3, 4, 5
 ; CHECK: blr
 }
 
diff --git a/llvm/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll b/llvm/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
--- a/llvm/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
+++ b/llvm/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
@@ -5,7 +5,7 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \
 ; RUN:   grep orc | count 2
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | \
-; RUN:   grep nor | count 3
+; RUN:   grep nor | count 2
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \
 ; RUN:   grep nand | count 1
 
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-binary.ll b/llvm/test/CodeGen/PowerPC/fast-isel-binary.ll
--- a/llvm/test/CodeGen/PowerPC/fast-isel-binary.ll
+++ b/llvm/test/CodeGen/PowerPC/fast-isel-binary.ll
@@ -91,7 +91,7 @@
 ; ELF64: sub_i8
   %a.addr = alloca i8, align 4
   %0 = sub i8 %a, %b
-; ELF64: subf
+; ELF64: sub
   store i8 %0, i8* %a.addr, align 4
   ret void
 }
@@ -111,7 +111,7 @@
 ; ELF64: sub_i16
   %a.addr = alloca i16, align 4
   %0 = sub i16 %a, %b
-; ELF64: subf
+; ELF64: sub
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
@@ -131,7 +131,7 @@
 ; ELF64: sub_i16_imm
   %a.addr = alloca i16, align 4
   %0 = sub i16 %a, -32768;
-; ELF64: subf
+; ELF64: sub
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
diff --git a/llvm/test/CodeGen/PowerPC/fold-zero.ll b/llvm/test/CodeGen/PowerPC/fold-zero.ll
--- a/llvm/test/CodeGen/PowerPC/fold-zero.ll
+++ b/llvm/test/CodeGen/PowerPC/fold-zero.ll
@@ -27,14 +27,14 @@
 
 ; CHECK-CRB-LABEL: @test2
 ; CHECK-CRB-NOT: li {{[0-9]+}}, 0
-; CHECK-CRB: isel 3, 0,
+; CHECK-CRB: iselgt 3, 0,
 ; CHECK-CRB: blr
 ; CHECK-NO-ISEL-LABEL: @test2
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: ori 3, 4, 0
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: li 3, 0
 ; CHECK-NO-ISEL-NEXT: blr
 }
 
diff --git a/llvm/test/CodeGen/PowerPC/i1-ext-fold.ll b/llvm/test/CodeGen/PowerPC/i1-ext-fold.ll
--- a/llvm/test/CodeGen/PowerPC/i1-ext-fold.ll
+++ b/llvm/test/CodeGen/PowerPC/i1-ext-fold.ll
@@ -65,7 +65,7 @@
 ; CHECK-NO-ISEL: ori 3, 5, 0
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: li 3, 0
 ; CHECK-NO-ISEL-NEXT: blr
 }
 
diff --git a/llvm/test/CodeGen/PowerPC/ifcvt.ll b/llvm/test/CodeGen/PowerPC/ifcvt.ll
--- a/llvm/test/CodeGen/PowerPC/ifcvt.ll
+++ b/llvm/test/CodeGen/PowerPC/ifcvt.ll
@@ -22,7 +22,7 @@
 ; CHECK-LABEL: @test
 ; CHECK-NO-ISEL-LABEL: @test
 ; CHECK: add [[REG:[0-9]+]], 
-; CHECK: subf [[REG2:[0-9]+]],
+; CHECK: sub [[REG2:[0-9]+]],
 ; CHECK: isel {{[0-9]+}}, [[REG]], [[REG2]],
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
diff --git a/llvm/test/CodeGen/PowerPC/inc-of-add.ll b/llvm/test/CodeGen/PowerPC/inc-of-add.ll
--- a/llvm/test/CodeGen/PowerPC/inc-of-add.ll
+++ b/llvm/test/CodeGen/PowerPC/inc-of-add.ll
@@ -406,12 +406,12 @@
 define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
 ; PPC32-LABEL: vector_i128_i64:
 ; PPC32:       # %bb.0:
-; PPC32-NEXT:    nor 4, 4, 4
-; PPC32-NEXT:    nor 3, 3, 3
+; PPC32-NEXT:    not 4, 4
+; PPC32-NEXT:    not 3, 3
 ; PPC32-NEXT:    subfc 4, 4, 8
-; PPC32-NEXT:    nor 6, 6, 6
+; PPC32-NEXT:    not 6, 6
 ; PPC32-NEXT:    subfe 3, 3, 7
-; PPC32-NEXT:    nor 5, 5, 5
+; PPC32-NEXT:    not 5, 5
 ; PPC32-NEXT:    subfc 6, 6, 10
 ; PPC32-NEXT:    subfe 5, 5, 9
 ; PPC32-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/memcmp.ll b/llvm/test/CodeGen/PowerPC/memcmp.ll
--- a/llvm/test/CodeGen/PowerPC/memcmp.ll
+++ b/llvm/test/CodeGen/PowerPC/memcmp.ll
@@ -44,7 +44,7 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lhbrx 3, 0, 3
 ; CHECK-NEXT:    lhbrx 4, 0, 4
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
   %t0 = bitcast i32* %buffer1 to i8*
@@ -58,7 +58,7 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lbz 3, 0(3)
 ; CHECK-NEXT:    lbz 4, 0(4)
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
   %t0 = bitcast i32* %buffer1 to i8*
diff --git a/llvm/test/CodeGen/PowerPC/popcnt-zext.ll b/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
--- a/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
+++ b/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
@@ -15,7 +15,7 @@
 ; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
@@ -51,7 +51,7 @@
 ; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
@@ -87,7 +87,7 @@
 ; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
@@ -123,7 +123,7 @@
 ; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
@@ -159,7 +159,7 @@
 ; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
@@ -195,7 +195,7 @@
 ; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
@@ -308,7 +308,7 @@
 ; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
diff --git a/llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll b/llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll
--- a/llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll
@@ -22,7 +22,7 @@
 ; CHECK-NO-ISEL: ori 4, 5, 0
 ; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 4, 0, 0
+; CHECK-NO-ISEL-NEXT: li 4, 0
 ; CHECK: and 3, [[REG4]], [[REG3]]
 ; CHECK: blr
 }
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll b/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
--- a/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
@@ -395,13 +395,13 @@
   ret <16 x i8> %vecins123
 ; CHECK-LABEL: sub_absv_8_ext
 ; CHECK-NOT: vabsdub
-; CHECK: subf
+; CHECK: sub
 ; CHECK-NOT: vabsdub
 ; CHECK: xor
 ; CHECK-NOT: vabsdub
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: sub_absv_8_ext
-; CHECK-PWR8: subf
+; CHECK-PWR8: sub
 ; CHECK-PWR8: xor
 ; CHECK-PWR8: blr
 }
diff --git a/llvm/test/CodeGen/PowerPC/pr44183.ll b/llvm/test/CodeGen/PowerPC/pr44183.ll
--- a/llvm/test/CodeGen/PowerPC/pr44183.ll
+++ b/llvm/test/CodeGen/PowerPC/pr44183.ll
@@ -16,7 +16,7 @@
 ; CHECK-NEXT:    lwz r5, 36(r30)
 ; CHECK-NEXT:    rldicl r4, r4, 60, 4
 ; CHECK-NEXT:    rlwinm r3, r4, 31, 0, 0
-; CHECK-NEXT:    rlwinm r4, r5, 0, 31, 31
+; CHECK-NEXT:    clrlwi r4, r5, 31
 ; CHECK-NEXT:    or r4, r4, r3
 ; CHECK-NEXT:    bl _ZN1llsE1d
 ; CHECK-NEXT:    nop
diff --git a/llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.ll b/llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.ll
--- a/llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.ll
+++ b/llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.ll
@@ -18,7 +18,7 @@
 ; PPC64LE-NEXT:    stdu 1, -32(1)
 ; PPC64LE-NEXT:    li 3, 1
 ; PPC64LE-NEXT:    li 4, 0
-; PPC64LE-NEXT:    isel 3, 3, 4, 1
+; PPC64LE-NEXT:    iselgt 3, 3, 4
 ; PPC64LE-NEXT:    bl barney.88
 ; PPC64LE-NEXT:    nop
 ; PPC64LE-NEXT:    addi 1, 1, 32
diff --git a/llvm/test/CodeGen/PowerPC/sat-add.ll b/llvm/test/CodeGen/PowerPC/sat-add.ll
--- a/llvm/test/CodeGen/PowerPC/sat-add.ll
+++ b/llvm/test/CodeGen/PowerPC/sat-add.ll
@@ -185,7 +185,7 @@
 define i8 @unsigned_sat_variable_i8_using_min(i8 %x, i8 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i8_using_min:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 5, 4, 4
+; CHECK-NEXT:    not 5, 4
 ; CHECK-NEXT:    clrlwi 6, 3, 24
 ; CHECK-NEXT:    clrlwi 7, 5, 24
 ; CHECK-NEXT:    cmplw 6, 7
@@ -218,7 +218,7 @@
 define i8 @unsigned_sat_variable_i8_using_cmp_notval(i8 %x, i8 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_notval:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 6, 4, 4
+; CHECK-NEXT:    not 6, 4
 ; CHECK-NEXT:    clrlwi 7, 3, 24
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    add 3, 3, 4
@@ -236,7 +236,7 @@
 define i16 @unsigned_sat_variable_i16_using_min(i16 %x, i16 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i16_using_min:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 5, 4, 4
+; CHECK-NEXT:    not 5, 4
 ; CHECK-NEXT:    clrlwi 6, 3, 16
 ; CHECK-NEXT:    clrlwi 7, 5, 16
 ; CHECK-NEXT:    cmplw 6, 7
@@ -269,7 +269,7 @@
 define i16 @unsigned_sat_variable_i16_using_cmp_notval(i16 %x, i16 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_notval:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 6, 4, 4
+; CHECK-NEXT:    not 6, 4
 ; CHECK-NEXT:    clrlwi 7, 3, 16
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    add 3, 3, 4
@@ -287,7 +287,7 @@
 define i32 @unsigned_sat_variable_i32_using_min(i32 %x, i32 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i32_using_min:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 5, 4, 4
+; CHECK-NEXT:    not 5, 4
 ; CHECK-NEXT:    cmplw 3, 5
 ; CHECK-NEXT:    isel 3, 3, 5, 0
 ; CHECK-NEXT:    add 3, 3, 4
@@ -316,7 +316,7 @@
 define i32 @unsigned_sat_variable_i32_using_cmp_notval(i32 %x, i32 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i32_using_cmp_notval:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 6, 4, 4
+; CHECK-NEXT:    not 6, 4
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    cmplw 3, 6
 ; CHECK-NEXT:    add 3, 3, 4
diff --git a/llvm/test/CodeGen/PowerPC/select_const.ll b/llvm/test/CodeGen/PowerPC/select_const.ll
--- a/llvm/test/CodeGen/PowerPC/select_const.ll
+++ b/llvm/test/CodeGen/PowerPC/select_const.ll
@@ -194,7 +194,7 @@
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 421
 ; ISEL-NEXT:    li 3, 42
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_C1_C2:
@@ -217,7 +217,7 @@
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 421
 ; ISEL-NEXT:    li 3, 42
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_C1_C2_zeroext:
@@ -240,7 +240,7 @@
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 421
 ; ISEL-NEXT:    li 3, 42
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_C1_C2_signext:
@@ -265,7 +265,7 @@
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 1
 ; ISEL-NEXT:    li 3, 28
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_add_constant:
@@ -289,7 +289,7 @@
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -9
 ; ISEL-NEXT:    li 3, 18
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_sub_constant:
@@ -313,7 +313,7 @@
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 9
 ; ISEL-NEXT:    li 3, 2
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_sub_constant_sel_constants:
@@ -337,7 +337,7 @@
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -20
 ; ISEL-NEXT:    li 3, 115
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_mul_constant:
@@ -360,7 +360,7 @@
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 3, 4
-; ISEL-NEXT:    isel 3, 0, 3, 1
+; ISEL-NEXT:    iselgt 3, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_sdiv_constant:
@@ -370,7 +370,7 @@
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB25_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB25_1:
-; NO_ISEL-NEXT:    addi 3, 0, 0
+; NO_ISEL-NEXT:    li 3, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = sdiv i8 %sel, 5
@@ -382,7 +382,7 @@
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 3, 5
-; ISEL-NEXT:    isel 3, 0, 3, 1
+; ISEL-NEXT:    iselgt 3, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sdiv_constant_sel_constants:
@@ -392,7 +392,7 @@
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB26_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB26_1:
-; NO_ISEL-NEXT:    addi 3, 0, 0
+; NO_ISEL-NEXT:    li 3, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 121, i8 23
   %bo = sdiv i8 120, %sel
@@ -405,7 +405,7 @@
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 50
 ; ISEL-NEXT:    li 3, 4
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_udiv_constant:
@@ -428,7 +428,7 @@
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 3, 5
-; ISEL-NEXT:    isel 3, 0, 3, 1
+; ISEL-NEXT:    iselgt 3, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: udiv_constant_sel_constants:
@@ -438,7 +438,7 @@
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB28_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB28_1:
-; NO_ISEL-NEXT:    addi 3, 0, 0
+; NO_ISEL-NEXT:    li 3, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = udiv i8 120, %sel
@@ -451,7 +451,7 @@
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -4
 ; ISEL-NEXT:    li 3, 3
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_srem_constant:
@@ -475,7 +475,7 @@
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 120
 ; ISEL-NEXT:    li 3, 5
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: srem_constant_sel_constants:
@@ -510,7 +510,7 @@
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 120
 ; ISEL-NEXT:    li 3, 5
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: urem_constant_sel_constants:
@@ -545,7 +545,7 @@
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -3
 ; ISEL-NEXT:    li 3, 23
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_or_constant:
@@ -569,7 +569,7 @@
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -7
 ; ISEL-NEXT:    li 3, 18
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_xor_constant:
@@ -593,7 +593,7 @@
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -128
 ; ISEL-NEXT:    li 3, -32
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_shl_constant:
@@ -630,7 +630,7 @@
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 7
 ; ISEL-NEXT:    li 3, 0
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_lshr_constant:
@@ -694,7 +694,7 @@
 ; ISEL-NEXT:    addis 3, 2, .LCPI42_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI42_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI42_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
@@ -725,7 +725,7 @@
 ; ISEL-NEXT:    addis 3, 2, .LCPI43_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI43_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI43_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
@@ -756,7 +756,7 @@
 ; ISEL-NEXT:    addis 3, 2, .LCPI44_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI44_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI44_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
@@ -787,7 +787,7 @@
 ; ISEL-NEXT:    addis 3, 2, .LCPI45_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI45_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI45_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
@@ -818,7 +818,7 @@
 ; ISEL-NEXT:    addis 3, 2, .LCPI46_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI46_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI46_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
@@ -849,7 +849,7 @@
 ; ISEL-NEXT:    addis 3, 2, .LCPI47_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI47_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI47_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
@@ -898,7 +898,7 @@
 ; ISEL-NEXT:    addis 3, 2, .LCPI49_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI49_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI49_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
diff --git a/llvm/test/CodeGen/PowerPC/setcc-logic.ll b/llvm/test/CodeGen/PowerPC/setcc-logic.ll
--- a/llvm/test/CodeGen/PowerPC/setcc-logic.ll
+++ b/llvm/test/CodeGen/PowerPC/setcc-logic.ll
@@ -499,7 +499,7 @@
 ; CHECK-NEXT:    addi 3, 3, -4625
 ; CHECK-NEXT:    rlwinm 3, 3, 0, 28, 26
 ; CHECK-NEXT:    cntlzw 3, 3
-; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
 ; CHECK-NEXT:    blr
   %a = icmp ne i32 %x, 4625
diff --git a/llvm/test/CodeGen/PowerPC/sms-phi-2.ll b/llvm/test/CodeGen/PowerPC/sms-phi-2.ll
--- a/llvm/test/CodeGen/PowerPC/sms-phi-2.ll
+++ b/llvm/test/CodeGen/PowerPC/sms-phi-2.ll
@@ -25,7 +25,7 @@
 ; CHECK-NEXT:    mr 3, 9
 ; CHECK-NEXT:    mullw 9, 9, 4
 ; CHECK-NEXT:    divw 10, 3, 4
-; CHECK-NEXT:    subf 8, 9, 8
+; CHECK-NEXT:    sub 8, 8, 9
 ; CHECK-NEXT:    cmplwi 8, 10
 ; CHECK-NEXT:    isel 9, 6, 5, 0
 ; CHECK-NEXT:    add 8, 9, 8
diff --git a/llvm/test/CodeGen/PowerPC/spe.ll b/llvm/test/CodeGen/PowerPC/spe.ll
--- a/llvm/test/CodeGen/PowerPC/spe.ll
+++ b/llvm/test/CodeGen/PowerPC/spe.ll
@@ -277,7 +277,7 @@
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB13_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp uno float %a, %b
@@ -296,7 +296,7 @@
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB14_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp ord float %a, %b
@@ -317,7 +317,7 @@
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB15_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp ueq float %a, %b
@@ -338,7 +338,7 @@
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB16_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp one float %a, %b
@@ -423,7 +423,7 @@
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB19_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp ult float %a, %b
@@ -696,7 +696,7 @@
 ; CHECK-NEXT:    ori 3, 7, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB35_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp uno double %a, %b
@@ -717,7 +717,7 @@
 ; CHECK-NEXT:    ori 3, 7, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB36_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp ord double %a, %b
@@ -957,7 +957,7 @@
 ; CHECK-NEXT:    ori 3, 7, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB43_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp one double %a, %b
@@ -1088,7 +1088,7 @@
 ; CHECK-NEXT:    ori 3, 7, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB47_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp oge double %a, %b
diff --git a/llvm/test/CodeGen/PowerPC/srem-lkk.ll b/llvm/test/CodeGen/PowerPC/srem-lkk.ll
--- a/llvm/test/CodeGen/PowerPC/srem-lkk.ll
+++ b/llvm/test/CodeGen/PowerPC/srem-lkk.ll
@@ -13,7 +13,7 @@
 ; CHECK-NEXT:    srawi 4, 4, 6
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 4, 4, 95
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, 95
   ret i32 %1
@@ -30,7 +30,7 @@
 ; CHECK-NEXT:    srawi 4, 4, 8
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 4, 4, 1060
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, 1060
   ret i32 %1
@@ -47,7 +47,7 @@
 ; CHECK-NEXT:    srawi 4, 4, 8
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 4, 4, -723
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, -723
   ret i32 %1
@@ -64,7 +64,7 @@
 ; CHECK-NEXT:    srawi 4, 4, 8
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 4, 4, -22981
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, -22981
   ret i32 %1
@@ -83,7 +83,7 @@
 ; CHECK-NEXT:    srawi 4, 4, 6
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 5, 4, 95
-; CHECK-NEXT:    subf 3, 5, 3
+; CHECK-NEXT:    sub 3, 3, 5
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, 95
@@ -99,7 +99,7 @@
 ; CHECK-NEXT:    srawi 4, 3, 6
 ; CHECK-NEXT:    addze 4, 4
 ; CHECK-NEXT:    slwi 4, 4, 6
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, 64
   ret i32 %1
diff --git a/llvm/test/CodeGen/PowerPC/stack-guard-reassign.ll b/llvm/test/CodeGen/PowerPC/stack-guard-reassign.ll
--- a/llvm/test/CodeGen/PowerPC/stack-guard-reassign.ll
+++ b/llvm/test/CodeGen/PowerPC/stack-guard-reassign.ll
@@ -8,7 +8,7 @@
 ; CHECK-NEXT: lis 0, -2
 ; CHECK-NEXT: ori 0, 0, 65488
 ; CHECK-NEXT: stwux 1, 1, 0
-; CHECK-NEXT: subf 0, 0, 1
+; CHECK-NEXT: sub 0, 1, 0
 ; CHECK-NEXT: lis 4, __stack_chk_guard@ha
 ; CHECK-NEXT: lwz 5, __stack_chk_guard@l(4)
 ; CHECK-NEXT: lis 6, 1
diff --git a/llvm/test/CodeGen/PowerPC/stack-realign.ll b/llvm/test/CodeGen/PowerPC/stack-realign.ll
--- a/llvm/test/CodeGen/PowerPC/stack-realign.ll
+++ b/llvm/test/CodeGen/PowerPC/stack-realign.ll
@@ -82,7 +82,7 @@
 ; CHECK-32-DAG: stw [[LR]], 4(1)
 ; CHECK-32-DAG: subfic 0, [[REG]], -64
 ; CHECK-32: stwux 1, 1, 0
-; CHECK-32: subf 0, 0, 1
+; CHECK-32: sub 0, 1, 0
 ; CHECK-32: addic 0, 0, -4
 ; CHECK-32: stwx 31, 0, 0
 ; CHECK-32: addic 0, 0, -4
@@ -95,7 +95,7 @@
 ; CHECK-32-PIC-DAG: stw [[LR]], 4(1)
 ; CHECK-32-PIC-DAG: subfic 0, [[REG]], -64
 ; CHECK-32-PIC:     stwux 1, 1, 0
-; CHECK-32-PIC:     subf 0, 0, 1
+; CHECK-32-PIC:     sub 0, 1, 0
 ; CHECK-32-PIC:     addic 0, 0, -4
 ; CHECK-32-PIC:     stwx 31, 0, 0
 ; CHECK-32-PIC:     addic 0, 0, -4
@@ -145,7 +145,7 @@
 ; CHECK-32-DAG: stw [[LR]], 4(1)
 ; CHECK-32-DAG: subfc 0, [[REG3]], [[REG2]]
 ; CHECK-32:     stwux 1, 1, 0
-; CHECK-32:     subf 0, 0, 1
+; CHECK-32:     sub 0, 1, 0
 ; CHECK-32:     addic 0, 0, -4
 ; CHECK-32:     stwx 31, 0, 0
 ; CHECK-32:     addic 0, 0, -4
@@ -163,7 +163,7 @@
 ; CHECK-32-PIC-DAG: stw 0, 4(1)
 ; CHECK-32-PIC-DAG: subfc 0, [[REG3]], [[REG2]]
 ; CHECK-32-PIC:     stwux 1, 1, 0
-; CHECK-32-PIC:     subf 0, 0, 1
+; CHECK-32-PIC:     sub 0, 1, 0
 ; CHECK-32-PIC:     addic 0, 0, -4
 ; CHECK-32-PIC:     stwx 31, 0, 0
 ; CHECK-32-PIC:     addic 0, 0, -8
diff --git a/llvm/test/CodeGen/PowerPC/sub-of-not.ll b/llvm/test/CodeGen/PowerPC/sub-of-not.ll
--- a/llvm/test/CodeGen/PowerPC/sub-of-not.ll
+++ b/llvm/test/CodeGen/PowerPC/sub-of-not.ll
@@ -406,12 +406,12 @@
 define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
 ; PPC32-LABEL: vector_i128_i64:
 ; PPC32:       # %bb.0:
-; PPC32-NEXT:    nor 4, 4, 4
-; PPC32-NEXT:    nor 3, 3, 3
+; PPC32-NEXT:    not 4, 4
+; PPC32-NEXT:    not 3, 3
 ; PPC32-NEXT:    subfc 4, 4, 8
-; PPC32-NEXT:    nor 6, 6, 6
+; PPC32-NEXT:    not 6, 6
 ; PPC32-NEXT:    subfe 3, 3, 7
-; PPC32-NEXT:    nor 5, 5, 5
+; PPC32-NEXT:    not 5, 5
 ; PPC32-NEXT:    subfc 6, 6, 10
 ; PPC32-NEXT:    subfe 5, 5, 9
 ; PPC32-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll b/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
--- a/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
+++ b/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
@@ -30,7 +30,7 @@
 ; PPC64-NEXT:    ori 5, 7, 0
 ; PPC64-NEXT:    blr
 ; PPC64-NEXT:  .LBB0_2: # %start
-; PPC64-NEXT:    addi 5, 0, 0
+; PPC64-NEXT:    li 5, 0
 ; PPC64-NEXT:    blr
 ;
 ; PPC32-LABEL: muloti_test:
@@ -131,7 +131,7 @@
 ; PPC32-NEXT:    ori 7, 3, 0
 ; PPC32-NEXT:    b .LBB0_3
 ; PPC32-NEXT:  .LBB0_2: # %start
-; PPC32-NEXT:    addi 7, 0, 0
+; PPC32-NEXT:    li 7, 0
 ; PPC32-NEXT:  .LBB0_3: # %start
 ; PPC32-NEXT:    mr 3, 8
 ; PPC32-NEXT:    mtcrf 32, 12 # cr2
diff --git a/llvm/test/CodeGen/PowerPC/urem-lkk.ll b/llvm/test/CodeGen/PowerPC/urem-lkk.ll
--- a/llvm/test/CodeGen/PowerPC/urem-lkk.ll
+++ b/llvm/test/CodeGen/PowerPC/urem-lkk.ll
@@ -8,12 +8,12 @@
 ; CHECK-NEXT:    lis 4, 22765
 ; CHECK-NEXT:    ori 4, 4, 8969
 ; CHECK-NEXT:    mulhwu 4, 3, 4
-; CHECK-NEXT:    subf 5, 4, 3
+; CHECK-NEXT:    sub 5, 3, 4
 ; CHECK-NEXT:    srwi 5, 5, 1
 ; CHECK-NEXT:    add 4, 5, 4
 ; CHECK-NEXT:    srwi 4, 4, 6
 ; CHECK-NEXT:    mulli 4, 4, 95
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = urem i32 %x, 95
   ret i32 %1
@@ -28,7 +28,7 @@
 ; CHECK-NEXT:    mulhwu 4, 3, 4
 ; CHECK-NEXT:    srwi 4, 4, 10
 ; CHECK-NEXT:    mulli 4, 4, 1060
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = urem i32 %x, 1060
   ret i32 %1
@@ -42,12 +42,12 @@
 ; CHECK-NEXT:    lis 4, 22765
 ; CHECK-NEXT:    ori 4, 4, 8969
 ; CHECK-NEXT:    mulhwu 4, 3, 4
-; CHECK-NEXT:    subf 5, 4, 3
+; CHECK-NEXT:    sub 5, 3, 4
 ; CHECK-NEXT:    srwi 5, 5, 1
 ; CHECK-NEXT:    add 4, 5, 4
 ; CHECK-NEXT:    srwi 4, 4, 6
 ; CHECK-NEXT:    mulli 5, 4, 95
-; CHECK-NEXT:    subf 3, 5, 3
+; CHECK-NEXT:    sub 3, 3, 5
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = urem i32 %x, 95
diff --git a/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll b/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
--- a/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
+++ b/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
@@ -15,7 +15,7 @@
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    lis r5, 21399
 ; P9LE-NEXT:    ori r5, r5, 33437
-; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulld r4, r4, r5
 ; P9LE-NEXT:    lis r5, 16727
 ; P9LE-NEXT:    ori r5, r5, 2287
@@ -25,7 +25,7 @@
 ; P9LE-NEXT:    mtvsrd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulld r4, r4, r5
 ; P9LE-NEXT:    lis r5, 8456
 ; P9LE-NEXT:    ori r5, r5, 16913
@@ -112,7 +112,7 @@
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r5
 ; P9BE-NEXT:    rldicl r4, r4, 32, 32
-; P9BE-NEXT:    subf r5, r4, r3
+; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
@@ -136,9 +136,9 @@
 ; P8LE-NEXT:    rldicl r9, r4, 32, 48
 ; P8LE-NEXT:    rlwinm r6, r5, 0, 16, 31
 ; P8LE-NEXT:    rldicl r10, r4, 16, 48
-; P8LE-NEXT:    rlwinm r11, r9, 0, 16, 31
+; P8LE-NEXT:    clrlwi r11, r9, 16
 ; P8LE-NEXT:    clrldi r7, r6, 32
-; P8LE-NEXT:    rlwinm r12, r10, 0, 16, 31
+; P8LE-NEXT:    clrlwi r12, r10, 16
 ; P8LE-NEXT:    mulld r3, r7, r3
 ; P8LE-NEXT:    lis r7, 16727
 ; P8LE-NEXT:    ori r7, r7, 2287
@@ -206,7 +206,7 @@
 ; P8BE-NEXT:    rldicl r3, r3, 32, 32
 ; P8BE-NEXT:    rlwinm r4, r4, 0, 16, 31
 ; P8BE-NEXT:    mulld r10, r11, r10
-; P8BE-NEXT:    subf r11, r3, r5
+; P8BE-NEXT:    sub r11, r5, r3
 ; P8BE-NEXT:    srwi r11, r11, 1
 ; P8BE-NEXT:    rldicl r9, r9, 24, 40
 ; P8BE-NEXT:    add r3, r11, r3
@@ -313,7 +313,7 @@
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r5
 ; P9BE-NEXT:    rldicl r4, r4, 32, 32
-; P9BE-NEXT:    subf r6, r4, r3
+; P9BE-NEXT:    sub r6, r3, r4
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r4, r6, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
@@ -327,7 +327,7 @@
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r5
 ; P9BE-NEXT:    rldicl r4, r4, 32, 32
-; P9BE-NEXT:    subf r6, r4, r3
+; P9BE-NEXT:    sub r6, r3, r4
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r4, r6, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
@@ -341,7 +341,7 @@
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r5
 ; P9BE-NEXT:    rldicl r4, r4, 32, 32
-; P9BE-NEXT:    subf r6, r4, r3
+; P9BE-NEXT:    sub r6, r3, r4
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r4, r6, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
@@ -356,7 +356,7 @@
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r5
 ; P9BE-NEXT:    rldicl r4, r4, 32, 32
-; P9BE-NEXT:    subf r5, r4, r3
+; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
@@ -458,16 +458,16 @@
 ; P8BE-NEXT:    mulld r3, r11, r3
 ; P8BE-NEXT:    rldicl r8, r8, 32, 32
 ; P8BE-NEXT:    rldicl r9, r9, 32, 32
-; P8BE-NEXT:    subf r11, r8, r5
+; P8BE-NEXT:    sub r11, r5, r8
 ; P8BE-NEXT:    rldicl r10, r10, 32, 32
-; P8BE-NEXT:    subf r12, r9, r6
+; P8BE-NEXT:    sub r12, r6, r9
 ; P8BE-NEXT:    srwi r11, r11, 1
 ; P8BE-NEXT:    rldicl r3, r3, 32, 32
 ; P8BE-NEXT:    add r8, r11, r8
-; P8BE-NEXT:    subf r11, r10, r7
+; P8BE-NEXT:    sub r11, r7, r10
 ; P8BE-NEXT:    srwi r12, r12, 1
 ; P8BE-NEXT:    add r9, r12, r9
-; P8BE-NEXT:    subf r12, r3, r4
+; P8BE-NEXT:    sub r12, r4, r3
 ; P8BE-NEXT:    srwi r11, r11, 1
 ; P8BE-NEXT:    srwi r8, r8, 6
 ; P8BE-NEXT:    add r10, r11, r10
@@ -633,7 +633,7 @@
 ; P9BE-NEXT:    clrldi r8, r3, 32
 ; P9BE-NEXT:    mulld r6, r8, r6
 ; P9BE-NEXT:    rldicl r6, r6, 32, 32
-; P9BE-NEXT:    subf r8, r6, r3
+; P9BE-NEXT:    sub r8, r3, r6
 ; P9BE-NEXT:    srwi r8, r8, 1
 ; P9BE-NEXT:    add r6, r8, r6
 ; P9BE-NEXT:    srwi r6, r6, 6
@@ -768,7 +768,7 @@
 ; P8BE-NEXT:    rldicl r0, r0, 32, 32
 ; P8BE-NEXT:    add r8, r8, r11
 ; P8BE-NEXT:    srwi r9, r9, 1
-; P8BE-NEXT:    subf r11, r5, r6
+; P8BE-NEXT:    sub r11, r6, r5
 ; P8BE-NEXT:    subf r10, r0, r10
 ; P8BE-NEXT:    add r9, r9, r12
 ; P8BE-NEXT:    srwi r8, r8, 6
@@ -878,7 +878,7 @@
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r5
 ; P9BE-NEXT:    rldicl r4, r4, 32, 32
-; P9BE-NEXT:    subf r5, r4, r3
+; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
@@ -943,7 +943,7 @@
 ; P8BE-NEXT:    clrldi r6, r5, 32
 ; P8BE-NEXT:    mulld r3, r6, r3
 ; P8BE-NEXT:    rldicl r3, r3, 32, 32
-; P8BE-NEXT:    subf r6, r3, r5
+; P8BE-NEXT:    sub r6, r5, r3
 ; P8BE-NEXT:    srwi r6, r6, 1
 ; P8BE-NEXT:    add r3, r6, r3
 ; P8BE-NEXT:    rldicl r6, r4, 32, 48
@@ -980,7 +980,7 @@
 ; P9LE-NEXT:    oris r5, r5, 51306
 ; P9LE-NEXT:    ori r6, r6, 17097
 ; P9LE-NEXT:    ori r5, r5, 30865
-; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulld r4, r4, r6
 ; P9LE-NEXT:    lis r6, 24749
 ; P9LE-NEXT:    ori r6, r6, 47143
@@ -990,7 +990,7 @@
 ; P9LE-NEXT:    mtvsrd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulld r4, r4, r6
 ; P9LE-NEXT:    rldicl r4, r4, 21, 43
 ; P9LE-NEXT:    mulli r4, r4, 5423
@@ -1074,10 +1074,10 @@
 ; P8LE-NEXT:    mfvsrd r4, f0
 ; P8LE-NEXT:    rldicl r6, r4, 32, 48
 ; P8LE-NEXT:    rldicl r7, r4, 16, 48
-; P8LE-NEXT:    rlwinm r9, r6, 0, 16, 31
+; P8LE-NEXT:    clrlwi r9, r6, 16
 ; P8LE-NEXT:    rldicl r4, r4, 48, 48
 ; P8LE-NEXT:    mulld r5, r9, r5
-; P8LE-NEXT:    rlwinm r9, r7, 0, 16, 31
+; P8LE-NEXT:    clrlwi r9, r7, 16
 ; P8LE-NEXT:    mulld r8, r9, r8
 ; P8LE-NEXT:    rlwinm r9, r4, 31, 17, 31
 ; P8LE-NEXT:    mulld r3, r9, r3
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt
@@ -1825,16 +1825,16 @@
 # CHECK: addic. 2, 3, -128
 0x34 0x43 0xff 0x80
 
-# CHECK: subf 2, 4, 3
+# CHECK: sub 2, 3, 4
 0x7c 0x44 0x18 0x50
 
-# CHECK: subf. 2, 4, 3
+# CHECK: sub. 2, 3, 4
 0x7c 0x44 0x18 0x51
 
-# CHECK: subfc 2, 4, 3
+# CHECK: subc 2, 3, 4
 0x7c 0x44 0x18 0x10
 
-# CHECK: subfc. 2, 4, 3
+# CHECK: subc. 2, 3, 4
 0x7c 0x44 0x18 0x11
 
 # CHECK: cmpdi 2, 3, 128
@@ -2239,16 +2239,16 @@
 # CHECK: mr 2, 3
 0x7c 0x62 0x1b 0x78
 
-# CHECK: or. 2, 3, 3
+# CHECK: mr. 2, 3
 0x7c 0x62 0x1b 0x79
 
-# CHECK: nor 2, 3, 3
+# CHECK: not 2, 3
 0x7c 0x62 0x18 0xf8
 
-# CHECK: nor. 2, 3, 3
+# CHECK: not. 2, 3
 0x7c 0x62 0x18 0xf9
 
-# CHECK: mtcrf 255, 2
+# CHECK: mtcr 2
 0x7c 0x4f 0xf1 0x20
 
 # CHECK: dss 3
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-p8htm.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-p8htm.txt
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-p8htm.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-p8htm.txt
@@ -6,10 +6,10 @@
 # CHECK: tbegin. 0
 0x7c 0x00 0x05 0x1d
 
-# CHECK: tend. 0
+# CHECK: tend.
 0x7c 0x00 0x05 0x5d
 
-# CHECK: tend. 1
+# CHECK: tendall.
 0x7e 0x00 0x05 0x5d
 
 # CHECK: tabort. 3
@@ -27,10 +27,10 @@
 # CHECK: tabortwci. 0, 4, 2
 0x7c 0x04 0x16 0x9d
 
-# CHECK: tsr. 1
+# CHECK: tresume.
 0x7c 0x20 0x05 0xdd
 
-# CHECK: tsr. 0
+# CHECK: tsuspend.
 0x7c 0x00 0x05 0xdd
 
 # CHECK: tcheck 0
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
@@ -79,7 +79,7 @@
 # CHECK: mfbhrbe 9, 983
 0x7d 0x3e 0xba 0x5c
 
-# CHECK: rfebb 1
+# CHECK: rfebb
 0x4c 0x00 0x09 0x24
 
 # CHECK: lbz 2, 128(4)                   
@@ -244,10 +244,10 @@
 # CHECK: addo. 2, 3, 4
 0x7c 0x43 0x26 0x15
 
-# CHECK: subf 2, 3, 4                    
+# CHECK: sub 2, 4, 3                     
 0x7c 0x43 0x20 0x50
 
-# CHECK: subf. 2, 3, 4                   
+# CHECK: sub. 2, 4, 3                    
 0x7c 0x43 0x20 0x51
 
 # CHECK: subfo 2, 3, 4
@@ -277,11 +277,11 @@
 # CHECK: addco. 2, 3, 4
 0x7c 0x43 0x24 0x15
 
-# CHECK: subfc 2, 3, 4                   
+# CHECK: subc 2, 4, 3                    
 0x7c 0x43 0x20 0x10
 
-# CHECK: subfc 2, 3, 4                   
-0x7c 0x43 0x20 0x10
+# CHECK: subc. 2, 4, 3                   
+0x7c 0x43 0x20 0x11
 
 # CHECK: subfco 2, 3, 4
 0x7c 0x43 0x24 0x10
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
@@ -79,7 +79,7 @@
 # CHECK: mfbhrbe 9, 983
 0x5c 0xba 0x3e 0x7d
 
-# CHECK: rfebb 1
+# CHECK: rfebb
 0x24 0x09 0x00 0x4c
 
 # CHECK: lbz 2, 128(4)
@@ -241,10 +241,10 @@
 # CHECK: addo. 2, 3, 4
 0x15 0x26 0x43 0x7c
 
-# CHECK: subf 2, 3, 4
+# CHECK: sub 2, 4, 3
 0x50 0x20 0x43 0x7c
 
-# CHECK: subf. 2, 3, 4
+# CHECK: sub. 2, 4, 3
 0x51 0x20 0x43 0x7c
 
 # CHECK: subfo 2, 3, 4
@@ -274,11 +274,11 @@
 # CHECK: addco. 2, 3, 4
 0x15 0x24 0x43 0x7c
 
-# CHECK: subfc 2, 3, 4
+# CHECK: subc 2, 4, 3
 0x10 0x20 0x43 0x7c
 
-# CHECK: subfc 2, 3, 4
-0x10 0x20 0x43 0x7c
+# CHECK: subc. 2, 4, 3
+0x11 0x20 0x43 0x7c
 
 # CHECK: subfco 2, 3, 4
 0x10 0x24 0x43 0x7c
diff --git a/llvm/test/MC/PowerPC/htm.s b/llvm/test/MC/PowerPC/htm.s
--- a/llvm/test/MC/PowerPC/htm.s
+++ b/llvm/test/MC/PowerPC/htm.s
@@ -8,11 +8,11 @@
 # CHECK-LE: tbegin. 1                      # encoding: [0x1d,0x05,0x20,0x7c]
             tbegin. 1
 
-# CHECK-BE: tend. 0                        # encoding: [0x7c,0x00,0x05,0x5d]
-# CHECK-LE: tend. 0                        # encoding: [0x5d,0x05,0x00,0x7c]
+# CHECK-BE: tend.                          # encoding: [0x7c,0x00,0x05,0x5d]
+# CHECK-LE: tend.                          # encoding: [0x5d,0x05,0x00,0x7c]
             tend. 0
-# CHECK-BE: tend. 1                        # encoding: [0x7e,0x00,0x05,0x5d]
-# CHECK-LE: tend. 1                        # encoding: [0x5d,0x05,0x00,0x7e]
+# CHECK-BE: tendall.                       # encoding: [0x7e,0x00,0x05,0x5d]
+# CHECK-LE: tendall.                       # encoding: [0x5d,0x05,0x00,0x7e]
             tend. 1
 
 # CHECK-BE: tabort. 9                      # encoding: [0x7c,0x09,0x07,0x1d]
@@ -31,11 +31,11 @@
 # CHECK-LE: tabortwci. 0, 9, 0             # encoding: [0x9d,0x06,0x09,0x7c]
             tabortwci. 0, 9, 0
 
-# CHECK-BE: tsr. 0                         # encoding: [0x7c,0x00,0x05,0xdd]
-# CHECK-LE: tsr. 0                         # encoding: [0xdd,0x05,0x00,0x7c]
+# CHECK-BE: tsuspend.                      # encoding: [0x7c,0x00,0x05,0xdd]
+# CHECK-LE: tsuspend.                      # encoding: [0xdd,0x05,0x00,0x7c]
             tsr. 0
-# CHECK-BE: tsr. 1                         # encoding: [0x7c,0x20,0x05,0xdd]
-# CHECK-LE: tsr. 1                         # encoding: [0xdd,0x05,0x20,0x7c]
+# CHECK-BE: tresume.                       # encoding: [0x7c,0x20,0x05,0xdd]
+# CHECK-LE: tresume.                       # encoding: [0xdd,0x05,0x20,0x7c]
             tsr. 1
 
 # CHECK-BE: tcheck 0                       # encoding: [0x7c,0x00,0x05,0x9c]
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding.s b/llvm/test/MC/PowerPC/ppc64-encoding.s
--- a/llvm/test/MC/PowerPC/ppc64-encoding.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding.s
@@ -161,8 +161,8 @@
 # CHECK-BE: mfbhrbe 9, 983                  # encoding: [0x7d,0x3e,0xba,0x5c]
 # CHECK-LE: mfbhrbe 9, 983                  # encoding: [0x5c,0xba,0x3e,0x7d]
             mfbhrbe 9, 983
-# CHECK-BE: rfebb 1                         # encoding: [0x4c,0x00,0x09,0x24]
-# CHECK-LE: rfebb 1                         # encoding: [0x24,0x09,0x00,0x4c]
+# CHECK-BE: rfebb                           # encoding: [0x4c,0x00,0x09,0x24]
+# CHECK-LE: rfebb                           # encoding: [0x24,0x09,0x00,0x4c]
             rfebb 1
 
 # Fixed-point facility
@@ -345,11 +345,11 @@
 # CHECK-BE: addo. 2, 3, 4                   # encoding: [0x7c,0x43,0x26,0x15]
 # CHECK-LE: addo. 2, 3, 4                   # encoding: [0x15,0x26,0x43,0x7c]
             addo. 2, 3, 4
-# CHECK-BE: subf 2, 3, 4                    # encoding: [0x7c,0x43,0x20,0x50]
-# CHECK-LE: subf 2, 3, 4                    # encoding: [0x50,0x20,0x43,0x7c]
+# CHECK-BE: sub 2, 4, 3                     # encoding: [0x7c,0x43,0x20,0x50]
+# CHECK-LE: sub 2, 4, 3                     # encoding: [0x50,0x20,0x43,0x7c]
             subf 2, 3, 4
-# CHECK-BE: subf. 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0x51]
-# CHECK-LE: subf. 2, 3, 4                   # encoding: [0x51,0x20,0x43,0x7c]
+# CHECK-BE: sub. 2, 4, 3                    # encoding: [0x7c,0x43,0x20,0x51]
+# CHECK-LE: sub. 2, 4, 3                    # encoding: [0x51,0x20,0x43,0x7c]
             subf. 2, 3, 4
 # CHECK-BE: subfo 2, 3, 4                   # encoding: [0x7c,0x43,0x24,0x50]
 # CHECK-LE: subfo 2, 3, 4                   # encoding: [0x50,0x24,0x43,0x7c]
@@ -379,11 +379,11 @@
 # CHECK-BE: addco. 2, 3, 4                  # encoding: [0x7c,0x43,0x24,0x15]
 # CHECK-LE: addco. 2, 3, 4                  # encoding: [0x15,0x24,0x43,0x7c]
             addco. 2, 3, 4
-# CHECK-BE: subfc 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0x10]
-# CHECK-LE: subfc 2, 3, 4                   # encoding: [0x10,0x20,0x43,0x7c]
+# CHECK-BE: subc 2, 4, 3                    # encoding: [0x7c,0x43,0x20,0x10]
+# CHECK-LE: subc 2, 4, 3                    # encoding: [0x10,0x20,0x43,0x7c]
             subfc 2, 3, 4
-# CHECK-BE: subfc 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0x10]
-# CHECK-LE: subfc 2, 3, 4                   # encoding: [0x10,0x20,0x43,0x7c]
+# CHECK-BE: subc 2, 4, 3                    # encoding: [0x7c,0x43,0x20,0x10]
+# CHECK-LE: subc 2, 4, 3                    # encoding: [0x10,0x20,0x43,0x7c]
             subfc 2, 3, 4
 # CHECK-BE: subfco 2, 3, 4                  # encoding: [0x7c,0x43,0x24,0x10]
 # CHECK-LE: subfco 2, 3, 4                  # encoding: [0x10,0x24,0x43,0x7c]
diff --git a/llvm/test/MC/PowerPC/ppc64-operands.s b/llvm/test/MC/PowerPC/ppc64-operands.s
--- a/llvm/test/MC/PowerPC/ppc64-operands.s
+++ b/llvm/test/MC/PowerPC/ppc64-operands.s
@@ -20,12 +20,12 @@
 # CHECK-LE: add 31, 31, 31                  # encoding: [0x14,0xfa,0xff,0x7f]
             add 31, 31, 31
 
-# CHECK-BE: addi 1, 0, 0                    # encoding: [0x38,0x20,0x00,0x00]
-# CHECK-LE: addi 1, 0, 0                    # encoding: [0x00,0x00,0x20,0x38]
+# CHECK-BE: li 1, 0                         # encoding: [0x38,0x20,0x00,0x00]
+# CHECK-LE: li 1, 0                         # encoding: [0x00,0x00,0x20,0x38]
             addi 1, 0, 0
 
-# CHECK-BE: addi 1, 0, 0                    # encoding: [0x38,0x20,0x00,0x00]
-# CHECK-LE: addi 1, 0, 0                    # encoding: [0x00,0x00,0x20,0x38]
+# CHECK-BE: li 1, 0                         # encoding: [0x38,0x20,0x00,0x00]
+# CHECK-LE: li 1, 0                         # encoding: [0x00,0x00,0x20,0x38]
             addi 1, %r0, 0
 
 # Signed 16-bit immediate operands
@@ -34,12 +34,12 @@
 # CHECK-LE: addi 1, 2, 0                    # encoding: [0x00,0x00,0x22,0x38]
             addi 1, 2, 0
 
-# CHECK-BE: addi 1, 0, -32768               # encoding: [0x38,0x20,0x80,0x00]
-# CHECK-LE: addi 1, 0, -32768               # encoding: [0x00,0x80,0x20,0x38]
+# CHECK-BE: li 1, -32768                    # encoding: [0x38,0x20,0x80,0x00]
+# CHECK-LE: li 1, -32768                    # encoding: [0x00,0x80,0x20,0x38]
             addi 1, 0, -32768
 
-# CHECK-BE: addi 1, 0, 32767                # encoding: [0x38,0x20,0x7f,0xff]
-# CHECK-LE: addi 1, 0, 32767                # encoding: [0xff,0x7f,0x20,0x38]
+# CHECK-BE: li 1, 32767                     # encoding: [0x38,0x20,0x7f,0xff]
+# CHECK-LE: li 1, 32767                     # encoding: [0xff,0x7f,0x20,0x38]
             addi 1, 0, 32767
 
 # Unsigned 16-bit immediate operands
@@ -54,12 +54,12 @@
 
 # Signed 16-bit immediate operands (extended range for addis)
 
-# CHECK-BE: addis 1, 0, 0                   # encoding: [0x3c,0x20,0x00,0x00]
-# CHECK-LE: addis 1, 0, 0                   # encoding: [0x00,0x00,0x20,0x3c]
+# CHECK-BE: lis 1, 0                        # encoding: [0x3c,0x20,0x00,0x00]
+# CHECK-LE: lis 1, 0                        # encoding: [0x00,0x00,0x20,0x3c]
             addis 1, 0, -65536
 
-# CHECK-BE: addis 1, 0, -1                  # encoding: [0x3c,0x20,0xff,0xff]
-# CHECK-LE: addis 1, 0, -1                  # encoding: [0xff,0xff,0x20,0x3c]
+# CHECK-BE: lis 1, -1                       # encoding: [0x3c,0x20,0xff,0xff]
+# CHECK-LE: lis 1, -1                       # encoding: [0xff,0xff,0x20,0x3c]
             addis 1, 0, 65535
 
 # D-Form memory operands