diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -706,7 +706,6 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) { - Register DstReg = I.getOperand(0).getReg(); Register SrcReg = I.getOperand(1).getReg(); const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); @@ -723,13 +722,6 @@ return false; } - // A couple helpers below, for making sure that the copy we produce is valid. - - // Set to true if we insert a SUBREG_TO_REG. If we do this, then we don't want - // to verify that the src and dst are the same size, since that's handled by - // the SUBREG_TO_REG. - bool KnownValid = false; - // Returns true, or asserts if something we don't expect happens. Instead of // returning true, we return isValidCopy() to ensure that we verify the // result. @@ -739,13 +731,12 @@ (!Register::isPhysicalRegister(I.getOperand(0).getReg()) && !Register::isPhysicalRegister(I.getOperand(1).getReg()))) && "No phys reg on generic operator!"); - assert(KnownValid || isValidCopy(I, DstRegBank, MRI, TRI, RBI)); - (void)KnownValid; - return true; + bool ValidCopy = isValidCopy(I, DstRegBank, MRI, TRI, RBI); + assert(ValidCopy && "Invalid copy."); + return ValidCopy; }; - // Is this a copy? If so, then we may need to insert a subregister copy, or - // a SUBREG_TO_REG. + // Is this a copy? If so, then we may need to insert a subregister copy. if (I.isCopy()) { // Yes. Check if there's anything to fix up. if (!SrcRC) { @@ -758,48 +749,23 @@ // If the source register is bigger than the destination we need to perform // a subregister copy. - if (SrcSize > DstSize) { - unsigned SubReg = 0; + unsigned SubReg = 0; - // If the source bank doesn't support a subregister copy small enough, - // then we first need to copy to the destination bank. - if (getMinSizeForRegBank(SrcRegBank) > DstSize) { - const TargetRegisterClass *SubregRC = getMinClassForRegBank( - DstRegBank, SrcSize, /* GetAllRegSet = */ true); - getSubRegForClass(DstRC, TRI, SubReg); + // If the source bank doesn't support a subregister copy small enough, + // then we first need to copy to the destination bank. + if (getMinSizeForRegBank(SrcRegBank) > DstSize) { + const TargetRegisterClass *SubregRC = getMinClassForRegBank( + DstRegBank, SrcSize, /* GetAllRegSet */ true); + getSubRegForClass(DstRC, TRI, SubReg); - MachineIRBuilder MIB(I); - auto Copy = MIB.buildCopy({SubregRC}, {SrcReg}); - copySubReg(I, MRI, RBI, Copy.getReg(0), DstRC, SubReg); - } else { - const TargetRegisterClass *SubregRC = getMinClassForRegBank( - SrcRegBank, DstSize, /* GetAllRegSet = */ true); - getSubRegForClass(SubregRC, TRI, SubReg); - copySubReg(I, MRI, RBI, SrcReg, DstRC, SubReg); - } - - return CheckCopy(); - } - - // Is this a cross-bank copy? - if (DstRegBank.getID() != SrcRegBank.getID()) { - if (DstRegBank.getID() == AArch64::GPRRegBankID && DstSize == 32 && - SrcSize == 16) { - // Special case for FPR16 to GPR32. - // FIXME: This can probably be generalized like the above case. - Register PromoteReg = - MRI.createVirtualRegister(&AArch64::FPR32RegClass); - BuildMI(*I.getParent(), I, I.getDebugLoc(), - TII.get(AArch64::SUBREG_TO_REG), PromoteReg) - .addImm(0) - .addUse(SrcReg) - .addImm(AArch64::hsub); - MachineOperand &RegOp = I.getOperand(1); - RegOp.setReg(PromoteReg); - - // Promise that the copy is implicitly validated by the SUBREG_TO_REG. - KnownValid = true; - } + MachineIRBuilder MIB(I); + auto Copy = MIB.buildCopy({SubregRC}, {SrcReg}); + copySubReg(I, MRI, RBI, Copy.getReg(0), DstRC, SubReg); + } else if (SrcSize > DstSize) { + const TargetRegisterClass *SubregRC = getMinClassForRegBank( + SrcRegBank, DstSize, /* GetAllRegSet */ true); + getSubRegForClass(SubregRC, TRI, SubReg); + copySubReg(I, MRI, RBI, SrcReg, DstRC, SubReg); } // If the destination is a physical register, then there's nothing to diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir @@ -48,11 +48,9 @@ ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0 ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub - ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]] + ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY]] ; CHECK: [[BFMWri:%[0-9]+]]:gpr32 = BFMWri [[DEF]], [[COPY2]], 0, 15 - ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub - ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG1]] + ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY1]] ; CHECK: [[BFMWri1:%[0-9]+]]:gpr32 = BFMWri [[BFMWri]], [[COPY3]], 16, 15 ; CHECK: [[COPY4:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: STRWui [[BFMWri1]], [[COPY4]], 0 :: (store 4 into %ir.addr, align 2) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir @@ -77,8 +77,7 @@ ; CHECK: bb.0: ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: liveins: $h0 - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, $h0, %subreg.hsub - ; CHECK: %copy:gpr32 = COPY [[SUBREG_TO_REG]] + ; CHECK: %copy:gpr32 = COPY $h0 ; CHECK: TBNZW %copy, 3, %bb.1 ; CHECK: B %bb.0 ; CHECK: bb.1: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir b/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir @@ -27,8 +27,7 @@ ; CHECK: successors: %bb.2(0x80000000) ; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[CSELWr]], %bb.1, %8, %bb.2 ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]] - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[FCVTHSr]], %subreg.hsub - ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] + ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[FCVTHSr]] ; CHECK: STRHHui [[PHI]], [[DEF1]], 0 :: (store 2 into `half* undef`) ; CHECK: B %bb.2 bb.0: