diff --git a/llvm/test/Analysis/MemorySSA/invariant-groups.ll b/llvm/test/Analysis/MemorySSA/invariant-groups.ll --- a/llvm/test/Analysis/MemorySSA/invariant-groups.ll +++ b/llvm/test/Analysis/MemorySSA/invariant-groups.ll @@ -342,7 +342,7 @@ ; CHECK-NEXT: call void @clobber8(i8* %ptr) call void @clobber8(i8* %ptr) ; 6 = MemoryDef(5) -; CHECK-NEXT call void @use(i8* %ptr2) +; CHECK-NEXT: call void @use(i8* %ptr2) call void @use(i8* %ptr2) ; CHECK: 7 = MemoryDef(6) ; CHECK-NEXT: call void @use(i8* %ptr3) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll @@ -136,7 +136,7 @@ br label %block } -; FALLBACK-WITH-REPORT-ERR remark: :0:0: unable to legalize instruction: G_STORE %3, %4 :: (store 12 into `i96* undef`, align 16) (in function: nonpow2_add_narrowing) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %3, %4 :: (store 12 into `i96* undef`, align 16) (in function: nonpow2_add_narrowing) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_add_narrowing ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_add_narrowing: define void @nonpow2_add_narrowing() { @@ -147,7 +147,7 @@ ret void } -; FALLBACK-WITH-REPORT-ERR remark: :0:0: unable to legalize instruction: G_STORE %3, %4 :: (store 12 into `i96* undef`, align 16) (in function: nonpow2_add_narrowing) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %3, %4 :: (store 12 into `i96* undef`, align 16) (in function: nonpow2_add_narrowing) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_or_narrowing ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_or_narrowing: define void @nonpow2_or_narrowing() { @@ -160,7 +160,7 @@ ret void } -; FALLBACK-WITH-REPORT-ERR remark: :0:0: unable to legalize instruction: G_STORE %0, %1 :: (store 12 into `i96* undef`, align 16) (in function: nonpow2_load_narrowing) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %0, %1 :: (store 12 into `i96* undef`, align 16) (in function: nonpow2_load_narrowing) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_load_narrowing ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_load_narrowing: define void @nonpow2_load_narrowing() { diff --git a/llvm/test/CodeGen/AMDGPU/fmin_legacy.ll b/llvm/test/CodeGen/AMDGPU/fmin_legacy.ll --- a/llvm/test/CodeGen/AMDGPU/fmin_legacy.ll +++ b/llvm/test/CodeGen/AMDGPU/fmin_legacy.ll @@ -106,7 +106,7 @@ ; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]] -; VI-SAFE v_cmp_le_f32_e32 vcc, [[A]], [[B]] +; VI-SAFE: v_cmp_le_f32_e32 vcc, [[A]], [[B]] ; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]] ; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]] @@ -130,7 +130,7 @@ ; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]] -; VI-SAFE v_cmp_lt_f32_e32 vcc, [[A]], [[B]] +; VI-SAFE: v_cmp_lt_f32_e32 vcc, [[A]], [[B]] ; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]] ; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]] @@ -154,7 +154,7 @@ ; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]] -; VI-SAFE v_cmp_lt_f32_e32 vcc, [[A]], [[B]] +; VI-SAFE: v_cmp_lt_f32_e32 vcc, [[A]], [[B]] ; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]] ; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]] @@ -178,7 +178,7 @@ ; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]] -; VI-SAFE v_cmp_lt_f32_e32 vcc, [[A]], [[B]] +; VI-SAFE: v_cmp_lt_f32_e32 vcc, [[A]], [[B]] ; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]] ; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]] @@ -202,9 +202,9 @@ ; SI-SAFE: v_min_legacy_f32_e32 ; SI-SAFE: v_min_legacy_f32_e32 -; VI-SAFE v_cmp_lt_f32_e32 +; VI-SAFE: v_cmp_lt_f32_e32 ; VI-SAFE: v_cndmask_b32_e32 -; VI-SAFE v_cmp_lt_f32_e32 +; VI-SAFE: v_cmp_lt_f32_e32 ; VI-SAFE: v_cndmask_b32_e32 ; GCN-NONAN: v_min_f32_e32 diff --git a/llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll b/llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll --- a/llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll +++ b/llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll @@ -1,11 +1,11 @@ ; RUN: llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs < %s | FileCheck %s ; CHECK-LABEL: {{^}}test: -; CHECK s_and_saveexec_b64 -; CHECK s_xor_b64 -; CHECK s_or_b64 exec, exec -; CHECK s_andn2_b64 exec, exec -; CHECK s_cbranch_execnz +; CHECK: s_and_saveexec_b64 +; CHECK: s_xor_b64 +; CHECK: s_or_b64 exec, exec +; CHECK: s_andn2_b64 exec, exec +; CHECK: s_cbranch_execnz define amdgpu_kernel void @test(i32 %arg, i32 %arg1) { bb: %tmp = icmp ne i32 %arg, 0 diff --git a/llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll b/llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll --- a/llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll +++ b/llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll @@ -8,7 +8,7 @@ ; No dynamic indexing required ; GCN-LABEL: {{^}}extract_insert_same_dynelt_v4i32: ; GCN: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd{{$}} -; GCN-NOT buffer_load_dword +; GCN-NOT: buffer_load_dword ; GCN-NOT: [[VAL]] ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] ; GCN-NOT: [[VVAL]] @@ -49,7 +49,7 @@ ; GCN-LABEL: {{^}}extract_insert_same_elt2_v4i32: ; GCN: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd{{$}} -; GCN-NOT buffer_load_dword +; GCN-NOT: buffer_load_dword ; GCN-NOT: [[VAL]] ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] ; GCN-NOT: [[VVAL]] @@ -68,7 +68,7 @@ ; GCN-LABEL: {{^}}extract_insert_same_dynelt_v4f32: ; GCN: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd{{$}} -; GCN-NOT buffer_load_dword +; GCN-NOT: buffer_load_dword ; GCN-NOT: [[VAL]] ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] ; GCN-NOT: [[VVAL]] diff --git a/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir b/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir --- a/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir +++ b/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir @@ -47,7 +47,7 @@ # CHECK_SWIFT: Latency : 3 # CHECK_R52: Latency : 4 # -# CHECK : SU(6): %6 = t2ADDrr %3:rgpr, %3:rgpr, 14, $noreg, $noreg +# CHECK: SU(6): %6 = t2ADDrr %3:rgpr, %3:rgpr, 14, $noreg, $noreg # CHECK_A9: Latency : 1 # CHECK_SWIFT: Latency : 1 # CHECK_R52: Latency : 3 diff --git a/llvm/test/CodeGen/ARM/thumb1_return_sequence.ll b/llvm/test/CodeGen/ARM/thumb1_return_sequence.ll --- a/llvm/test/CodeGen/ARM/thumb1_return_sequence.ll +++ b/llvm/test/CodeGen/ARM/thumb1_return_sequence.ll @@ -28,7 +28,7 @@ ; CHECK-V4T-NEXT: ldr [[POP:r[4567]]], [sp, #16] ; CHECK-V4T-NEXT: mov lr, [[POP]] ; CHECK-V4T-NEXT: pop {[[SAVED]]} -; CHECK-V4T-NEXT add sp, sp, #4 +; CHECK-V4T-NEXT: add sp, sp, #4 ; The ISA for v4 does not support pop pc, so make sure we do not emit ; one even when we do not need to update SP. ; CHECK-V4T-NOT: pop {pc} @@ -104,7 +104,7 @@ ; used for the return value). ; CHECK-V4T-NEXT: pop {[[POP_REG:r[1-3]]]} ; CHECK-V4T-NEXT: bx [[POP_REG]] -; CHECK-V5T: pop {[[SAVED]], pc} +; CHECK-V5T: pop {[[SAVED]], pc} } ; CHECK-V4T-LABEL: simplevariadicframe diff --git a/llvm/test/CodeGen/PowerPC/fold-frame-offset-using-rr.mir b/llvm/test/CodeGen/PowerPC/fold-frame-offset-using-rr.mir --- a/llvm/test/CodeGen/PowerPC/fold-frame-offset-using-rr.mir +++ b/llvm/test/CodeGen/PowerPC/fold-frame-offset-using-rr.mir @@ -11,7 +11,7 @@ --- name: testIndexForm1 -#CHECK : name : testIndexForm1 +#CHECK-LABEL: name : testIndexForm1 # ToBeDeletedReg equals to ScaleReg tracksRegLiveness: true body: | @@ -27,7 +27,7 @@ ... --- name: testIndexForm2 -#CHECK : name : testIndexForm2 +#CHECK-LABEL: name : testIndexForm2 # ToBeDeletedReg equals to ToBeChangedReg tracksRegLiveness: true body: | @@ -43,7 +43,7 @@ ... --- name: testIndexForm3 -#CHECK : name : testIndexForm3 +#CHECK-LABEL: name : testIndexForm3 # There is other use for ToBeDeletedReg between ADD instr and Imm instr tracksRegLiveness: true body: | @@ -61,7 +61,7 @@ ... --- name: testIndexForm4 -#CHECK : name : testIndexForm3 +#CHECK-LABEL: name : testIndexForm3 # There is other use for ToBeChangedReg between ADDI instr and ADD instr tracksRegLiveness: true body: | @@ -79,7 +79,7 @@ ... --- name: testIndexForm5 -#CHECK : name : testIndexForm5 +#CHECK-LABEL: name : testIndexForm5 # ToBeChangedReg has no killed flag tracksRegLiveness: true body: | @@ -97,7 +97,7 @@ ... --- name: testIndexForm6 -#CHECK : name : testIndexForm6 +#CHECK-LABEL: name : testIndexForm6 # ToBeDeletedReg has no killed flag tracksRegLiveness: true body: | @@ -114,7 +114,7 @@ ... --- name: testIndexForm7 -#CHECK : name : testIndexForm7 +#CHECK-LABEL: name : testIndexForm7 # There is other def for ToBeChangedReg between ADD instr and Imm instr tracksRegLiveness: true body: | @@ -134,7 +134,7 @@ ... --- name: testIndexForm8 -#CHECK : name : testIndexForm8 +#CHECK-LABEL: name : testIndexForm8 # There is other def for ScaleReg between ADD instr and Imm instr tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir b/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir --- a/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir +++ b/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir @@ -3,7 +3,7 @@ --- name: testFoldRLWINM -#CHECK : name : testFoldRLWINM +#CHECK-LABEL: name : testFoldRLWINM tracksRegLiveness: true body: | bb.0.entry: @@ -18,7 +18,7 @@ ... --- name: testFoldRLWINMSrcFullMask1 -#CHECK : name : testFoldRLWINMSrcFullMask1 +#CHECK-LABEL: name : testFoldRLWINMSrcFullMask1 tracksRegLiveness: true body: | bb.0.entry: @@ -33,7 +33,7 @@ ... --- name: testFoldRLWINMSrcFullMask2 -#CHECK : name : testFoldRLWINMSrcFullMask2 +#CHECK-LABEL: name : testFoldRLWINMSrcFullMask2 tracksRegLiveness: true body: | bb.0.entry: @@ -48,7 +48,7 @@ ... --- name: testFoldRLWINMSrcWrapped -#CHECK : name : testFoldRLWINMSrcWrapped +#CHECK-LABEL: name : testFoldRLWINMSrcWrapped tracksRegLiveness: true body: | bb.0.entry: @@ -63,7 +63,7 @@ ... --- name: testFoldRLWINMUserWrapped -#CHECK : name : testFoldRLWINMUserWrapped +#CHECK-LABEL: name : testFoldRLWINMUserWrapped tracksRegLiveness: true body: | bb.0.entry: @@ -78,7 +78,7 @@ ... --- name: testFoldRLWINMResultWrapped -#CHECK : name : testFoldRLWINMResultWrapped +#CHECK-LABEL: name : testFoldRLWINMResultWrapped tracksRegLiveness: true body: | bb.0.entry: @@ -93,7 +93,7 @@ ... --- name: testFoldRLWINMMultipleUses -#CHECK : name : testFoldRLWINMMultipleUses +#CHECK-LABEL: name : testFoldRLWINMMultipleUses tracksRegLiveness: true body: | bb.0.entry: @@ -110,7 +110,7 @@ ... --- name: testFoldRLWINMToZero -#CHECK : name : testFoldRLWINMToZero +#CHECK-LABEL: name : testFoldRLWINMToZero tracksRegLiveness: true body: | bb.0.entry: @@ -125,7 +125,7 @@ ... --- name: testFoldRLWINM_recToZero -#CHECK : name : testFoldRLWINM_recToZero +#CHECK-LABEL: name : testFoldRLWINM_recToZero tracksRegLiveness: true body: | bb.0.entry: @@ -140,7 +140,7 @@ ... --- name: testFoldRLWINMoToZeroSrcCanNotBeDeleted -#CHECK : name : testFoldRLWINMoToZeroSrcCanNotBeDeleted +#CHECK-LABEL: name : testFoldRLWINMoToZeroSrcCanNotBeDeleted tracksRegLiveness: true body: | bb.0.entry: @@ -155,7 +155,7 @@ ... --- name: testFoldRLWINMInvalidMask -#CHECK : name : testFoldRLWINMInvalidMask +#CHECK-LABEL: name : testFoldRLWINMInvalidMask tracksRegLiveness: true body: | bb.0.entry: diff --git a/llvm/test/CodeGen/PowerPC/optcmp.ll b/llvm/test/CodeGen/PowerPC/optcmp.ll --- a/llvm/test/CodeGen/PowerPC/optcmp.ll +++ b/llvm/test/CodeGen/PowerPC/optcmp.ll @@ -60,7 +60,7 @@ ; CHECK: isel 3, 4, 3, 1 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]] ; CHECK-NO-ISEL-NEXT: b .LBB -; CHECK-NO-ISEL addi: 3, 4, 0 +; CHECK-NO-ISEL: addi: 3, 4, 0 ; CHECK: std [[REG]], 0(5) } diff --git a/llvm/test/Transforms/CodeExtractor/live_shrink_unsafe.ll b/llvm/test/Transforms/CodeExtractor/live_shrink_unsafe.ll --- a/llvm/test/Transforms/CodeExtractor/live_shrink_unsafe.ll +++ b/llvm/test/Transforms/CodeExtractor/live_shrink_unsafe.ll @@ -68,7 +68,7 @@ ret void } -; CHECK-LABEL define internal void @_Z3foo_unknown_calli.1_bb3 +; CHECK-LABEL: define internal void @_Z3foo_unknown_calli.1_bb3 ; CHECK: newFuncRoot: ; CHECK-NEXT: br label %bb3 diff --git a/llvm/test/Transforms/InstCombine/phi-preserve-ir-flags.ll b/llvm/test/Transforms/InstCombine/phi-preserve-ir-flags.ll --- a/llvm/test/Transforms/InstCombine/phi-preserve-ir-flags.ll +++ b/llvm/test/Transforms/InstCombine/phi-preserve-ir-flags.ll @@ -17,8 +17,8 @@ ; The fast-math flags should always be transfered if possible. ; CHECK-LABEL: cond.end -; CHECK [[PHI:%[^ ]*]] = phi float [ %b, %cond.true ], [ %c, %cond.false ] -; CHECK fsub fast float %a, [[PHI]] +; CHECK: [[PHI:%[^ ]*]] = phi float [ %b, %cond.true ], [ %c, %cond.false ] +; CHECK: fsub fast float %a, [[PHI]] cond.end: %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ] ret float %e @@ -39,8 +39,8 @@ ; The fast-math flags should always be transfered if possible. ; CHECK-LABEL: cond.end -; CHECK [[PHI:%[^ ]*]] = phi float [ %b, %cond.true ], [ %c, %cond.false ] -; CHECK fsub float %a, [[PHI]] +; CHECK: [[PHI:%[^ ]*]] = phi float [ %b, %cond.true ], [ %c, %cond.false ] +; CHECK: fsub float %a, [[PHI]] cond.end: %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ] ret float %e @@ -60,8 +60,8 @@ br label %cond.end ; CHECK-LABEL: cond.end -; CHECK [[PHI:%[^ ]*]] = phi float [ %a, %cond.true ], [ %b, %cond.false ] -; CHECK fadd fast float %a, [[PHI]] +; CHECK: [[PHI:%[^ ]*]] = phi float [ %a, %cond.true ], [ %b, %cond.false ] +; CHECK: fadd fast float %a, [[PHI]] cond.end: %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ] ret float %e @@ -81,8 +81,8 @@ br label %cond.end ; CHECK-LABEL: cond.end -; CHECK [[PHI:%[^ ]*]] = phi float [ %a, %cond.true ], [ %b, %cond.false ] -; CHECK fadd float %a, [[PHI]] +; CHECK: [[PHI:%[^ ]*]] = phi float [ %a, %cond.true ], [ %b, %cond.false ] +; CHECK: fadd float %a, [[PHI]] cond.end: %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ] ret float %e diff --git a/llvm/test/Transforms/SampleProfile/gcc-simple.ll b/llvm/test/Transforms/SampleProfile/gcc-simple.ll --- a/llvm/test/Transforms/SampleProfile/gcc-simple.ll +++ b/llvm/test/Transforms/SampleProfile/gcc-simple.ll @@ -129,12 +129,12 @@ ret i32 %cond, !dbg !71 } -; CHECK ![[EC1]] = !{!"function_entry_count", i64 24108} -; CHECK ![[PROF1]] = !{!"branch_weights", i32 1, i32 30124} -; CHECK ![[PROF2]] = !{!"branch_weights", i32 30177, i32 29579} -; CHECK ![[EC2]] = !{!"function_entry_count", i64 0} -; CHECK ![[PROF3]] = !{!"branch_weights", i32 1, i32 1} -; CHECK ![[PROF4]] = !{!"branch_weights", i32 1, i32 20238} +; CHECK: ![[EC1]] = !{!"function_entry_count", i64 24108} +; CHECK: ![[PROF1]] = !{!"branch_weights", i32 1, i32 30124} +; CHECK: ![[PROF2]] = !{!"branch_weights", i32 30177, i32 29579} +; CHECK: ![[EC2]] = !{!"function_entry_count", i64 0} +; CHECK: ![[PROF3]] = !{!"branch_weights", i32 1, i32 1} +; CHECK: ![[PROF4]] = !{!"branch_weights", i32 1, i32 20238} attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/tools/dsymutil/X86/modules.m b/llvm/test/tools/dsymutil/X86/modules.m --- a/llvm/test/tools/dsymutil/X86/modules.m +++ b/llvm/test/tools/dsymutil/X86/modules.m @@ -117,7 +117,7 @@ // // CHECK: 0x{{0*}}[[PTR]]: DW_TAG_pointer_type // FIXME: The next line doesn't work. -// CHECK-NEXT DW_AT_type [DW_FORM_ref_addr] {0x{{0*}}[[INTERFACE]] +// CHECK-NEXT: DW_AT_type [DW_FORM_ref_addr] {0x{{0*}}[[INTERFACE]] extern int odr_violation; @import Foo;