[llvm] Fix missing FileCheck directive colons

[jhenderson]

llvm/test/CodeGen/PowerPC/spe.ll

46

I'm not sure I follow why it's safe to remove the lines from this test?

llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll

154

Are you sure this line should be removed?

llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll

318

Are you sure this line should be removed?

llvm/test/CodeGen/X86/avx-vzeroupper.ll

86

Any thoughts on why this line is here, and why it is safe to remove (i.e. instead of fixing)?

[jroelofs]

I suppose I should have separated out the trivial ones from these that took a bit more reasoning to confirm.

llvm/test/CodeGen/PowerPC/spe.ll

46

Have a look at the patch that added them in the first place: d52990c71b6f83c9beeba4efc9103412e0416ba9

They can't have been correct then, since PPC doesn't use @s as a label prefix, but they were pretty clearly intended to mark the beginning of the function. Later on in a51c61ea332f89dfbb9f3b3498c37b2efc99e13b, the test got reworked with utils/update_llc_test_checks.py, which didn't know to delete them.

llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll

154

That label can't appear twice in the ASM, and it's already matched above on line 36.

llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll

318

This one came from a8ba572dcfdb969fe1bb3381663298488891f838, and the subsequent rewrite in 347921a28157daf87acfcb31ce4787a46bd7ad12 is what left it in the wrong place breaking it further.

llvm/test/CodeGen/X86/avx-vzeroupper.ll

86

This one wasn't correct when it got added in b2b6a54f847f33f821f41e3e82bf3b86e08817a0, as that block label was already matched by another check a few lines earlier in the test.

[tra]

LGTM for NVPTX tests.

[jroelofs]

Rebased

[jhenderson]

I'm not sure if it was intended, but the addition of colons in the original version of the patch to llvm/test/Transforms/LoopStrengthReduce/X86/lsr-insns-2.ll seem to have disappeared in the rebase. Otherwise, looks good to me.

[jroelofs]

In D77352#1963084, @jhenderson wrote:

I'm not sure if it was intended, but the addition of colons in the original version of the patch to llvm/test/Transforms/LoopStrengthReduce/X86/lsr-insns-2.ll seem to have disappeared in the rebase. Otherwise, looks good to me.

Those got fixed by Simon in 396b1ee0e0b0c80484095a33daed7b53e701b090

[jroelofs]

7c5d2bec762550d305018de4292470c12015ecb5

[MaskRay]

Hi Jonathan,

If you included Differential Revision: https://reviews.llvm.org/D77352 in the git description, the differential would be closed automatically when the commit landed in master.

Many people agree that the commit description should include Reviewed-By: (not a strict rule). You can find plenty of examples in the history.

llvm/test/Analysis/AliasSet/saturation.ll

define void @allmust() {
   %d = alloca i32
   store i32 1, i32* %a
   store i32 2, i32* %b
   store i32 3, i32* %c
   store i32 4, i32* %d
   ret void
 }
 
-; CHECK-LABEL :'mergemay'
+; CHECK-LABEL: 'mergemay'
 ; NOSAT: AliasSet[{{.*}}, 2] may alias, Mod Pointers: (i32* %a, LocationSize::precise(4)), (i32* %a1, LocationSize::precise(4))
 ; NOSAT: AliasSet[{{.*}}, 1] must alias, Mod Pointers: (i32* %b, LocationSize::precise(4))
 ; SAT: AliasSet[{{.*}}, 2] may alias, Mod forwarding to 0x[[FWD:[0-9a-f]*]]
 ; SAT: AliasSet[{{.*}}, 1] must alias, Mod forwarding to 0x[[FWD]]
 ; SAT: AliasSet[0x[[FWD]], 2] may alias, Mod/Ref Pointers: (i32* %a, LocationSize::precise(4)), (i32* %a1, LocationSize::precise(4)), (i32* %b, LocationSize::precise(4))
 define void @mergemay(i32 %k) {
   %a = alloca i32
   %b = alloca i32

llvm/test/Analysis/CostModel/AMDGPU/fmul.ll

 ; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -mattr=+half-rate-64-ops < %s | FileCheck -check-prefixes=FASTF64,FASTF16,ALL %s
 ; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mattr=-half-rate-64-ops < %s | FileCheck -check-prefixes=SLOWF64,SLOWF16,ALL %s
 ; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -mattr=+half-rate-64-ops < %s | FileCheck -check-prefixes=FASTF64,FASTF16,ALL %s
 ; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa -mattr=-half-rate-64-ops < %s | FileCheck -check-prefixes=SLOWF64,SLOWF16,ALL %s
 
-; ALL: 'fmul_f32'
+; ALL-LABEL: 'fmul_f32'
 ; ALL: estimated cost of 1 for {{.*}} fmul float
 define amdgpu_kernel void @fmul_f32(float addrspace(1)* %out, float addrspace(1)* %vaddr, float %b) #0 {
   %vec = load float, float addrspace(1)* %vaddr
   %add = fmul float %vec, %b
   store float %add, float addrspace(1)* %out
   ret void
 }
 
-; ALL: 'fmul_v2f32'
+; ALL-LABEL: 'fmul_v2f32'
 ; ALL: estimated cost of 2 for {{.*}} fmul <2 x float>
 define amdgpu_kernel void @fmul_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %vaddr, <2 x float> %b) #0 {
   %vec = load <2 x float>, <2 x float> addrspace(1)* %vaddr
   %add = fmul <2 x float> %vec, %b
   store <2 x float> %add, <2 x float> addrspace(1)* %out
   ret void
 }
 
-; ALL: 'fmul_v3f32'
+; ALL-LABEL: 'fmul_v3f32'
 ; Allow for 4 when v3f32 is illegal and TargetLowering thinks it needs widening,
 ; and 3 when it is legal.
 ; ALL: estimated cost of {{[34]}} for {{.*}} fmul <3 x float>
 define amdgpu_kernel void @fmul_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %vaddr, <3 x float> %b) #0 {
   %vec = load <3 x float>, <3 x float> addrspace(1)* %vaddr
   %add = fmul <3 x float> %vec, %b
   store <3 x float> %add, <3 x float> addrspace(1)* %out
   ret void
 }
 
-; ALL: 'fmul_v5f32'
+; ALL-LABEL: 'fmul_v5f32'
 ; Allow for 8 when v5f32 is illegal and TargetLowering thinks it needs widening,
 ; and 5 when it is legal.
 ; ALL: estimated cost of {{[58]}} for {{.*}} fmul <5 x float>
 define amdgpu_kernel void @fmul_v5f32(<5 x float> addrspace(1)* %out, <5 x float> addrspace(1)* %vaddr, <5 x float> %b) #0 {
   %vec = load <5 x float>, <5 x float> addrspace(1)* %vaddr
   %add = fmul <5 x float> %vec, %b
   store <5 x float> %add, <5 x float> addrspace(1)* %out
   ret void
 }
 
-; ALL: 'fmul_f64'
+; ALL-LABEL: 'fmul_f64'
 ; FASTF64: estimated cost of 2 for {{.*}} fmul double
 ; SLOWF64: estimated cost of 3 for {{.*}} fmul double
 define amdgpu_kernel void @fmul_f64(double addrspace(1)* %out, double addrspace(1)* %vaddr, double %b) #0 {
   %vec = load double, double addrspace(1)* %vaddr
   %add = fmul double %vec, %b
   store double %add, double addrspace(1)* %out
   ret void
 }
 
-; ALL: 'fmul_v2f64'
+; ALL-LABEL: 'fmul_v2f64'
 ; FASTF64: estimated cost of 4 for {{.*}} fmul <2 x double>
 ; SLOWF64: estimated cost of 6 for {{.*}} fmul <2 x double>
 define amdgpu_kernel void @fmul_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %vaddr, <2 x double> %b) #0 {
   %vec = load <2 x double>, <2 x double> addrspace(1)* %vaddr
   %add = fmul <2 x double> %vec, %b
   store <2 x double> %add, <2 x double> addrspace(1)* %out
   ret void
 }
 
-; ALL: 'fmul_v3f64'
+; ALL-LABEL: 'fmul_v3f64'
 ; FASTF64: estimated cost of 6 for {{.*}} fmul <3 x double>
 ; SLOWF64: estimated cost of 9 for {{.*}} fmul <3 x double>
 define amdgpu_kernel void @fmul_v3f64(<3 x double> addrspace(1)* %out, <3 x double> addrspace(1)* %vaddr, <3 x double> %b) #0 {
   %vec = load <3 x double>, <3 x double> addrspace(1)* %vaddr
   %add = fmul <3 x double> %vec, %b
   store <3 x double> %add, <3 x double> addrspace(1)* %out
   ret void
 }
 
-; ALL: 'fmul_f16'
+; ALL-LABEL: 'fmul_f16'
 ; ALL: estimated cost of 1 for {{.*}} fmul half
 define amdgpu_kernel void @fmul_f16(half addrspace(1)* %out, half addrspace(1)* %vaddr, half %b) #0 {
   %vec = load half, half addrspace(1)* %vaddr
   %add = fmul half %vec, %b
   store half %add, half addrspace(1)* %out
   ret void
 }
 
-; ALL: 'fmul_v2f16'
-; SLOWF16 estimated cost of 2 for {{.*}} fmul <2 x half>
-; FASTF16 estimated cost of 1 for {{.*}} fmul <2 x half>
+; ALL-LABEL: 'fmul_v2f16'
+; SLOWF16: estimated cost of 2 for {{.*}} fmul <2 x half>
+; FASTF16: estimated cost of 1 for {{.*}} fmul <2 x half>
 define amdgpu_kernel void @fmul_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %vaddr, <2 x half> %b) #0 {
   %vec = load <2 x half>, <2 x half> addrspace(1)* %vaddr
   %add = fmul <2 x half> %vec, %b
   store <2 x half> %add, <2 x half> addrspace(1)* %out
   ret void
 }
 
-; ALL: 'fmul_v3f16'
-; SLOWF16 estimated cost of 4 for {{.*}} fmul <3 x half>
-; FASTF16 estimated cost of 2 for {{.*}} fmul <3 x half>
+; ALL-LABEL: 'fmul_v3f16'
+; SLOWF16: estimated cost of 4 for {{.*}} fmul <3 x half>
+; FASTF16: estimated cost of 2 for {{.*}} fmul <3 x half>
 define amdgpu_kernel void @fmul_v3f16(<3 x half> addrspace(1)* %out, <3 x half> addrspace(1)* %vaddr, <3 x half> %b) #0 {
   %vec = load <3 x half>, <3 x half> addrspace(1)* %vaddr
   %add = fmul <3 x half> %vec, %b
   store <3 x half> %add, <3 x half> addrspace(1)* %out
   ret void
 }
 
-; ALL: 'fmul_v4f16'
+; ALL-LABEL: 'fmul_v4f16'
 ; SLOWF16: estimated cost of 4 for {{.*}} fmul <4 x half>
 ; FASTF16: estimated cost of 2 for {{.*}} fmul <4 x half>
 define amdgpu_kernel void @fmul_v4f16(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %vaddr, <4 x half> %b) #0 {
   %vec = load <4 x half>, <4 x half> addrspace(1)* %vaddr
   %add = fmul <4 x half> %vec, %b
   store <4 x half> %add, <4 x half> addrspace(1)* %out
   ret void
 }
 
 attributes #0 = { nounwind }

llvm/test/Analysis/MemorySSA/volatile-clobber.ll

 ; CHECK: 4 = MemoryDef(3)
 ; CHECK-NEXT: %3 = load volatile i32
   %3 = load volatile i32, i32* %1, align 4
   %4 = add i32 %3, %2
   ret i32 %4
 }
 
 ; Ensuring we allow hoisting nonvolatile loads around volatile loads.
-; CHECK-LABEL define void @volatile_only
+; CHECK-LABEL: define void @volatile_only
 define void @volatile_only(i32* %arg1, i32* %arg2) {
   ; Trivially NoAlias/MustAlias
   %a = alloca i32
   %b = alloca i32
 
 ; CHECK: 1 = MemoryDef(liveOnEntry)
 ; CHECK-NEXT: load volatile i32, i32* %a
   load volatile i32, i32* %a

 ; CHECK: MemoryUse(liveOnEntry)
 ; CHECK-NEXT: load i32, i32* %arg2
   load i32, i32* %arg2
 
   ret void
 }
 
 ; Ensuring that volatile atomic operations work properly.
-; CHECK-LABEL define void @volatile_atomics
+; CHECK-LABEL: define void @volatile_atomics
 define void @volatile_atomics(i32* %arg1, i32* %arg2) {
   %a = alloca i32
   %b = alloca i32
 
  ; Trivially NoAlias/MustAlias
 
 ; CHECK: 1 = MemoryDef(liveOnEntry)
 ; CHECK-NEXT: load atomic volatile i32, i32* %a acquire, align 4

llvm/test/Analysis/ValueTracking/known-nonnull-at.ll

 
 define i32 @test_null_after_load_addrspace(i32 addrspace(1)* %0) {
 ; CHECK-LABEL: @test_null_after_load_addrspace(
 ; CHECK-NEXT:    [[TMP2:%.*]] = load i32, i32 addrspace(1)* [[TMP0:%.*]], align 4
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 addrspace(1)* [[TMP0]], null
 ; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 1
 ; CHECK-NEXT:    ret i32 [[TMP4]]
 ;
-; CHECK-NEXT     ret i32 %4
   %2 = load i32, i32 addrspace(1)* %0, align 4
   %3 = icmp eq i32 addrspace(1)* %0, null
   %4 = select i1 %3, i32 %2, i32 1
   ret i32 %4
 }
 
 ; Make sure if store happened after the check, nullptr check is not removed.
 

llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll

 ; CHECK: trunc i64 [[popc]] to i32
   %r6 = call i32 @llvm.nvvm.popc.ll(i64 %b)
 
 ; CHECK: call float @llvm.convert.from.fp16.f32(i16 %c)
   %r7 = call float @llvm.nvvm.h2f(i16 %c)
   ret void
 }
 
-; CHECK-LABEL @abs
+; CHECK-LABEL: @abs
 define void @abs(i32 %a, i64 %b) {
 ; CHECK-DAG: [[negi:%[a-zA-Z0-9.]+]] = sub i32 0, %a
 ; CHECK-DAG: [[cmpi:%[a-zA-Z0-9.]+]] = icmp sge i32 %a, 0
 ; CHECK: select i1 [[cmpi]], i32 %a, i32 [[negi]]
   %r1 = call i32 @llvm.nvvm.abs.i(i32 %a)
 
 ; CHECK-DAG: [[negll:%[a-zA-Z0-9.]+]] = sub i64 0, %b
 ; CHECK-DAG: [[cmpll:%[a-zA-Z0-9.]+]] = icmp sge i64 %b, 0

llvm/test/Assembler/immarg-param-attribute.ll

 ; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
 
 ; CHECK: declare void @llvm.test.immarg.intrinsic.i32(i32 immarg)
 declare void @llvm.test.immarg.intrinsic.i32(i32 immarg)
 
 ; CHECK: declare void @llvm.test.immarg.intrinsic.f32(float immarg)
 declare void @llvm.test.immarg.intrinsic.f32(float immarg)
 
 ; CHECK-LABEL: @call_llvm.test.immarg.intrinsic.i32(
 define void @call_llvm.test.immarg.intrinsic.i32() {
   ; CHECK: call void @llvm.test.immarg.intrinsic.i32(i32 0)
   call void @llvm.test.immarg.intrinsic.i32(i32 0)
 
   ; CHECK: call void @llvm.test.immarg.intrinsic.i32(i32 0)
   call void @llvm.test.immarg.intrinsic.i32(i32 0)
 
-  ; CHECK call void @llvm.test.immarg.intrinsic.i32(i32 1)
+  ; CHECK: call void @llvm.test.immarg.intrinsic.i32(i32 1)
   call void @llvm.test.immarg.intrinsic.i32(i32 1)
 
   ; CHECK: call void @llvm.test.immarg.intrinsic.i32(i32 5)
   call void @llvm.test.immarg.intrinsic.i32(i32 add (i32 2, i32 3))
 
   ; CHECK: call void @llvm.test.immarg.intrinsic.i32(i32 0)
   call void @llvm.test.immarg.intrinsic.i32(i32 ptrtoint (i32* null to i32))
   ret void

llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll

 ; tests for vXiYY_indexed in SIMDIndexedSQRDMLxHSDTied
 
 define <4 x i16> @test_sqrdmlah_lane_s16(<4 x i16> %acc, <4 x i16> %x, <4 x i16> %v) {
 ; CHECK-LABEL: test_sqrdmlah_lane_s16:
 entry:
   %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
   %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %x, <4 x i16> %shuffle)
   %retval =  call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %acc, <4 x i16> %prod)
-; CHECK-V8a :       sqrdmulh    v1.4h, v1.4h, v2.h[3]
+; CHECK-V8a:        sqrdmulh    v1.4h, v1.4h, v2.h[3]
 ; CHECK-V81a:       sqrdmlah    v0.4h, v1.4h, v2.h[3]
 ; CHECK-V81a-apple: sqrdmlah.4h v0,    v1,    v2[3]
   ret <4 x i16> %retval
 }
 
 define <8 x i16> @test_sqrdmlahq_lane_s16(<8 x i16> %acc, <8 x i16> %x, <8 x i16> %v) {
 ; CHECK-LABEL: test_sqrdmlahq_lane_s16:
 entry:

llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll

define %v4f32 @test_v4f32.fabs(%v4f32 %a) {
   ret %v4f32 %1
 }
 
 ; FALLBACK-NOT: remark{{.*}}test_v4f32.floor
 ; CHECK: test_v4f32.floor:
 ; GISEL: test_v4f32.floor:
 define %v4f32 @test_v4f32.floor(%v4f32 %a) {
   ; CHECK: frintm.4s
-  ; GISEL frintm.4s
+  ; GISEL: frintm.4s
   %1 = call %v4f32 @llvm.floor.v4f32(%v4f32 %a)
   ret %v4f32 %1
 }
 ; CHECK: test_v4f32.ceil:
 ; FALLBACK-NOT: remark{{.*}}test_v4f32.ceil
 ; GISEL-LABEL: test_v4f32.ceil:
 define %v4f32 @test_v4f32.ceil(%v4f32 %a) {
   ; CHECK: frintp.4s

llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll

 ; RUN: llc -mtriple=aarch64-linux %s               -o - | \
 ; RUN:   FileCheck %s --check-prefix=ASM
 ; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - |  \
 ; RUN:   llvm-readelf --notes | FileCheck %s --check-prefix=OBJ
 @x = common dso_local global i32 0, align 4
 
 attributes #0 = { "branch-target-enforcement" }
 
 ; Both attributes present in a file with no functions.
 ; ASM:      .word 3221225472
 ; ASM-NEXT: .word 4
-; ASM-NEXT  .word 3
+; ASM-NEXT: .word 3
 
 ; OBJ: Properties: aarch64 feature: BTI, PAC

llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-1.ll

 ; RUN: llc -mtriple=aarch64-linux %s               -o - | \
 ; RUN:   FileCheck %s --check-prefix=ASM
 ; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - |  \
 ; RUN:   llvm-readelf --notes | FileCheck %s --check-prefix=OBJ
 
 define dso_local i32 @f() #0 {
 entry:
   ret i32 0
 }
 
 attributes #0 = { "branch-target-enforcement" }
 
 ; BTI attribute present
 ; ASM:      .word 3221225472
 ; ASM-NEXT: .word 4
-; ASM-NEXT  .word 1
+; ASM-NEXT: .word 1
 
 ; OBJ: Properties: aarch64 feature: BTI

llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll

 ; RUN: llc -mtriple=aarch64-linux %s               -o - | \
 ; RUN:   FileCheck %s --check-prefix=ASM
 ; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - |  \
 ; RUN:   llvm-readelf --notes | FileCheck %s --check-prefix=OBJ
 
 define dso_local i32 @f() #0 {
 entry:
   ret i32 0
 }
 
 attributes #0 = { "sign-return-address"="all" }
 
 ; PAC attribute present
 ; ASM:      .word 3221225472
 ; ASM-NEXT: .word 4
-; ASM-NEXT  .word 2
+; ASM-NEXT: .word 2
 
 ; OBJ: Properties: aarch64 feature: PAC

llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll

 ; RUN: llc -mtriple=aarch64-linux %s               -o - | \
 ; RUN:   FileCheck %s --check-prefix=ASM
 ; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - |  \
 ; RUN:   llvm-readelf --notes | FileCheck %s --check-prefix=OBJ
 
 define dso_local i32 @f() #0 {
 entry:
   ret i32 0
 }
 
 attributes #0 = { "branch-target-enforcement" "sign-return-address"="non-leaf" }
 
 ; Both attribute present
 ; ASM:      .word 3221225472
 ; ASM-NEXT: .word 4
-; ASM-NEXT  .word 3
+; ASM-NEXT: .word 3
 
 ; OBJ: Properties: aarch64 feature: BTI, PAC

llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll

 
 attributes #0 = { "branch-target-enforcement" "sign-return-address"="non-leaf" }
 
 attributes #1 = { "branch-target-enforcement" }
 
 ; Only the common atttribute (BTI)
 ; ASM:      .word 3221225472
 ; ASM-NEXT: .word 4
-; ASM-NEXT  .word 1
+; ASM-NEXT: .word 1
 
 ; OBJ: Properties: aarch64 feature: BTI

llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll

 attributes #0 = { "branch-target-enforcement" "sign-return-address"="non-leaf" }
 
 attributes #1 = { "sign-return-address"="all" }
 
 ; Only the common atttribute (PAC)
 ; ASM: warning: not setting BTI in feature flags
 ; ASM:      .word 3221225472
 ; ASM-NEXT: .word 4
-; ASM-NEXT  .word 2
+; ASM-NEXT: .word 2
 
 ; OBJ: Properties: aarch64 feature: PAC

llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll

 
 declare dso_local i32 @g()
 
 attributes #0 = { "branch-target-enforcement" }
 
 ; Declarations don't prevent setting BTI
 ; ASM:      .word 3221225472
 ; ASM-NEXT: .word 4
-; ASM-NEXT  .word 1
+; ASM-NEXT: .word 1
 
 ; OBJ: Properties: aarch64 feature: BTI

llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

bb.0:
     STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
     renamable $x8 = MRS 55840
     STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
     RET undef $lr
 
 ...
 ---
 # CHECK-LABEL: name: test6
-# CHECK-LABEL  bb.0:
+# CHECK-LABEL: bb.0:
 # CHECK:    liveins: $x0, $x1, $q3
 
 # CHECK:         renamable $q9 = LDRQui $x0, 0 :: (load 16)
 # CHECK-NEXT:    renamable $q9 = XTNv8i16 renamable $q9, killed renamable $q3
 # CHECK-NEXT:    STRQui renamable $q9, renamable $x0, 11 :: (store 16, align 4)
 # CHECK-NEXT:    renamable $q9 = FADDv2f64 renamable $q9, renamable $q9
 # CHECK-NEXT:    STRQui renamable $q9, renamable $x0, 10 :: (store 16, align 4)
 # CHECK-NEXT:    RET undef $lr
bb.0:
     RET undef $lr
 
 ...
 ---
 # The reg class returned for $q9 contains only the first 16 Q registers.
 # TODO: Can we check that all instructions that require renaming also support
 #       the second 16 Q registers?
 # CHECK-LABEL: name: test9
-# CHECK-LABEL  bb.0:
+# CHECK-LABEL: bb.0:
 # CHECK:    liveins: $x0, $x1, $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
 
 # CHECK:         renamable $q9 = LDRQui $x0, 0 :: (load 16)
 # CHECK-NEXT:    STRQui killed renamable $q9, renamable $x0, 10 :: (store 16, align 4)
 # CHECK:         renamable $q9 = LDRQui $x0, 1 :: (load 16)
 # CHECK-NEXT:    STRQui renamable $q9, renamable $x0, 11 :: (store 16, align 4)
 # CHECK-NEXT:    RET undef $lr
 
bb.0:
     renamable $q9 = LDRQui $x0, 1 :: (load 16)
     STRQui renamable $q9, renamable $x0, 11 :: (store 16, align 4)
     RET undef $lr
 
 ...
 ---
 # The livein $q7 is killed early, so we can re-use it for renaming.
 # CHECK-LABEL: name: test10
-# CHECK-LABEL  bb.0:
+# CHECK-LABEL: bb.0:
 # CHECK:    liveins: $x0, $x1, $q0, $q1, $q2, $q3, $q4, $q5, $q6, $q7
 
 # CHECK:         renamable $q7 = FADDv2f64 renamable $q7, renamable $q7
 # CHECK-NEXT:    STRQui killed renamable $q7, renamable $x0, 100 :: (store 16, align 4)
 # CHECK-NEXT:    $q7 = LDRQui $x0, 0 :: (load 16)
 # CHECK-NEXT:    renamable $q9 = LDRQui $x0, 1 :: (load 16)
 # CHECK-NEXT:    STPQi killed renamable $q9, killed $q7, renamable $x0, 10 :: (store 16, align 4)
 # CHECK-NEXT:    RET undef $lr

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll

 ; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA  %s
 ; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA  %s
 ; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=SI-MESA %s
 ; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=VI-MESA %s
 ; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s
 ; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s
 
 declare i32 @llvm.amdgcn.workgroup.id.x() #0
 declare i32 @llvm.amdgcn.workgroup.id.y() #0
 declare i32 @llvm.amdgcn.workgroup.id.z() #0
 
-; ALL-LABEL {{^}}test_workgroup_id_x:
+; ALL-LABEL: {{^}}test_workgroup_id_x:
 
 ; CO-V2: .amd_kernel_code_t
 ; CO-V2: user_sgpr_count = 6
 ; CO-V2: enable_sgpr_workgroup_id_x = 1
 ; CO-V2: enable_sgpr_workgroup_id_y = 0
 ; CO-V2: enable_sgpr_workgroup_id_z = 0
 ; CO-V2: enable_sgpr_workgroup_info = 0
 ; CO-V2: enable_vgpr_workitem_id = 0

 ; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
 ; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
 define amdgpu_kernel void @test_workgroup_id_x(i32 addrspace(1)* %out) #1 {
   %id = call i32 @llvm.amdgcn.workgroup.id.x()
   store i32 %id, i32 addrspace(1)* %out
   ret void
 }
 
-; ALL-LABEL {{^}}test_workgroup_id_y:
+; ALL-LABEL: {{^}}test_workgroup_id_y:
 ; CO-V2: user_sgpr_count = 6
 ; CO-V2: enable_sgpr_workgroup_id_x = 1
 ; CO-V2: enable_sgpr_workgroup_id_y = 1
 ; CO-V2: enable_sgpr_workgroup_id_z = 0
 ; CO-V2: enable_sgpr_workgroup_info = 0
 ; CO-V2: enable_sgpr_grid_workgroup_count_x = 0
 ; CO-V2: enable_sgpr_grid_workgroup_count_y = 0
 ; CO-V2: enable_sgpr_grid_workgroup_count_z = 0

 ; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
 ; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
 define amdgpu_kernel void @test_workgroup_id_y(i32 addrspace(1)* %out) #1 {
   %id = call i32 @llvm.amdgcn.workgroup.id.y()
   store i32 %id, i32 addrspace(1)* %out
   ret void
 }
 
-; ALL-LABEL {{^}}test_workgroup_id_z:
+; ALL-LABEL: {{^}}test_workgroup_id_z:
 ; CO-V2: user_sgpr_count = 6
 ; CO-V2: enable_sgpr_workgroup_id_x = 1
 ; CO-V2: enable_sgpr_workgroup_id_y = 0
 ; CO-V2: enable_sgpr_workgroup_id_z = 1
 ; CO-V2: enable_sgpr_workgroup_info = 0
 ; CO-V2: enable_vgpr_workitem_id = 0
 ; CO-V2: enable_sgpr_private_segment_buffer = 1
 ; CO-V2: enable_sgpr_dispatch_ptr = 0

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll

 ; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA  %s
 ; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA  %s
 ; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=hawaii -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=SI-MESA %s
 ; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tonga -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=VI-MESA %s
 ; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=+flat-for-global,-code-object-v3 -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s
 ; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s
 
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 declare i32 @llvm.amdgcn.workitem.id.y() #0
 declare i32 @llvm.amdgcn.workitem.id.z() #0
 
 ; MESA: .section .AMDGPU.config
 ; MESA: .long 47180
 ; MESA-NEXT: .long 132{{$}}
 
-; ALL-LABEL {{^}}test_workitem_id_x:
+; ALL-LABEL: {{^}}test_workitem_id_x:
 ; CO-V2: enable_vgpr_workitem_id = 0
 
 ; ALL-NOT: v0
 ; ALL: {{buffer|flat}}_store_dword {{.*}}v0
 define amdgpu_kernel void @test_workitem_id_x(i32 addrspace(1)* %out) #1 {
   %id = call i32 @llvm.amdgcn.workitem.id.x()
   store i32 %id, i32 addrspace(1)* %out
   ret void
 }
 
 ; MESA: .section .AMDGPU.config
 ; MESA: .long 47180
 ; MESA-NEXT: .long 2180{{$}}
 
-; ALL-LABEL {{^}}test_workitem_id_y:
+; ALL-LABEL: {{^}}test_workitem_id_y:
 ; CO-V2: enable_vgpr_workitem_id = 1
 
 ; ALL-NOT: v1
 ; ALL: {{buffer|flat}}_store_dword {{.*}}v1
 define amdgpu_kernel void @test_workitem_id_y(i32 addrspace(1)* %out) #1 {
   %id = call i32 @llvm.amdgcn.workitem.id.y()
   store i32 %id, i32 addrspace(1)* %out
   ret void
 }
 
 ; MESA: .section .AMDGPU.config
 ; MESA: .long 47180
 ; MESA-NEXT: .long 4228{{$}}
 
-; ALL-LABEL {{^}}test_workitem_id_z:
+; ALL-LABEL: {{^}}test_workitem_id_z:
 ; CO-V2: enable_vgpr_workitem_id = 2
 
 ; ALL-NOT: v2
 ; ALL: {{buffer|flat}}_store_dword {{.*}}v2
 define amdgpu_kernel void @test_workitem_id_z(i32 addrspace(1)* %out) #1 {
   %id = call i32 @llvm.amdgcn.workitem.id.z()
   store i32 %id, i32 addrspace(1)* %out
   ret void

llvm/test/CodeGen/AMDGPU/branch-relaxation.ll

 
 ; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %loop
 ; GCN-NEXT: ; in Loop: Header=[[LOOP]] Depth=1
 
 ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
 ; GCN-NEXT: s_sub_u32 s[[PC_LO]], s[[PC_LO]], ([[LONGBB]]+4)-[[LOOP]]
 ; GCN-NEXT: s_subb_u32 s[[PC_HI]], s[[PC_HI]], 0{{$}}
 ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
-; GCN-NEXT .Lfunc_end{{[0-9]+}}:
+; GCN-NEXT: .Lfunc_end{{[0-9]+}}:
 define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(i32 addrspace(1)* %arg, i32 %arg1) {
 entry:
   br label %loop
 
 loop:
   ; 32 byte asm
   call void asm sideeffect
    "v_nop_e64

llvm/test/CodeGen/AMDGPU/call-argument-types.ll

 }
 
 ; GCN-LABEL: {{^}}test_call_external_void_func_v5i32_imm:
 ; GCN-DAG: v_mov_b32_e32 v0, 1
 ; GCN-DAG: v_mov_b32_e32 v1, 2
 ; GCN-DAG: v_mov_b32_e32 v2, 3
 ; GCN-DAG: v_mov_b32_e32 v3, 4
 ; GCN-DAG: v_mov_b32_e32 v4, 5
-; GCN-NOT v5,
+; GCN-NOT: v5,
 ; GCN: s_swappc_b64
 define amdgpu_kernel void @test_call_external_void_func_v5i32_imm() #0 {
   call void @external_void_func_v5i32(<5 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5>)
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_call_external_void_func_v8i32:
 ; GCN-DAG: buffer_load_dwordx4 v[0:3], off

llvm/test/CodeGen/AMDGPU/ds_read2.ll

define amdgpu_kernel void @simple_read2_f32_max_offset(float addrspace(1)* %out) #0 {
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
 
 ; GCN-LABEL: @simple_read2_f32_too_far
 ; CI-DAG: s_mov_b32 m0
 ; GFX9-NOT: m0
 
-; GCN-NOT ds_read2_b32
+; GCN-NOT: ds_read2_b32
 ; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}
 ; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:1028
 ; GCN: s_endpgm
 define amdgpu_kernel void @simple_read2_f32_too_far(float addrspace(1)* %out) #0 {
   %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
   %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
   %val0 = load float, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 257
define amdgpu_kernel void @read2_ptr_is_subreg_f32(float addrspace(1)* %out) #0 {
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
 
 ; GCN-LABEL: @simple_read2_f32_volatile_0
 ; CI-DAG: s_mov_b32 m0
 ; GFX9-NOT: m0
 
-; GCN-NOT ds_read2_b32
+; GCN-NOT: ds_read2_b32
 ; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}
 ; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:32
 ; GCN: s_endpgm
 define amdgpu_kernel void @simple_read2_f32_volatile_0(float addrspace(1)* %out) #0 {
   %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
   %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
   %val0 = load volatile float, float addrspace(3)* %arrayidx0, align 4
   %add.x = add nsw i32 %x.i, 8

llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll

define void @global_inst_offset(i32 addrspace(1)* nocapture %p) {
   %gep = getelementptr inbounds i32, i32 addrspace(1)* %p, i64 1
   %load = load i32, i32 addrspace(1)* %gep, align 4
   %inc = add nsw i32 %load, 1
   store i32 %inc, i32 addrspace(1)* %gep, align 4
   ret void
 }
 
 ; GCN-LABEL: load_i16_lo:
-; GFX9 : flat_load_short_d16 v{{[0-9]+}}, v[{{[0-9:]+}}] offset:8{{$}}
+; GFX9:  flat_load_short_d16 v{{[0-9]+}}, v[{{[0-9:]+}}] offset:8{{$}}
 ; GFX10: flat_load_short_d16 v{{[0-9]+}}, v[{{[0-9:]+}}]{{$}}
 define amdgpu_kernel void @load_i16_lo(i16* %arg, <2 x i16>* %out) {
   %gep = getelementptr inbounds i16, i16* %arg, i32 4
   %ld = load i16, i16* %gep, align 2
   %vec = insertelement <2 x i16> <i16 undef, i16 0>, i16 %ld, i32 0
   %v = add <2 x i16> %vec, %vec
   store <2 x i16> %v, <2 x i16>* %out, align 4
   ret void

llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll

 ; SI-FLUSH: buffer_store_dword [[R2]]
 ; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
 
 ; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
 
 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
 
-; SI-DENORM buffer_store_dword [[RESULT]]
+; SI-DENORM: buffer_store_dword [[RESULT]]
 ; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
 define amdgpu_kernel void @fmuladd_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
   %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
   %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
 
   %r1 = load volatile float, float addrspace(1)* %gep.0

llvm/test/CodeGen/AMDGPU/function-args.ll

 ; CI-DAG: buffer_load_dword [[LOAD_ARG4:v[0-9]+]], off, s[0:3], s32 offset:12{{$}}
 
 ; GCN-DAG: v_and_b32_e32 [[TRUNC_ARG1_I1:v[0-9]+]], 1, [[LOAD_ARG1]]
 ; CI-DAG: v_cvt_f16_f32_e32 [[CVT_ARG4:v[0-9]+]], [[LOAD_ARG4]]
 
 ; GCN: buffer_store_byte [[TRUNC_ARG1_I1]], off
 ; GCN: buffer_store_byte [[LOAD_ARG2]], off
 ; GCN: buffer_store_short [[LOAD_ARG3]], off
-; GFX89 buffer_store_short [[LOAD_ARG4]], off
+; GFX89: buffer_store_short [[LOAD_ARG4]], off
 
 ; CI: buffer_store_short [[CVT_ARG4]], off
 define void @void_func_v32i32_i1_i8_i16(<32 x i32> %arg0, i1 %arg1, i8 %arg2, i16 %arg3, half %arg4) #0 {
   store volatile <32 x i32> %arg0, <32 x i32> addrspace(1)* undef
   store volatile i1 %arg1, i1 addrspace(1)* undef
   store volatile i8 %arg2, i8 addrspace(1)* undef
   store volatile i16 %arg3, i16 addrspace(1)* undef
   store volatile half %arg4, half addrspace(1)* undef

llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll

 ; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v8i32 void (): illegal SGPR to VGPR copy
 ; GCN: ; illegal copy v[0:7] to s[8:15]
 define amdgpu_kernel void @illegal_vgpr_to_sgpr_copy_v8i32() #0 {
   %vgpr = call <8 x i32> asm sideeffect "; def $0", "=${v[0:7]}"()
   call void asm sideeffect "; use $0", "${s[8:15]}"(<8 x i32> %vgpr)
   ret void
 }
 
-; ERR error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v16i32 void (): illegal SGPR to VGPR copy
+; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v16i32 void (): illegal SGPR to VGPR copy
 ; GCN: ; illegal copy v[0:15] to s[16:31]
 define amdgpu_kernel void @illegal_vgpr_to_sgpr_copy_v16i32() #0 {
   %vgpr = call <16 x i32> asm sideeffect "; def $0", "=${v[0:15]}"()
   call void asm sideeffect "; use $0", "${s[16:31]}"(<16 x i32> %vgpr)
   ret void
 }
 
 ; ERR: error: <unknown>:0:0: in function illegal_agpr_to_sgpr_copy_i32 void (): illegal SGPR to VGPR copy

llvm/test/CodeGen/AMDGPU/insert-skip-from-vcc.mir

bb.2:
     $vcc = S_AND_B64 $exec, killed $sgpr0_sgpr1, implicit-def dead $scc
     S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
     S_ENDPGM 0
 ...
 ---
 # GCN-LABEL: name: and_execz_imm_vccz_liveout_scc
 # GCN:      $vcc = S_AND_B64 $exec, -1, implicit-def $scc
 # GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
-# GCN-NEXT  S_ENDPGM 0, implicit $scc
+# GCN-NEXT: S_ENDPGM 0, implicit $scc
 name:            and_execz_imm_vccz_liveout_scc
 body:             |
   bb.0:
     S_NOP 0
 
   bb.1:
     S_NOP 0
 

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll

 ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA  %s
 ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA  %s
 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=SI-MESA %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=VI-MESA %s
 ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s
 ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s
 
 declare i32 @llvm.amdgcn.workgroup.id.x() #0
 declare i32 @llvm.amdgcn.workgroup.id.y() #0
 declare i32 @llvm.amdgcn.workgroup.id.z() #0
 
-; ALL-LABEL {{^}}test_workgroup_id_x:
+; ALL-LABEL: {{^}}test_workgroup_id_x:
 
 ; CO-V2: .amd_kernel_code_t
 ; CO-V2: user_sgpr_count = 6
 ; CO-V2: enable_sgpr_workgroup_id_x = 1
 ; CO-V2: enable_sgpr_workgroup_id_y = 0
 ; CO-V2: enable_sgpr_workgroup_id_z = 0
 ; CO-V2: enable_sgpr_workgroup_info = 0
 ; CO-V2: enable_vgpr_workitem_id = 0

 ; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
 ; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
 define amdgpu_kernel void @test_workgroup_id_x(i32 addrspace(1)* %out) #1 {
   %id = call i32 @llvm.amdgcn.workgroup.id.x()
   store i32 %id, i32 addrspace(1)* %out
   ret void
 }
 
-; ALL-LABEL {{^}}test_workgroup_id_y:
+; ALL-LABEL: {{^}}test_workgroup_id_y:
 ; CO-V2: user_sgpr_count = 6
 ; CO-V2: enable_sgpr_workgroup_id_x = 1
 ; CO-V2: enable_sgpr_workgroup_id_y = 1
 ; CO-V2: enable_sgpr_workgroup_id_z = 0
 ; CO-V2: enable_sgpr_workgroup_info = 0
 ; CO-V2: enable_sgpr_grid_workgroup_count_x = 0
 ; CO-V2: enable_sgpr_grid_workgroup_count_y = 0
 ; CO-V2: enable_sgpr_grid_workgroup_count_z = 0

 ; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
 ; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
 define amdgpu_kernel void @test_workgroup_id_y(i32 addrspace(1)* %out) #1 {
   %id = call i32 @llvm.amdgcn.workgroup.id.y()
   store i32 %id, i32 addrspace(1)* %out
   ret void
 }
 
-; ALL-LABEL {{^}}test_workgroup_id_z:
+; ALL-LABEL: {{^}}test_workgroup_id_z:
 ; CO-V2: user_sgpr_count = 6
 ; CO-V2: enable_sgpr_workgroup_id_x = 1
 ; CO-V2: enable_sgpr_workgroup_id_y = 0
 ; CO-V2: enable_sgpr_workgroup_id_z = 1
 ; CO-V2: enable_sgpr_workgroup_info = 0
 ; CO-V2: enable_vgpr_workitem_id = 0
 ; CO-V2: enable_sgpr_private_segment_buffer = 1
 ; CO-V2: enable_sgpr_dispatch_ptr = 0

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll

 ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA  %s
 ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=carrizo -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA  %s
 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=SI-MESA %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=VI-MESA %s
 ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s
 ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s
 
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 declare i32 @llvm.amdgcn.workitem.id.y() #0
 declare i32 @llvm.amdgcn.workitem.id.z() #0
 
 ; MESA: .section .AMDGPU.config
 ; MESA: .long 47180
 ; MESA-NEXT: .long 132{{$}}
 
-; ALL-LABEL {{^}}test_workitem_id_x:
+; ALL-LABEL: {{^}}test_workitem_id_x:
 ; CO-V2: enable_vgpr_workitem_id = 0
 
 ; ALL-NOT: v0
 ; ALL: {{buffer|flat}}_store_dword {{.*}}v0
 define amdgpu_kernel void @test_workitem_id_x(i32 addrspace(1)* %out) #1 {
   %id = call i32 @llvm.amdgcn.workitem.id.x()
   store i32 %id, i32 addrspace(1)* %out
   ret void
 }
 
 ; MESA: .section .AMDGPU.config
 ; MESA: .long 47180
 ; MESA-NEXT: .long 2180{{$}}
 
-; ALL-LABEL {{^}}test_workitem_id_y:
+; ALL-LABEL: {{^}}test_workitem_id_y:
 ; CO-V2: enable_vgpr_workitem_id = 1
 
 ; ALL-NOT: v1
 ; ALL: {{buffer|flat}}_store_dword {{.*}}v1
 define amdgpu_kernel void @test_workitem_id_y(i32 addrspace(1)* %out) #1 {
   %id = call i32 @llvm.amdgcn.workitem.id.y()
   store i32 %id, i32 addrspace(1)* %out
   ret void
 }
 
 ; MESA: .section .AMDGPU.config
 ; MESA: .long 47180
 ; MESA-NEXT: .long 4228{{$}}
 
-; ALL-LABEL {{^}}test_workitem_id_z:
+; ALL-LABEL: {{^}}test_workitem_id_z:
 ; CO-V2: enable_vgpr_workitem_id = 2
 
 ; ALL-NOT: v2
 ; ALL: {{buffer|flat}}_store_dword {{.*}}v2
 define amdgpu_kernel void @test_workitem_id_z(i32 addrspace(1)* %out) #1 {
   %id = call i32 @llvm.amdgcn.workitem.id.z()
   store i32 %id, i32 addrspace(1)* %out
   ret void
 }
 
 attributes #0 = { nounwind readnone }
 attributes #1 = { nounwind }

llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll

 ; SI:  v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[C_F32]]
 ; SI:  buffer_store_short v[[R_F16]]
 
 ; VI-FLUSH: v_mac_f16_e32 v[[C_F16]], 0x4200, v[[A_F16]]
 ; VI-FLUSH: buffer_store_short v[[C_F16]]
 
 ; VI-DENORM: s_movk_i32 [[KA:s[0-9]+]], 0x4200
 ; VI-DENORM: v_fma_f16 [[RESULT:v[0-9]+]], v[[A_F16]], [[KA]], v[[C_F16]]
-; VI-DENORM buffer_store_short [[RESULT]]
+; VI-DENORM: buffer_store_short [[RESULT]]
 
 ; GFX10-FLUSH: v_mul_f16_e32 [[MUL:v[0-9]+]], 0x4200, v[[A_F16]]
 ; GFX10-FLUSH: v_add_f16_e32 [[ADD:v[0-9]+]], [[MUL]], v[[C_F16]]
 ; GFX10-FLUSH: buffer_store_short [[ADD]]
 
 ; GFX10-DENORM: v_fmac_f16_e32 v[[C_F16]], 0x4200, v[[A_F16]]
-; GFX10-DENORM buffer_store_short v[[C_F16]],
+; GFX10-DENORM: buffer_store_short v[[C_F16]],
 
 ; GCN: s_endpgm
 define amdgpu_kernel void @fmuladd_f16_imm_b(
     half addrspace(1)* %r,
     half addrspace(1)* %a,
     half addrspace(1)* %c) {
   %a.val = load volatile half, half addrspace(1)* %a
   %c.val = load volatile half, half addrspace(1)* %c

llvm/test/CodeGen/AMDGPU/llvm.rint.f64.ll

 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
 ; FUNC-LABEL: {{^}}rint_f64:
 ; CI: v_rndne_f64_e32
 
 ; SI-DAG: v_add_f64
 ; SI-DAG: v_add_f64
-; SI-DAG v_cmp_gt_f64_e64
+; SI-DAG: v_cmp_gt_f64_e64
 ; SI: v_cndmask_b32
 ; SI: v_cndmask_b32
 ; SI: s_endpgm
 define amdgpu_kernel void @rint_f64(double addrspace(1)* %out, double %in) {
 entry:
   %0 = call double @llvm.rint.f64(double %in)
   store double %0, double addrspace(1)* %out
   ret void

llvm/test/CodeGen/AMDGPU/merge-m0.mir

 body:             |
   bb.0:
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     $m0 = S_MOV_B32 -1
     DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
 ...
 
 # GCN-LABEL: name: move-m0-with-prologue
-# GCN $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
+# GCN: $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
 # GCN: $m0 = S_MOV_B32 -1
 # GCN-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
 # GCN-NEXT: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
 ---
 name: move-m0-with-prologue
 body:             |
   bb.0:
     liveins: $sgpr0_sgpr1

llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir

 # W64: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
 # W64: [[CMP0:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
 # W64: [[CMP1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
 # W64: [[CMP:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
 # W64: [[TMPEXEC:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec
 # W64: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, 0, 0, implicit $exec
 # W64: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc
 # W64: S_CBRANCH_EXECNZ %bb.1, implicit $exec
-# W64-LABEL  bb.2:
+# W64-LABEL:  bb.2:
 # W64: $exec = S_MOV_B64 [[SAVEEXEC]]
 
 # W32-LABEL: name: idxen
 # W32-LABEL:  bb.0:
 # W32-NEXT: successors: %bb.1({{.*}})
 # W32: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
 # W32: [[SAVEEXEC:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
 # W32-LABEL: bb.1:
 # W32-NEXT: successors: %bb.1({{.*}}), %bb.2({{.*}})
 # W32: [[SRSRC0:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub0, implicit $exec
 # W32: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
 # W32: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
 # W32: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
 # W32: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
 # W32: [[CMP0:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
 # W32: [[CMP1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
 # W32: [[CMP:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[CMP0]], [[CMP1]], implicit-def $scc
 # W32: [[TMPEXEC:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec
 # W32: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, 0, 0, implicit $exec
 # TODO: S_XOR_B32_term should be `implicit-def $scc`
 # W32: $exec_lo = S_XOR_B32_term $exec_lo, [[TMPEXEC]]
 # W32: S_CBRANCH_EXECNZ %bb.1, implicit $exec
-# W32-LABEL  bb.2:
+# W32-LABEL:  bb.2:
 # W32: $exec_lo = S_MOV_B32 [[SAVEEXEC]]
 ---
 name:            idxen
 liveins:
   - { reg: '$vgpr0', virtual-reg: '%0' }
   - { reg: '$vgpr1', virtual-reg: '%1' }
   - { reg: '$vgpr2', virtual-reg: '%2' }
   - { reg: '$vgpr3', virtual-reg: '%3' }

 # W64: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
 # W64: [[CMP0:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
 # W64: [[CMP1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
 # W64: [[CMP:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
 # W64: [[TMPEXEC:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec
 # W64: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, 0, 0, implicit $exec
 # W64: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc
 # W64: S_CBRANCH_EXECNZ %bb.1, implicit $exec
-# W64-LABEL  bb.2:
+# W64-LABEL:  bb.2:
 # W64: $exec = S_MOV_B64 [[SAVEEXEC]]
 
 # W32-LABEL: name: offen
 # W32-LABEL:  bb.0:
 # W32-NEXT: successors: %bb.1({{.*}})
 # W32: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
 # W32: [[SAVEEXEC:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
 # W32-LABEL: bb.1:
 # W32-NEXT: successors: %bb.1({{.*}}), %bb.2({{.*}})
 # W32: [[SRSRC0:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub0, implicit $exec
 # W32: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
 # W32: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
 # W32: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
 # W32: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
 # W32: [[CMP0:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
 # W32: [[CMP1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
 # W32: [[CMP:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[CMP0]], [[CMP1]], implicit-def $scc
 # W32: [[TMPEXEC:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec
 # W32: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, 0, 0, implicit $exec
 # TODO: S_XOR_B32_term should be `implicit-def $scc`
 # W32: $exec_lo = S_XOR_B32_term $exec_lo, [[TMPEXEC]]
 # W32: S_CBRANCH_EXECNZ %bb.1, implicit $exec
-# W32-LABEL  bb.2:
+# W32-LABEL:  bb.2:
 # W32: $exec_lo = S_MOV_B32 [[SAVEEXEC]]
 ---
 name:            offen
 liveins:
   - { reg: '$vgpr0', virtual-reg: '%0' }
   - { reg: '$vgpr1', virtual-reg: '%1' }
   - { reg: '$vgpr2', virtual-reg: '%2' }
   - { reg: '$vgpr3', virtual-reg: '%3' }

 # W64: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
 # W64: [[CMP0:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
 # W64: [[CMP1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
 # W64: [[CMP:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
 # W64: [[TMPEXEC:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec
 # W64: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_BOTHEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, 0, 0, implicit $exec
 # W64: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc
 # W64: S_CBRANCH_EXECNZ %bb.1, implicit $exec
-# W64-LABEL  bb.2:
+# W64-LABEL:  bb.2:
 # W64: $exec = S_MOV_B64 [[SAVEEXEC]]
 
 # W32-LABEL: name: bothen
 # W32-LABEL:  bb.0:
 # W32-NEXT: successors: %bb.1({{.*}})
 # W32: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
 # W32: [[SAVEEXEC:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
 # W32-LABEL: bb.1:
 # W32-NEXT: successors: %bb.1({{.*}}), %bb.2({{.*}})
 # W32: [[SRSRC0:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub0, implicit $exec
 # W32: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
 # W32: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
 # W32: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
 # W32: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
 # W32: [[CMP0:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
 # W32: [[CMP1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
 # W32: [[CMP:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[CMP0]], [[CMP1]], implicit-def $scc
 # W32: [[TMPEXEC:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec
 # W32: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_BOTHEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, 0, 0, implicit $exec
 # TODO: S_XOR_B32_term should be `implicit-def $scc`
 # W32: $exec_lo = S_XOR_B32_term $exec_lo, [[TMPEXEC]]
 # W32: S_CBRANCH_EXECNZ %bb.1, implicit $exec
-# W32-LABEL  bb.2:
+# W32-LABEL:  bb.2:
 # W32: $exec_lo = S_MOV_B32 [[SAVEEXEC]]
 ---
 name:            bothen
 liveins:
   - { reg: '$vgpr0', virtual-reg: '%0' }
   - { reg: '$vgpr1', virtual-reg: '%1' }
   - { reg: '$vgpr2', virtual-reg: '%2' }
   - { reg: '$vgpr3', virtual-reg: '%3' }

 # W64-NO-ADDR64: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
 # W64-NO-ADDR64: [[CMP0:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
 # W64-NO-ADDR64: [[CMP1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
 # W64-NO-ADDR64: [[CMP:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
 # W64-NO-ADDR64: [[TMPEXEC:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec
 # W64-NO-ADDR64: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFSET killed [[SRSRC]], 0, 0, 0, 0, 0, 0, 0, implicit $exec
 # W64-NO-ADDR64: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc
 # W64-NO-ADDR64: S_CBRANCH_EXECNZ %bb.1, implicit $exec
-# W64-NO-ADDR64-LABEL  bb.2:
+# W64-NO-ADDR64-LABEL:  bb.2:
 # W64-NO-ADDR64: $exec = S_MOV_B64 [[SAVEEXEC]]
 
 # W32: successors: %bb.1({{.*}})
 # W32: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
 # W32: [[SAVEEXEC:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
 # W32-LABEL: bb.1:
 # W32-NEXT: successors: %bb.1({{.*}}), %bb.2({{.*}})
 # W32: [[SRSRC0:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub0, implicit $exec
 # W32: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
 # W32: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
 # W32: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
 # W32: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
 # W32: [[CMP0:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
 # W32: [[CMP1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
 # W32: [[CMP:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[CMP0]], [[CMP1]], implicit-def $scc
 # W32: [[TMPEXEC:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec
 # W32: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFSET killed [[SRSRC]], 0, 0, 0, 0, 0, 0, 0, implicit $exec
 # TODO: S_XOR_B32_term should be `implicit-def $scc`
 # W32: $exec_lo = S_XOR_B32_term $exec_lo, [[TMPEXEC]]
 # W32: S_CBRANCH_EXECNZ %bb.1, implicit $exec
-# W32-LABEL  bb.2:
+# W32-LABEL:  bb.2:
 # W32: $exec_lo = S_MOV_B32 [[SAVEEXEC]]
 
 # ADDR64: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
 # ADDR64: [[RSRCPTR:%[0-9]+]]:vreg_64 = COPY [[VRSRC]].sub0_sub1
 # ADDR64: [[ZERO64:%[0-9]+]]:sreg_64 = S_MOV_B64 0
 # ADDR64: [[RSRCFMTLO:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
 # ADDR64: [[RSRCFMTHI:%[0-9]+]]:sgpr_32 = S_MOV_B32 61440
 # ADDR64: [[ZERORSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[ZERO64]], %subreg.sub0_sub1, [[RSRCFMTLO]], %subreg.sub2, [[RSRCFMTHI]], %subreg.sub3

llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll

 ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -mattr=-code-object-v3,+promote-alloca < %s | FileCheck -check-prefix=NOOPTS -check-prefix=ALL %s
 ; RUN: llc -O1 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -mattr=-code-object-v3,+promote-alloca < %s | FileCheck -check-prefix=OPTS -check-prefix=ALL %s
 
 ; ALL-LABEL: {{^}}promote_alloca_i32_array_array:
 ; NOOPTS: workgroup_group_segment_byte_size = 0{{$}}
-; NOOPTS-NOT ds_write
+; NOOPTS-NOT: ds_write
 ; OPTS: ds_write
 define amdgpu_kernel void @promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 {
 entry:
   %alloca = alloca [2 x [2 x i32]], addrspace(5)
   %gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 0
   %gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 1
   store i32 0, i32 addrspace(5)* %gep0
   store i32 1, i32 addrspace(5)* %gep1
   %gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index
   %load = load i32, i32 addrspace(5)* %gep2
   store i32 %load, i32 addrspace(1)* %out
   ret void
 }
 
 ; ALL-LABEL: {{^}}optnone_promote_alloca_i32_array_array:
 ; ALL: workgroup_group_segment_byte_size = 0{{$}}
-; ALL-NOT ds_write
+; ALL-NOT: ds_write
 define amdgpu_kernel void @optnone_promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #1 {
 entry:
   %alloca = alloca [2 x [2 x i32]], addrspace(5)
   %gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 0
   %gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 1
   store i32 0, i32 addrspace(5)* %gep0
   store i32 1, i32 addrspace(5)* %gep1
   %gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index
   %load = load i32, i32 addrspace(5)* %gep2
   store i32 %load, i32 addrspace(1)* %out
   ret void
 }
 
 attributes #0 = { nounwind "amdgpu-flat-work-group-size"="64,64" }
 attributes #1 = { nounwind optnone noinline "amdgpu-flat-work-group-size"="64,64" }

llvm/test/CodeGen/AMDGPU/rewrite-out-arguments.ll

 
 ; CHECK-LABEL: define private %unused_different_type @unused_different_type.body(i32* %arg0, float* nocapture %arg1) #0 {
 ; CHECK-NEXT: ret %unused_different_type { float 4.000000e+00 }
 
 ; CHECK-LABEL: define void @unused_different_type(i32* %0, float* nocapture %1) #2 {
 ; CHECK-NEXT: %3 = call %unused_different_type @unused_different_type.body(i32* %0, float* undef)
 ; CHECK-NEXT: %4 = extractvalue %unused_different_type %3, 0
 ; CHECK-NEXT: store float %4, float* %1, align 4
-; CHECK-NEXT  ret void
+; CHECK-NEXT: ret void
 define void @unused_different_type(i32* %arg0, float* nocapture %arg1) #0 {
   store float 4.0, float* %arg1, align 4
   ret void
 }
 
 ; CHECK-LABEL: define private %multiple_same_return_noalias @multiple_same_return_noalias.body(i32* noalias %out0, i32* noalias %out1) #0 {
 ; CHECK-NEXT: ret %multiple_same_return_noalias { i32 1, i32 2 }
 

llvm/test/CodeGen/AMDGPU/salu-to-valu.ll

entry:
   %tmp3 = load i32, i32 addrspace(4)* %tmp2
   %tmp4 = add i32 %tmp3, %a
   store i32 %tmp4, i32 addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}smrd_valu2_max_smrd_offset:
 ; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1020{{$}}
-; GCN-HSA flat_load_dword v{{[0-9]}}, v{{[0-9]+:[0-9]+}}
+; GCN-HSA: flat_load_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}]
 define amdgpu_kernel void @smrd_valu2_max_smrd_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(4)* %in) #1 {
 entry:
   %tmp = call i32 @llvm.amdgcn.workitem.id.x()
   %tmp1 = add i32 %tmp, 4
   %tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(4)* %in, i32 %tmp, i32 255
   %tmp3 = load i32, i32 addrspace(4)* %tmp2
   store i32 %tmp3, i32 addrspace(1)* %out
   ret void

llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir

bb.0:
     %0:vgpr_32 = COPY $vgpr0
     %1:sreg_32_xm0 = COPY %0
     S_ENDPGM 0, implicit %1
 ...
 
 ---
 
 # GCN-LABEL: name: dead_illegal_physreg_copy
-# GCN %2:vgpr_32 = COPY $vgpr0
+# GCN: %2:vgpr_32 = COPY $vgpr0
 # GCN: %1:sreg_32_xm0 = IMPLICIT_DEF
 # GCN: S_ENDPGM 0, implicit %2
 
 name: dead_illegal_physreg_copy
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $vgpr0
     %0:sreg_32_xm0 = COPY $vgpr0
     %1:sreg_32_xm0 = COPY %0
     S_ENDPGM 0, implicit %1
 ...

llvm/test/CodeGen/AMDGPU/si-scheduler.ll

 attributes #2 = { nounwind readonly }
 
 !0 = !{!1, !1, i64 0, i32 1}
 !1 = !{!"const", !2}
 !2 = !{!"tbaa root"}
 
 
 ; CHECK-LABEL: amdgpu_ps_main:
-; CHECK s_buffer_load_dword
+; CHECK: s_buffer_load_dword
 define amdgpu_ps void @_amdgpu_ps_main(i32 %arg) local_unnamed_addr {
 .entry:
   %tmp = insertelement <2 x i32> zeroinitializer, i32 %arg, i32 0
   %tmp1 = bitcast <2 x i32> %tmp to i64
   %tmp2 = inttoptr i64 %tmp1 to <4 x i32> addrspace(4)*
   %tmp3 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp2, align 16
   %tmp4 = tail call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp3, i32 0, i32 0) #0
   switch i32 %tmp4, label %bb [

llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll

 ; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX908 %s
 ; RUN: not llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefixes=GCN,GFX900 %s
 
 ; GCN-LABEL: {{^}}max_10_vgprs:
 ; GFX900-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
 ; GFX900-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
 ; GFX908-NOT: SCRATCH_RSRC
 ; GFX908-DAG: v_accvgpr_write_b32 a0, v{{[0-9]}}
 ; GFX908-DAG: v_accvgpr_write_b32 a1, v{{[0-9]}}
 ; GFX900:     buffer_store_dword v{{[0-9]}},
 ; GFX900:     buffer_store_dword v{{[0-9]}},
 ; GFX900:     buffer_load_dword v{{[0-9]}},
 ; GFX900:     buffer_load_dword v{{[0-9]}},
 ; GFX908-NOT: buffer_
-; GFX908-DAG  v_accvgpr_read_b32 v{{[0-9]}}, a0
+; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a0
 ; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a1
 
 ; GCN:    NumVgprs: 10
 ; GFX900: ScratchSize: 12
 ; GFX908: ScratchSize: 0
 ; GCN:    VGPRBlocks: 2
 ; GCN:    NumVGPRsForWavesPerEU: 10
 define amdgpu_kernel void @max_10_vgprs(i32 addrspace(1)* %p) #0 {

 ; GFX908-DAG: v_accvgpr_write_b32 a6, v{{[0-9]}}
 ; GFX908-DAG: v_accvgpr_write_b32 a7, v{{[0-9]}}
 ; GFX908-DAG: v_accvgpr_write_b32 a8, v{{[0-9]}}
 ; GFX908-DAG: v_accvgpr_write_b32 a9, v{{[0-9]}}
 ; GFX900:     buffer_store_dword v{{[0-9]}},
 ; GCN-DAG:    buffer_store_dword v{{[0-9]}},
 ; GFX900:     buffer_load_dword v{{[0-9]}},
 ; GCN-DAG:    buffer_load_dword v{{[0-9]}},
-; GFX908-DAG  v_accvgpr_read_b32 v{{[0-9]}}, a1
+; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a1
 ; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a2
 ; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a3
 ; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a4
 ; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a5
 ; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a6
 ; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a7
 ; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a8
 ; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a9

 ; GCN-LABEL: {{^}}max_256_vgprs_spill_9x32:
 ; GFX900-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
 ; GFX900-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
 ; GFX908-NOT: SCRATCH_RSRC
 ; GFX908-DAG: v_accvgpr_write_b32 a0, v
 ; GFX900:     buffer_store_dword v
 ; GFX900:     buffer_load_dword v
 ; GFX908-NOT: buffer_
-; GFX908-DAG  v_accvgpr_read_b32
+; GFX908-DAG: v_accvgpr_read_b32
 
 ; GCN:    NumVgprs: 256
 ; GFX900: ScratchSize: 148
 ; GFX908: ScratchSize: 0
 ; GCN:    VGPRBlocks: 63
 ; GCN:    NumVGPRsForWavesPerEU: 256
 define amdgpu_kernel void @max_256_vgprs_spill_9x32(<32 x float> addrspace(1)* %p) {
   %tid = call i32 @llvm.amdgcn.workitem.id.x()

llvm/test/CodeGen/AMDGPU/udivrem24.ll

define amdgpu_kernel void @udiv23_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
   %den.i23 = lshr i32 %den.i23.0, 9
   %result = udiv i32 %num.i23, %den.i23
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; FUNC-LABEL: {{^}}udiv24_i32:
 ; SI: v_rcp_iflag
-; SI-NOT v_rcp_f32
+; SI-NOT: v_rcp_f32
 ; EG-NOT: RECIP_IEEE
 define amdgpu_kernel void @udiv24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
   %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
   %num = load i32, i32 addrspace(1) * %in, align 4
   %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 8
   %den.i24.0 = shl i32 %den, 8
   %num.i24 = lshr i32 %num.i24.0, 8
   %den.i24 = lshr i32 %den.i24.0, 8
   %result = udiv i32 %num.i24, %den.i24
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; FUNC-LABEL: {{^}}no_udiv24_u23_u24_i32:
 ; SI: v_rcp_iflag
-; SI-NOT v_rcp_f32
+; SI-NOT: v_rcp_f32
 ; EG-NOT: RECIP_IEEE
 define amdgpu_kernel void @no_udiv24_u23_u24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
   %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
   %num = load i32, i32 addrspace(1) * %in, align 4
   %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i23.0 = shl i32 %num, 9
   %den.i24.0 = shl i32 %den, 8
   %num.i23 = lshr i32 %num.i23.0, 9
   %den.i24 = lshr i32 %den.i24.0, 8
   %result = udiv i32 %num.i23, %den.i24
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; FUNC-LABEL: {{^}}no_udiv24_u24_u23_i32:
 ; SI: v_rcp_iflag
-; SI-NOT v_rcp_f32
+; SI-NOT: v_rcp_f32
 ; EG-NOT: RECIP_IEEE
 define amdgpu_kernel void @no_udiv24_u24_u23_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
   %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
   %num = load i32, i32 addrspace(1) * %in, align 4
   %den = load i32, i32 addrspace(1) * %den_ptr, align 4
   %num.i24.0 = shl i32 %num, 8
   %den.i23.0 = shl i32 %den, 9
   %num.i24 = lshr i32 %num.i24.0, 8

llvm/test/CodeGen/ARM/acle-intrinsics.ll

; CHECK: uxtb16 r0, r0
   %tmp1 = call i32 @llvm.arm.sxtb16(i32 %tmp)
   %tmp2 = call i32 @llvm.arm.uxtab16(i32 %b, i32 %tmp1)
   %tmp3 = call i32 @llvm.arm.uxtb16(i32 %tmp2)
   ret i32 %tmp3
 }
 
 define i32 @sel(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: sel
-; CHECK sel r0, r0, r1
+; CHECK: sel r0, r0, r1
   %tmp = call i32 @llvm.arm.sel(i32 %a, i32 %b)
   ret i32 %tmp
 }
 
 define i32 @qadd8(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: qadd8
 ; CHECK: qadd8 r0, r0, r1
   %tmp = call i32 @llvm.arm.qadd8(i32 %a, i32 %b)

llvm/test/CodeGen/ARM/debug-segmented-stacks.ll

 ; ARM-linux-NEXT: bl      __morestack
 ; ARM-linux-NEXT: ldm     sp!, {lr}
 ; ARM-linux-NEXT: pop     {r4, r5}
 ; ARM-linux:      .cfi_def_cfa_offset 0
 ; ARM-linux-NEXT: bx      lr
 
 ; ARM-linux:      pop     {r4, r5}
 ; ARM-linux:      .cfi_def_cfa_offset 0
-; ARM-linux       .cfi_same_value r4
-; ARM-linux       .cfi_same_value r5
+; ARM-linux:      .cfi_same_value r4
+; ARM-linux:      .cfi_same_value r5
 }
 
 !0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: FullDebug, file: !1, enums: !2, retainedTypes: !2, globals: !2, imports: !2)
 !1 = !DIFile(filename: "var.c", directory: "/tmp")
 !2 = !{}
 !4 = distinct !DISubprogram(name: "test_basic", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, unit: !0, scopeLine: 5, file: !1, scope: !5, type: !6, retainedNodes: !2)
 !5 = !DIFile(filename: "var.c", directory: "/tmp")
 !6 = !DISubroutineType(types: !7)

llvm/test/CodeGen/BPF/rodata_4.ll

 entry:
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 bitcast (%struct.test_t1* @g to i8*), i8* align 2 bitcast (%struct.test_t1* getelementptr inbounds ([4 x %struct.test_t1], [4 x %struct.test_t1]* @test.t1, i64 0, i64 1) to i8*), i64 6, i1 false)
 ; CHECK:  r2 = 600
 ; CHECK:  *(u16 *)(r1 + 2) = r2
 ; CHECK:  r2 = 60
 ; CHECK:  *(u16 *)(r1 + 0) = r2
   ret i32 0
 }
-; CHECK  .section  .rodata,"a",@progbits
+; CHECK:  .section  .rodata,"a",@progbits
 
 ; Function Attrs: argmemonly nounwind
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1) #1
 
 attributes #0 = { nounwind }
 attributes #1 = { argmemonly nounwind }

llvm/test/CodeGen/Hexagon/constant_compound.ll

 ; RUN: llc -march=hexagon < %s 2>&1 | FileCheck %s
 
 ; Generating a compound instruction with a constant is not profitable.
 ; The constant needs to be kept in a register before it is fed to compound
 ; instruction.
 ; Before, we are generating
 ; ra = #65820;
 ; rb = lsr(rb, #8);
 ; rc ^= and (rb, ra)
 ; Now, we are generating
 ; ra = and (#65820, lsr(ra, #8));
 ; rb = xor(rb, ra)
 
 ; CHECK: and(##65280,lsr(r
-; CHECK-NOT : ^= and
+; CHECK-NOT: ^= and
 
 define dso_local zeroext i16 @test_compound(i16 zeroext %varA, i16 zeroext %varB) local_unnamed_addr #0 {
 entry:
   %tmp = zext i16 %varB to i32
   %tmp1 = and i16 %varA, 255
   %tmp2 = zext i16 %tmp1 to i32
   %.masked.i = and i32 %tmp, 255
   %tmp3 = xor i32 %.masked.i, %tmp2

llvm/test/CodeGen/Hexagon/intrinsics/v65.ll

 ; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O0 < %s | FileCheck %s
 ; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
 
 ; CHECK-CALL-NOT: call
 
 declare i32 @llvm.hexagon.A6.vcmpbeq.notany(i64, i64)
 define i32 @A6_vcmpbeq_notany(i64 %a, i64 %b) {
   %c = call i32 @llvm.hexagon.A6.vcmpbeq.notany(i64 %a, i64 %b)
   ret i32 %c
 }
-; CHECK = !any8(vcmpb.eq(r1:0,r3:2))
+; CHECK: = !any8(vcmpb.eq(r1:0,r3:2))
 
 declare <16 x i32> @llvm.hexagon.V6.vabsb(<16 x i32>)
 define <16 x i32> @V6_vabsb(<16 x i32> %a) {
   %b = call <16 x i32> @llvm.hexagon.V6.vabsb(<16 x i32> %a)
   ret <16 x i32> %b
 }
 ; CHECK: = vabs(v0.b)
 

llvm/test/CodeGen/Mips/nmadd.ll

 
 define float @add1(float %f, float %g, float %h) local_unnamed_addr #0 {
 entry:
 ; ALL-LABEL: add1
 
 ; CHECK-NM-64:             nmadd.s $f0, $f14, $f12, $f13
 ; CHECK-NM:                nmadd.s $f0, $f0, $f12, $f14
 ; CHECK-MM:                NMADD_S_MM
-; CHECK-NOT-NM-64          mul.s $f0, $f12, $f13
+; CHECK-NOT-NM-64:         mul.s $f0, $f12, $f13
 ; CHECK-NOT-NM-64:         neg.s $f0, $f0
 ; CHECK-NOT-NM:            mul.s $f0, $f12, $f14
 ; CHECK-NOT-NM:            neg.s $f0, $f0
 
   %mul = fmul nnan float %f, %g
   %add = fadd nnan float %mul, %h
   %sub = fsub nnan float -0.000000e+00, %add
   ret float %sub
 }
 
 define double @add2(double %f, double %g, double %h) local_unnamed_addr #0 {
 entry:
 ; ALL-LABEL: add2
 
 ; CHECK-NM-64:             nmadd.d $f0, $f14, $f12, $f13
 ; CHECK-NM:                nmadd.d $f0, $f0, $f12, $f14
 ; CHECK-MM:                NMADD_D32_MM
-; CHECK-NOT-NM-64          mul.d $f0, $f12, $f13
+; CHECK-NOT-NM-64:         mul.d $f0, $f12, $f13
 ; CHECK-NOT-NM-64:         neg.d $f0, $f0
 ; CHECK-NOT-NM:            mul.d $f0, $f12, $f14
 ; CHECK-NOT-NM:            neg.d $f0, $f0
 
   %mul = fmul nnan double %f, %g
   %add = fadd nnan double %mul, %h
   %sub = fsub nnan double -0.000000e+00, %add
   ret double %sub
 }
 
 define float @sub1(float %f, float %g, float %h) local_unnamed_addr #0 {
 entry:
 ; ALL-LABEL: sub1
 
 ; CHECK-NM-64:             nmsub.s $f0, $f14, $f12, $f13
 ; CHECK-NM:                nmsub.s $f0, $f0, $f12, $f14
 ; CHECK-MM:                NMSUB_S_MM
-; CHECK-NOT-NM-64          mul.s $f0, $f12, $f13
+; CHECK-NOT-NM-64:         mul.s $f0, $f12, $f13
 ; CHECK-NOT-NM-64:         neg.s $f0, $f0
 ; CHECK-NOT-NM:            mul.s $f0, $f12, $f14
 ; CHECK-NOT-NM:            neg.s $f0, $f0
 
   %mul = fmul nnan float %f, %g
   %sub = fsub nnan float %mul, %h
   %sub1 = fsub nnan float -0.000000e+00, %sub
   ret float %sub1
 }
 
 define double @sub2(double %f, double %g, double %h) local_unnamed_addr #0 {
 entry:
 ; ALL-LABEL: sub2
 
 ; CHECK-NM-64:             nmsub.d $f0, $f14, $f12, $f13
 ; CHECK-NM:                nmsub.d $f0, $f0, $f12, $f14
 ; CHECK-MM:                NMSUB_D32_MM
-; CHECK-NOT-NM-64          mul.d $f0, $f12, $f13
+; CHECK-NOT-NM-64:         mul.d $f0, $f12, $f13
 ; CHECK-NOT-NM-64:         neg.d $f0, $f0
 ; CHECK-NOT-NM:            mul.d $f0, $f12, $f14
 ; CHECK-NOT-NM:            neg.d $f0, $f0
 
   %mul = fmul nnan double %f, %g
   %sub = fsub nnan double %mul, %h
   %sub1 = fsub nnan double -0.000000e+00, %sub
   ret double %sub1
 }

llvm/test/CodeGen/NVPTX/atomics-sm60.ll

 ; RUN: llc < %s -march=nvptx -mcpu=sm_60 | FileCheck %s
 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_60 | FileCheck %s
 
-; CHECK-LABEL .func test(
+; CHECK-LABEL: .func test(
 define void @test(double* %dp0, double addrspace(1)* %dp1, double addrspace(3)* %dp3, double %d) {
 ; CHECK: atom.add.f64
   %r1 = call double @llvm.nvvm.atomic.load.add.f64.p0f64(double* %dp0, double %d)
 ; CHECK: atom.global.add.f64
   %r2 = call double @llvm.nvvm.atomic.load.add.f64.p1f64(double addrspace(1)* %dp1, double %d)
 ; CHECK: atom.shared.add.f64
   %ret = call double @llvm.nvvm.atomic.load.add.f64.p3f64(double addrspace(3)* %dp3, double %d)
   ret void
 }
 
-; CHECK-LABEL .func test2(
+; CHECK-LABEL: .func test2(
 define void @test2(double* %dp0, double addrspace(1)* %dp1, double addrspace(3)* %dp3, double %d) {
 ; CHECK: atom.add.f64
   %r1 = atomicrmw fadd double* %dp0, double %d seq_cst
 ; CHECK: atom.global.add.f64
   %r2 = atomicrmw fadd double addrspace(1)* %dp1, double %d seq_cst
 ; CHECK: atom.shared.add.f64
   %ret = atomicrmw fadd double addrspace(3)* %dp3, double %d seq_cst
   ret void
 }
 
 declare double @llvm.nvvm.atomic.load.add.f64.p0f64(double* nocapture, double) #1
 declare double @llvm.nvvm.atomic.load.add.f64.p1f64(double addrspace(1)* nocapture, double) #1
 declare double @llvm.nvvm.atomic.load.add.f64.p3f64(double addrspace(3)* nocapture, double) #1
 
 attributes #1 = { argmemonly nounwind }

llvm/test/CodeGen/NVPTX/intrinsics.ll

 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
 
-; CHECK-LABEL test_fabsf(
+; CHECK-LABEL: test_fabsf(
 define float @test_fabsf(float %f) {
 ; CHECK: abs.f32
   %x = call float @llvm.fabs.f32(float %f)
   ret float %x
 }
 
 ; CHECK-LABEL: test_fabs(
 define double @test_fabs(double %d) {

llvm/test/CodeGen/NVPTX/param-load-store.ll

define <4 x i8> @test_v4i8(<4 x i8> %a) {
        %r = tail call <4 x i8> @test_v4i8(<4 x i8> %a);
        ret <4 x i8> %r;
 }
 
 ; CHECK: .func  (.param .align 8 .b8 func_retval0[8])
 ; CHECK-LABEL: test_v5i8(
 ; CHECK-NEXT: .param .align 8 .b8 test_v5i8_param_0[8]
 ; CHECK-DAG:  ld.param.u8     [[E4:%rs[0-9]+]], [test_v5i8_param_0+4];
-; CHECK-DAG   ld.param.v4.u8  {[[E0:%rs[0-9]+]], [[E1:%rs[0-9]+]], [[E2:%rs[0-9]+]], [[E3:%rs[0-9]+]]}, [test_v5i8_param_0]
+; CHECK-DAG:  ld.param.v4.u8  {[[E0:%rs[0-9]+]], [[E1:%rs[0-9]+]], [[E2:%rs[0-9]+]], [[E3:%rs[0-9]+]]}, [test_v5i8_param_0]
 ; CHECK:      .param .align 8 .b8 param0[8];
 ; CHECK-DAG:  st.param.v4.b8  [param0+0], {[[E0]], [[E1]], [[E2]], [[E3]]};
 ; CHECK-DAG:  st.param.b8     [param0+4], [[E4]];
 ; CHECK:      .param .align 8 .b8 retval0[8];
 ; CHECK:      call.uni (retval0),
 ; CHECK-NEXT: test_v5i8,
 ; CHECK-DAG:  ld.param.v4.b8  {[[RE0:%rs[0-9]+]], [[RE1:%rs[0-9]+]], [[RE2:%rs[0-9]+]], [[RE3:%rs[0-9]+]]}, [retval0+0];
 ; CHECK-DAG:  ld.param.b8     [[RE4:%rs[0-9]+]], [retval0+4];
define <4 x i16> @test_v4i16(<4 x i16> %a) {
        %r = tail call <4 x i16> @test_v4i16(<4 x i16> %a);
        ret <4 x i16> %r;
 }
 
 ; CHECK: .func  (.param .align 16 .b8 func_retval0[16])
 ; CHECK-LABEL: test_v5i16(
 ; CHECK-NEXT: .param .align 16 .b8 test_v5i16_param_0[16]
 ; CHECK-DAG:  ld.param.u16    [[E4:%rs[0-9]+]], [test_v5i16_param_0+8];
-; CHECK-DAG   ld.param.v4.u16 {[[E0:%rs[0-9]+]], [[E1:%rs[0-9]+]], [[E2:%rs[0-9]+]], [[E3:%rs[0-9]+]]}, [test_v5i16_param_0]
+; CHECK-DAG:  ld.param.v4.u16 {[[E0:%rs[0-9]+]], [[E1:%rs[0-9]+]], [[E2:%rs[0-9]+]], [[E3:%rs[0-9]+]]}, [test_v5i16_param_0]
 ; CHECK:      .param .align 16 .b8 param0[16];
 ; CHECK-DAG:  st.param.v4.b16 [param0+0], {[[E0]], [[E1]], [[E2]], [[E3]]};
 ; CHECK-DAG:  st.param.b16    [param0+8], [[E4]];
 ; CHECK:      .param .align 16 .b8 retval0[16];
 ; CHECK:      call.uni (retval0),
 ; CHECK-NEXT: test_v5i16,
 ; CHECK-DAG:  ld.param.v4.b16 {[[RE0:%rs[0-9]+]], [[RE1:%rs[0-9]+]], [[RE2:%rs[0-9]+]], [[RE3:%rs[0-9]+]]}, [retval0+0];
 ; CHECK-DAG:  ld.param.b16    [[RE4:%rs[0-9]+]], [retval0+8];
define <4 x i32> @test_v4i32(<4 x i32> %a) {
        %r = tail call <4 x i32> @test_v4i32(<4 x i32> %a);
        ret <4 x i32> %r;
 }
 
 ; CHECK: .func  (.param .align 32 .b8 func_retval0[32])
 ; CHECK-LABEL: test_v5i32(
 ; CHECK-NEXT: .param .align 32 .b8 test_v5i32_param_0[32]
 ; CHECK-DAG:  ld.param.u32     [[E4:%r[0-9]+]], [test_v5i32_param_0+16];
-; CHECK-DAG   ld.param.v4.u32  {[[E0:%r[0-9]+]], [[E1:%r[0-9]+]], [[E2:%r[0-9]+]], [[E3:%r[0-9]+]]}, [test_v5i32_param_0]
+; CHECK-DAG:  ld.param.v4.u32  {[[E0:%r[0-9]+]], [[E1:%r[0-9]+]], [[E2:%r[0-9]+]], [[E3:%r[0-9]+]]}, [test_v5i32_param_0]
 ; CHECK:      .param .align 32 .b8 param0[32];
 ; CHECK-DAG:  st.param.v4.b32  [param0+0], {[[E0]], [[E1]], [[E2]], [[E3]]};
 ; CHECK-DAG:  st.param.b32     [param0+16], [[E4]];
 ; CHECK:      .param .align 32 .b8 retval0[32];
 ; CHECK:      call.uni (retval0),
 ; CHECK-NEXT: test_v5i32,
 ; CHECK-DAG:  ld.param.v4.b32  {[[RE0:%r[0-9]+]], [[RE1:%r[0-9]+]], [[RE2:%r[0-9]+]], [[RE3:%r[0-9]+]]}, [retval0+0];
 ; CHECK-DAG:  ld.param.b32     [[RE4:%r[0-9]+]], [retval0+16];

llvm/test/CodeGen/NVPTX/sqrt-approx.ll

 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-prec-divf32=0 -nvptx-prec-sqrtf32=0 \
 ; RUN:   | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
 
 declare float @llvm.sqrt.f32(float)
 declare double @llvm.sqrt.f64(double)
 
 ; -- reciprocal sqrt --
 
-; CHECK-LABEL test_rsqrt32
+; CHECK-LABEL: test_rsqrt32
 define float @test_rsqrt32(float %a) #0 {
 ; CHECK: rsqrt.approx.f32
   %val = tail call float @llvm.sqrt.f32(float %a)
   %ret = fdiv float 1.0, %val
   ret float %ret
 }
 
-; CHECK-LABEL test_rsqrt_ftz
+; CHECK-LABEL: test_rsqrt_ftz
 define float @test_rsqrt_ftz(float %a) #0 #1 {
 ; CHECK: rsqrt.approx.ftz.f32
   %val = tail call float @llvm.sqrt.f32(float %a)
   %ret = fdiv float 1.0, %val
   ret float %ret
 }
 
-; CHECK-LABEL test_rsqrt64
+; CHECK-LABEL: test_rsqrt64
 define double @test_rsqrt64(double %a) #0 {
 ; CHECK: rsqrt.approx.f64
   %val = tail call double @llvm.sqrt.f64(double %a)
   %ret = fdiv double 1.0, %val
   ret double %ret
 }
 
-; CHECK-LABEL test_rsqrt64_ftz
+; CHECK-LABEL: test_rsqrt64_ftz
 define double @test_rsqrt64_ftz(double %a) #0 #1 {
 ; There's no rsqrt.approx.ftz.f64 instruction; we just use the non-ftz version.
 ; CHECK: rsqrt.approx.f64
   %val = tail call double @llvm.sqrt.f64(double %a)
   %ret = fdiv double 1.0, %val
   ret double %ret
 }
 
 ; -- sqrt --
 
-; CHECK-LABEL test_sqrt32
+; CHECK-LABEL: test_sqrt32
 define float @test_sqrt32(float %a) #0 {
 ; CHECK: sqrt.rn.f32
   %ret = tail call float @llvm.sqrt.f32(float %a)
   ret float %ret
 }
 
-; CHECK-LABEL test_sqrt32_ninf
+; CHECK-LABEL: test_sqrt32_ninf
 define float @test_sqrt32_ninf(float %a) #0 {
 ; CHECK: sqrt.approx.f32
   %ret = tail call ninf float @llvm.sqrt.f32(float %a)
   ret float %ret
 }
 
-; CHECK-LABEL test_sqrt_ftz
+; CHECK-LABEL: test_sqrt_ftz
 define float @test_sqrt_ftz(float %a) #0 #1 {
 ; CHECK: sqrt.rn.ftz.f32
   %ret = tail call float @llvm.sqrt.f32(float %a)
   ret float %ret
 }
 
-; CHECK-LABEL test_sqrt_ftz_ninf
+; CHECK-LABEL: test_sqrt_ftz_ninf
 define float @test_sqrt_ftz_ninf(float %a) #0 #1 {
 ; CHECK: sqrt.approx.ftz.f32
   %ret = tail call ninf float @llvm.sqrt.f32(float %a)
   ret float %ret
 }
 
-; CHECK-LABEL test_sqrt64
+; CHECK-LABEL: test_sqrt64
 define double @test_sqrt64(double %a) #0 {
 ; CHECK: sqrt.rn.f64
   %ret = tail call double @llvm.sqrt.f64(double %a)
   ret double %ret
 }
 
-; CHECK-LABEL test_sqrt64_ninf
+; CHECK-LABEL: test_sqrt64_ninf
 define double @test_sqrt64_ninf(double %a) #0 {
 ; There's no sqrt.approx.f64 instruction; we emit
 ; reciprocal(rsqrt.approx.f64(x)).  There's no non-ftz approximate reciprocal,
 ; so we just use the ftz version.
 ; CHECK: rsqrt.approx.f64
 ; CHECK: rcp.approx.ftz.f64
   %ret = tail call ninf double @llvm.sqrt.f64(double %a)
   ret double %ret
 }
 
-; CHECK-LABEL test_sqrt64_ftz
+; CHECK-LABEL: test_sqrt64_ftz
 define double @test_sqrt64_ftz(double %a) #0 #1 {
 ; CHECK: sqrt.rn.f64
   %ret = tail call double @llvm.sqrt.f64(double %a)
   ret double %ret
 }
 
-; CHECK-LABEL test_sqrt64_ftz_ninf
+; CHECK-LABEL: test_sqrt64_ftz_ninf
 define double @test_sqrt64_ftz_ninf(double %a) #0 #1 {
 ; There's no sqrt.approx.ftz.f64 instruction; we just use the non-ftz version.
 ; CHECK: rsqrt.approx.f64
 ; CHECK: rcp.approx.ftz.f64
   %ret = tail call ninf double @llvm.sqrt.f64(double %a)
   ret double %ret
 }
 

llvm/test/CodeGen/NVPTX/vector-loads.ll

 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
 
 ; Even though general vector types are not supported in PTX, we can still
 ; optimize loads/stores with pseudo-vector instructions of the form:
 ;
 ; ld.v2.f32 {%f0, %f1}, [%r0]
 ;
 ; which will load two floats at once into scalar registers.
 
-; CHECK-LABEL foo
+; CHECK-LABEL: foo
 define void @foo(<2 x float>* %a) {
 ; CHECK: ld.v2.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}}
   %t1 = load <2 x float>, <2 x float>* %a
   %t2 = fmul <2 x float> %t1, %t1
   store <2 x float> %t2, <2 x float>* %a
   ret void
 }
 
-; CHECK-LABEL foo2
+; CHECK-LABEL: foo2
 define void @foo2(<4 x float>* %a) {
 ; CHECK: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
   %t1 = load <4 x float>, <4 x float>* %a
   %t2 = fmul <4 x float> %t1, %t1
   store <4 x float> %t2, <4 x float>* %a
   ret void
 }
 
-; CHECK-LABEL foo3
+; CHECK-LABEL: foo3
 define void @foo3(<8 x float>* %a) {
 ; CHECK: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
 ; CHECK-NEXT: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
   %t1 = load <8 x float>, <8 x float>* %a
   %t2 = fmul <8 x float> %t1, %t1
   store <8 x float> %t2, <8 x float>* %a
   ret void
 }
 
 
 
-; CHECK-LABEL foo4
+; CHECK-LABEL: foo4
 define void @foo4(<2 x i32>* %a) {
 ; CHECK: ld.v2.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}}
   %t1 = load <2 x i32>, <2 x i32>* %a
   %t2 = mul <2 x i32> %t1, %t1
   store <2 x i32> %t2, <2 x i32>* %a
   ret void
 }
 
-; CHECK-LABEL foo5
+; CHECK-LABEL: foo5
 define void @foo5(<4 x i32>* %a) {
 ; CHECK: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
   %t1 = load <4 x i32>, <4 x i32>* %a
   %t2 = mul <4 x i32> %t1, %t1
   store <4 x i32> %t2, <4 x i32>* %a
   ret void
 }
 
-; CHECK-LABEL foo6
+; CHECK-LABEL: foo6
 define void @foo6(<8 x i32>* %a) {
 ; CHECK: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
 ; CHECK-NEXT: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
   %t1 = load <8 x i32>, <8 x i32>* %a
   %t2 = mul <8 x i32> %t1, %t1
   store <8 x i32> %t2, <8 x i32>* %a
   ret void
 }
 
 ; The following test wasn't passing previously as the address
 ; computation was still too complex when LSV was called.
 declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #0
 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
-; CHECK-LABEL foo_complex
+; CHECK-LABEL: foo_complex
 define void @foo_complex(i8* nocapture readonly align 16 dereferenceable(134217728) %alloc0) {
   %targ0.1.typed = bitcast i8* %alloc0 to [1024 x [131072 x i8]]*
   %t0 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !range !1
   %t1 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x()
   %t2 = lshr i32 %t1, 8
   %t3 = shl nuw nsw i32 %t1, 9
   %ttile_origin.2 = and i32 %t3, 130560
   %tstart_offset_x_mul = shl nuw nsw i32 %t0, 1

llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-kill-flag.mir

 # RUN: llc -mtriple=powerpc64le--linux-gnu -stop-after ppc-pre-emit-peephole %s -o - -verify-machineinstrs | FileCheck %s
 
 ---
 # LI + XFORM -> DFORM, no killed/dead flag fixup.
 name: testKillPassUpLI1
-#CHECK : name : testKillPassUpLI1
+#CHECK: name: testKillPassUpLI1
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3, $f1, $x5
     $x3 = LI8 100
     STFSX killed $f1, $x3, $x5
     ; CHECK: STFS killed $f1, 100, $x5
     STD killed $x3, killed $x5, 100
     ; CHECK: STD killed $x3, killed $x5, 100
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 # LI + XFORM -> DFORM, fixup killed/dead flag for $x3, find no use, set def as
 # dead(LI8 is deleted).
-name : testKillPassUpLI2
+name: testKillPassUpLI2
 # CHECK: name: testKillPassUpLI2
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3, $f1, $x5
     $x3 = LI8 100
     ; CHECK-NOT: LI8
     STFSX killed $f1, killed $x3, killed $x5

llvm/test/CodeGen/PowerPC/f128-arith.ll

entry:
   %2 = bitcast fp128* %PtrF to i8*
   %add.ptr1 = getelementptr inbounds i8, i8* %2, i64 8
   %3 = bitcast i8* %add.ptr1 to fp128*
   store fp128 %1, fp128* %3, align 16
   ret void
 ; CHECK-LABEL: testLdNSt
 ; CHECK: lxvx
 ; CHECK: stxvx
-; CHECK-NEXT blr
+; CHECK-NEXT: blr
 }
 
 define void @qpSqrt(fp128* nocapture readonly %a, fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.sqrt.f128(fp128 %0)
   store fp128 %1, fp128* %res, align 16
   ret void

llvm/test/CodeGen/PowerPC/fastcc_stacksize.ll

 define linkonce_odr void @WithoutParamArea3(i8* %a, i32 signext %b) align 2 {
 entry:
   call fastcc void
       @mixedArgs(i32 signext 1, float 1.0, i32 signext 2, float 2.0,
                  i32 signext 3, i32 signext 4, i32 signext 5, i32 signext 6,
                  i32 signext 7, i32 signext 8) ret void
   ret void
 
-; CHECK-LABEL : WithoutParamArea3
+; CHECK-LABEL: WithoutParamArea3
 ; CHECK: stdu 1, -32(1)
 ; CHECK: blr
 }
 
 declare fastcc void
     @mixedArgs(i32 signext %level, float %levelf1, i32 signext %level2,
                float %levelf2, i32 signext %level3, i32 signext %level4,
                i32 signext %level5, i32 signext %level6, i32 signext %level7,
                i32 signext %level8) unnamed_addr
 
 ; Pass by value usage requiring less GPR then available
 %"myClass::Mem" = type { i8, i8, i16, i32, i32, i32, i64 }
 
 define internal fastcc void @CallPassByValue(%"myClass::Mem"* %E) align 2 {
 entry:
   call fastcc void @PassByValue(%"myClass::Mem"* byval nonnull align 8 undef);
   ret void
 
-; CHECK-LABEL : PassByValue
+; CHECK-LABEL: PassByValue
 ; CHECK: stdu 1, -32(1)
 ; CHECK: blr
 }
 
 declare dso_local fastcc void
     @PassByValue(%"myClass::Mem"* byval nocapture readonly align 8) align 2
 
 ; Verify Paramater Save Area is allocated if parameter exceed the number that
%"myClass::MemK" = type { i32, %"myClass::MemD"*, %"myClass::MemD"*, i64, i32,
               i8, %"myClass::MemA"* }
 
 define internal fastcc void @AggMemExprEmitter(%"myClass::MemK"* %E) align 2 {
 entry:
   call fastcc void @MemExprEmitterInitialization(%"myClass::MemK" *
                                                byval nonnull align 8 undef);
   ret void
 
-; CHECK-LABEL : AggMemExprEmitter
+; CHECK-LABEL: AggMemExprEmitter
 ; CHECK: stdu 1, -144(1)
 ; CHECK: blr
 }
 
 declare dso_local fastcc void
     @MemExprEmitterInitialization(%"myClass::MemK" *
                                   byval nocapture readonly align 8) align 2

llvm/test/CodeGen/PowerPC/spe.ll

 define float @test_fmul(float %a, float %b) {
 ; CHECK-LABEL: test_fmul:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    efsmul 3, 3, 4
 ; CHECK-NEXT:    blr
   entry:
   %v = fmul float %a, %b
   ret float %v
-; CHECK-LABEL @test_fmul
 }
 
 define float @test_fadd(float %a, float %b) {
 ; CHECK-LABEL: test_fadd:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    efsadd 3, 3, 4
 ; CHECK-NEXT:    blr
   entry:
   %v = fadd float %a, %b
   ret float %v
-; CHECK-LABEL @test_fadd
 }
 
 define float @test_fsub(float %a, float %b) {
 ; CHECK-LABEL: test_fsub:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    efssub 3, 3, 4
 ; CHECK-NEXT:    blr
   entry:
   %v = fsub float %a, %b
   ret float %v
-; CHECK-LABEL @test_fsub
 }
 
 define float @test_fneg(float %a) {
 ; CHECK-LABEL: test_fneg:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    efsneg 3, 3
 ; CHECK-NEXT:    blr
   entry:
   %v = fsub float -0.0, %a
   ret float %v
-
-; CHECK-LABEL @test_fneg
 }
 
 define float @test_dtos(double %a) {
 ; CHECK-LABEL: test_dtos:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    evmergelo 3, 3, 4
 ; CHECK-NEXT:    efscfd 3, 3
 ; CHECK-NEXT:    blr

llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s --check-prefixes=PPC64
 ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s --check-prefixes=PPC32
 
 define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
-; PPC64-LABEL muloti_test:
 ; PPC64-LABEL: muloti_test:
 ; PPC64:       # %bb.0: # %start
 ; PPC64-NEXT:    mulld 8, 5, 4
 ; PPC64-NEXT:    cmpdi 5, 3, 0
 ; PPC64-NEXT:    mulhdu. 9, 3, 6
 ; PPC64-NEXT:    mulld 3, 3, 6
 ; PPC64-NEXT:    mcrf 1, 0
 ; PPC64-NEXT:    add 3, 3, 8

 ; PPC32-NEXT:    lwz 23, 44(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 22, 40(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 21, 36(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 20, 32(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 0, 84(1)
 ; PPC32-NEXT:    addi 1, 1, 80
 ; PPC32-NEXT:    mtlr 0
 ; PPC32-NEXT:    blr
-; PPC32-LABEL muloti_test:
 start:
   %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
   %1 = extractvalue { i128, i1 } %0, 0
   %2 = extractvalue { i128, i1 } %0, 1
   %3 = zext i1 %2 to i8
   %4 = insertvalue { i128, i8 } undef, i128 %1, 0
   %5 = insertvalue { i128, i8 } %4, i8 %3, 1
   ret { i128, i8 } %5
 }
 
 ; Function Attrs: nounwind readnone speculatable
 declare { i128, i1 } @llvm.umul.with.overflow.i128(i128, i128) #1
 
 attributes #0 = { nounwind readnone }
 attributes #1 = { nounwind readnone speculatable }
 attributes #2 = { nounwind }

llvm/test/CodeGen/PowerPC/xray-ret-is-terminator.ll

 ; RUN: llc -verify-machineinstrs -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
 define void @ILLBeBack() #0 {
-; CHECK-LABEL @ILLBeBack
+; CHECK-LABEL: @ILLBeBack
 ; CHECK: bne {{[0-9]+}}, [[LABEL:\.[a-zA-Z0-9_]+]]
 ; CHECK: [[LABEL]]:
 ; CHECK: bl __xray_FunctionExit
 bb:
   br i1 undef, label %bb1, label %bb8
 
 bb1:
   %tmp = tail call i64 asm sideeffect "", "=&r,=*m,b,r,*m,~{cc}"(i64* nonnull undef, i64* nonnull undef, i64 1, i64* nonnull undef)

llvm/test/CodeGen/Thumb2/float-ops.ll

 ; FP-ARMv8: vseleq.f32 s0, s1, s0
   %1 = select i1 %c, float %a, float %b
   ret float %1
 }
 
 define double @select_d(double %a, double %b, i1 %c) {
 ; CHECK-LABEL: select_d:
 ; NONE: ldr{{(.w)?}}     [[REG:r[0-9]+]], [sp]
-; NONE  ands    [[REG]], [[REG]], #1
+; NONE: ands    [[REG]], [[REG]], #1
 ; NONE-DAG: moveq   r0, r2
 ; NONE-DAG: moveq   r1, r3
 ; SP: ands r0, r0, #1
 ; SP-DAG: vmov [[ALO:r[0-9]+]], [[AHI:r[0-9]+]], d0
 ; SP-DAG: vmov [[BLO:r[0-9]+]], [[BHI:r[0-9]+]], d1
 ; SP: itt ne
 ; SP-DAG: movne [[BLO]], [[ALO]]
 ; SP-DAG: movne [[BHI]], [[AHI]]
 ; SP: vmov d0, [[BLO]], [[BHI]]
 ; DP: lsls   r0, r0, #31
 ; VFP4-DP: vmovne.f64      d1, d0
 ; VFP4-DP: vmov.f64        d0, d1
 ; FP-ARMV8: vseleq.f64      d0, d1, d0
   %1 = select i1 %c, double %a, double %b
   ret double %1
 }

llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll

define void @test_void_return() {
   ; X64-LABEL: name: test_void_return
   ; X64: bb.1.entry:
   ; X64:   RET 0
 entry:
   ret void
 }
 
 define i32 * @test_memop_i32(i32 * %p1) {
-;X64    liveins: $rdi
   ; X32-LABEL: name: test_memop_i32
   ; X32: bb.1 (%ir-block.0):
   ; X32:   [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
   ; X32:   [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 16)
   ; X32:   $eax = COPY [[LOAD]](p0)
   ; X32:   RET 0, implicit $eax
   ; X64-LABEL: name: test_memop_i32
   ; X64: bb.1 (%ir-block.0):

llvm/test/CodeGen/X86/avx-vzeroupper.ll

 ; BTVER2-NEXT:    vmovups %ymm2, (%rsp) # 32-byte Spill
 ; BTVER2-NEXT:    callq do_sse
 ; BTVER2-NEXT:    vmovaps %xmm0, {{.*}}(%rip)
 ; BTVER2-NEXT:    callq do_sse
 ; BTVER2-NEXT:    vmovaps %xmm0, {{.*}}(%rip)
 ; BTVER2-NEXT:    vmovups (%rsp), %ymm0 # 32-byte Reload
 ; BTVER2-NEXT:    addq $56, %rsp
 ; BTVER2-NEXT:    retq
-; DISABLE-VZ       # %bb.0:
   %tmp = load <4 x float>, <4 x float>* @x, align 16
   %call = tail call <4 x float> @do_sse(<4 x float> %tmp) nounwind
   store <4 x float> %call, <4 x float>* @x, align 16
   %call2 = tail call <4 x float> @do_sse(<4 x float> %call) nounwind
   store <4 x float> %call2, <4 x float>* @x, align 16
   ret <8 x float> %c
 }
 

llvm/test/CodeGen/X86/inline-0bh.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
 
 ; Function Attrs: noinline nounwind
 define i32 @PR31007() {
 ; CHECK-LABEL: PR31007:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:  #APP
-; CHECK   :    addb $11, %al
+; CHECK:       addb $11, %al
 ; CHECK:       #NO_APP
 ; CHECK-NEXT:  xorl %eax, %eax
 ; CHECK-NEXT:  retq
 entry:
   call void asm sideeffect inteldialect "add al,$$0bH", "~{al},~{flags},~{dirflag},~{fpsr},~{flags}"()
   ret i32 0
 }
 

llvm/test/CodeGen/X86/scavenger.mir

bb.0:
     RETQ $eax
 ...
 ---
 # CHECK-LABEL: name: func3
 name: func3
 tracksRegLiveness: true
 body: |
   bb.0:
-    ; CHECK dead {{\$e[a-z]+}} = MOV32ri 42
+    ; CHECK: dead {{\$e[a-z]+}} = MOV32ri 42
     dead %0 : gr32 = MOV32ri 42
 ...

llvm/test/DebugInfo/MIR/X86/live-debug-values-fragments.mir

 
 # CHECK-LABEL: bb.2.bb2:
 # CHECK-NOT:  DBG_VALUE
 # CHECK:      DBG_VALUE $ax, $noreg, !{{[0-9]+}},
 # CHECK-SAME:                 !DIExpression(DW_OP_LLVM_fragment, 8, 16)
 # CHECK-NEXT: MOV32rr
 # CHECK-NEXT: ADD32ri8
 # CHECK-NEXT: DBG_VALUE $ebx, $noreg, !{{[0-9]+}},
-# CHECK-SAME                  !DIExpression(DW_OP_LLVM_fragment, 32, 32)
+# CHECK-SAME:                 !DIExpression(DW_OP_LLVM_fragment, 32, 32)
 # CHECK-NEXT: JMP_1
 
 # CHECK-LABEL: bb.3.bb3:
 # CHECK:      DBG_VALUE $ebx, $noreg, !{{[0-9]+}},
-# CHECK-SAME                  !DIExpression(DW_OP_LLVM_fragment, 32, 32)
+# CHECK-SAME:                 !DIExpression(DW_OP_LLVM_fragment, 32, 32)
 # CHECK-NEXT: DBG_VALUE $ax, $noreg, !{{[0-9]+}},
 # CHECK-SAME:                 !DIExpression(DW_OP_LLVM_fragment, 8, 16)
 # CHECK-NEXT: XOR32rr
 # CHECK-NEXT: RETQ
 
 # CHECK-LABEL: baz
 # CHECK-LABEL: bb.0.entry:
 # CHECK:      DBG_VALUE $cx,  $noreg, !{{[0-9]+}},

llvm/test/DebugInfo/X86/objc-property-void.ll

 ; RUN: llc -filetype=obj -o %t.o < %s >/dev/null 2>&1
 ; RUN: llvm-dwarfdump -v -debug-info %t.o | FileCheck %s
 
 ; CHECK: DW_TAG_structure_type
 ; CHECK:  DW_AT_APPLE_objc_complete_type
 ; CHECK:  DW_AT_name [DW_FORM_strp] ( .debug_str[0x{{[0-9a-fA-F]+}}] = "Foo")
-; CHECK   DW_AT_APPLE_runtime_class [DW_FORM_data1]       (DW_LANG_ObjC)
+; CHECK:  DW_AT_APPLE_runtime_class [DW_FORM_data1]       (DW_LANG_ObjC)
 ; CHECK: DW_TAG_APPLE_property
 ; CHECK:  DW_AT_APPLE_property_name [DW_FORM_strp] ( .debug_str[0x{{[0-9a-fA-F]+}}] = "foo")
 
 ; generated from:
 ; @interface Foo
 ; @property (nonatomic,assign,readonly) void foo;
 ; @end
 ; @implementation Foo

llvm/test/Instrumentation/AddressSanitizer/basic-msvc64.ll

 ; Test basic address sanitizer instrumentation.
 ;
 ; RUN: opt -asan -asan-module -S  < %s | FileCheck %s
 
 target triple = "x86_64-pc-windows-msvc"
 ; CHECK: @llvm.global_ctors = {{.*}}@asan.module_ctor
 
 define i32 @test_load(i32* %a) sanitize_address {
 ; First instrumentation in the function must be to load the dynamic shadow
 ; address into a local variable.
 ; CHECK-LABEL: @test_load
 ; CHECK: entry:
 ; CHECK-NEXT: %[[SHADOW:[^ ]*]] = load i64, i64* @__asan_shadow_memory_dynamic_address
 
 ; Shadow address is loaded and added into the whole offset computation.
-; CHECK add i64 %{{.*}}, %[[SHADOW] ]
+; CHECK: add i64 %{{.*}}, %[[SHADOW]]
 
 entry:
   %tmp1 = load i32, i32* %a, align 4
   ret i32 %tmp1
 }
 
 define i32 @__asan_options(i32* %a) sanitize_address {
 ; Asan functions are not instrumented. Asan function may be called by

llvm/test/Instrumentation/AddressSanitizer/force-dynamic-shadow.ll

 ; Test -asan-force-dynamic-shadow flag.
 ;
 ; RUN: opt -asan -asan-module -S -asan-force-dynamic-shadow=1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-FDS
 ; RUN: opt -asan -asan-module -S -asan-force-dynamic-shadow=0 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-NDS
 
 target triple = "x86_64-unknown-linux-gnu"
 
 define i32 @test_load(i32* %a) sanitize_address {
 ; First instrumentation in the function must be to load the dynamic shadow
 ; address into a local variable.
 ; CHECK-LABEL: @test_load
 ; CHECK: entry:
 ; CHECK-FDS-NEXT: %[[SHADOW:[^ ]*]] = load i64, i64* @__asan_shadow_memory_dynamic_address
 ; CHECK-NDS-NOT: __asan_shadow_memory_dynamic_address
 
 ; Shadow address is loaded and added into the whole offset computation.
-; CHECK-FDS add i64 %{{.*}}, %[[SHADOW] ]
+; CHECK-FDS: add i64 %{{.*}}, %[[SHADOW]]
 
 entry:
   %tmp1 = load i32, i32* %a, align 4
   ret i32 %tmp1
 }

llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll

entry:
   %1 = bitcast %struct.StructByVal* %agg.tmp2 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %1, i8* align 4 %0, i64 16, i1 false)
   call void (i32, ...) @VAArgStructFn(i32 undef, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, %struct.StructByVal* byval align 8 %agg.tmp2)
   ret void
 }
 
 attributes #0 = { "target-features"="+fxsr,+x87,-sse" }
 
-; CHECK call void @llvm.memcpy.p0i8.p0i8.i64{{.*}}@__msan_va_arg_tls {{.*}}, i64 48
+; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64{{.*}}@__msan_va_arg_tls {{.*}}, i64 48
 
 declare i32 @InnerTailCall(i32 %a)
 
 define void @MismatchedReturnTypeTailCall(i32 %a) sanitize_memory {
   %b = tail call i32 @InnerTailCall(i32 %a)
   ret void
 }
 

llvm/test/Instrumentation/SanitizerCoverage/const-cmp-tracing.ll

 ; compare (non-const, const)
   icmp slt i32 1, %a
 ; CHECK: call void @__sanitizer_cov_trace_const_cmp4(i32 1, i32 %a)
 ; CHECK-NEXT: icmp slt i32 1, %a
 
 ; compare (const, const) - should not be instrumented
   icmp slt i32 1, 0
 ; CHECK-NOT: call void @__sanitizer_cov_trace
-; CHECK icmp slt i32 1, 0
+; CHECK: icmp slt i32 1, 0
 
 ; compare variables of byte size
   %x = trunc i32 %a to i8
 
   icmp slt i8 %x, 1
 ; CHECK: call void @__sanitizer_cov_trace_const_cmp1(i8 1, i8 %x)
 ; CHECK-NEXT: icmp slt i8 %x, 1
 

llvm/test/MC/AArch64/tme-error.s

 // CHECK-NEXT: tcommit x4
 tcommit  sp
 // CHECK: error: invalid operand for instruction
 // CHECK-NEXT: tcommit sp
 
 
 tcancel
 // CHECK: error: too few operands for instruction
-// CHECK-NEXT tcancel
+// CHECK-NEXT: tcancel
 tcancel x0
 // CHECK: error: immediate must be an integer in range [0, 65535]
-// CHECK-NEXT tcancel
+// CHECK-NEXT: tcancel
 tcancel #65536
 // CHECK: error: immediate must be an integer in range [0, 65535]
 // CHECK-NEXT: tcancel #65536
 

llvm/test/MC/Disassembler/ARM/vstrldr_sys.txt

 [0x88,0xbf]
 
 # CHECK-NOSEC: vldrhi fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
 # CHECK-NOMVE: vldrhi fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
 # CHECK-NOVFP: vldrhi fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
 # CHECK: vldrhi fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
 [0x90,0xed,0x80,0x2f]
 
-# ERROR-NOSEC invalid instruction encoding
+# ERROR-NOSEC: invalid instruction encoding
 # CHECK-NOMVE: vstr fpcxts, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xef]
 # CHECK-NOVFP: vstr fpcxts, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xef]
 # CHECK: vstr fpcxts, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xef]
 [0xcc,0xed,0xff,0xef]
 
 # ERROR-NOSEC invalid instruction encoding
 # CHECK-NOMVE: vstr fpcxts, [r12, #508]! @ encoding: [0xec,0xed,0xff,0xef]
 # CHECK-NOVFP: vstr fpcxts, [r12, #508]! @ encoding: [0xec,0xed,0xff,0xef]

 
 # ERROR-NOSEC invalid instruction encoding
 # CHECK-NOMVE: vldr fpcxtns, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xcf]
 # CHECK-NOVFP: vldr fpcxtns, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xcf]
 # CHECK: vldr fpcxtns, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xcf]
 [0x7d,0xec,0x86,0xcf]
 
 # CHECK-NOSEC: vstr vpr, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0x8f]
-# ERROR-NOMVE invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
 # CHECK-NOVFP: vstr vpr, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0x8f]
 # CHECK: vstr vpr, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0x8f]
 [0xc6,0xed,0xfd,0x8f]
 
 # CHECK-NOSEC: vstr p0, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xaf]
-# ERROR-NOMVE invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
 # CHECK-NOVFP: vstr p0, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xaf]
 # CHECK: vstr p0, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xaf]
 [0x4e,0xed,0xff,0xaf]
 
 # CHECK-NOSEC: vstr vpr, [r6, #500]! @ encoding: [0xe6,0xed,0xfd,0x8f]
-# ERROR-NOMVE invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
 # CHECK-NOVFP: vstr vpr, [r6, #500]! @ encoding: [0xe6,0xed,0xfd,0x8f]
 # CHECK: vstr vpr, [r6, #500]! @ encoding: [0xe6,0xed,0xfd,0x8f]
 [0xe6,0xed,0xfd,0x8f]
 
 # CHECK-NOSEC: vstr p0, [lr, #-508]! @ encoding: [0x6e,0xed,0xff,0xaf]
-# ERROR-NOMVE invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
 # CHECK-NOVFP: vstr p0, [lr, #-508]! @ encoding: [0x6e,0xed,0xff,0xaf]
 # CHECK: vstr p0, [lr, #-508]! @ encoding: [0x6e,0xed,0xff,0xaf]
 [0x6e,0xed,0xff,0xaf]
 
 # CHECK-NOSEC: vstr vpr, [r6], #500 @ encoding: [0xe6,0xec,0xfd,0x8f]
-# ERROR-NOMVE invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
 # CHECK-NOVFP: vstr vpr, [r6], #500 @ encoding: [0xe6,0xec,0xfd,0x8f]
 # CHECK: vstr vpr, [r6], #500 @ encoding: [0xe6,0xec,0xfd,0x8f]
 [0xe6,0xec,0xfd,0x8f]
 
 # CHECK-NOSEC: vstr p0, [lr], #-508 @ encoding: [0x6e,0xec,0xff,0xaf]
-# ERROR-NOMVE invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
 # CHECK-NOVFP: vstr p0, [lr], #-508 @ encoding: [0x6e,0xec,0xff,0xaf]
 # CHECK: vstr p0, [lr], #-508 @ encoding: [0x6e,0xec,0xff,0xaf]
 [0x6e,0xec,0xff,0xaf]
 
 # CHECK-NOSEC: vstr p0, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xaf]
-# ERROR-NOMVE invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
 # CHECK-NOVFP: vstr p0, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xaf]
 # CHECK: vstr p0, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xaf]
 [0x6d,0xec,0x86,0xaf]
 
 # CHECK-NOSEC: vldr vpr, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0x8f]
-# ERROR-NOMVE invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
 # CHECK-NOVFP: vldr vpr, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0x8f]
 # CHECK: vldr vpr, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0x8f]
 [0xd6,0xed,0xfd,0x8f]
 
 # CHECK-NOSEC: vldr p0, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xaf]
-# ERROR-NOMVE invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
 # CHECK-NOVFP: vldr p0, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xaf]
 # CHECK: vldr p0, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xaf]
 [0x5e,0xed,0xff,0xaf]
 
 # CHECK-NOSEC: vldr vpr, [r6, #500]! @ encoding: [0xf6,0xed,0xfd,0x8f]
-# ERROR-NOMVE invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
 # CHECK-NOVFP: vldr vpr, [r6, #500]! @ encoding: [0xf6,0xed,0xfd,0x8f]
 # CHECK: vldr vpr, [r6, #500]! @ encoding: [0xf6,0xed,0xfd,0x8f]
 [0xf6,0xed,0xfd,0x8f]
 
 # CHECK-NOSEC: vldr p0, [lr, #-508]! @ encoding: [0x7e,0xed,0xff,0xaf]
-# ERROR-NOMVE invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
 # CHECK-NOVFP: vldr p0, [lr, #-508]! @ encoding: [0x7e,0xed,0xff,0xaf]
 # CHECK: vldr p0, [lr, #-508]! @ encoding: [0x7e,0xed,0xff,0xaf]
 [0x7e,0xed,0xff,0xaf]
 
 # CHECK-NOSEC: vldr vpr, [r6], #500 @ encoding: [0xf6,0xec,0xfd,0x8f]
-# ERROR-NOMVE invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
 # CHECK-NOVFP: vldr vpr, [r6], #500 @ encoding: [0xf6,0xec,0xfd,0x8f]
 # CHECK: vldr vpr, [r6], #500 @ encoding: [0xf6,0xec,0xfd,0x8f]
 [0xf6,0xec,0xfd,0x8f]
 
 # CHECK-NOSEC: vldr p0, [lr], #-508 @ encoding: [0x7e,0xec,0xff,0xaf]
-# ERROR-NOMVE invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
 # CHECK-NOVFP: vldr p0, [lr], #-508 @ encoding: [0x7e,0xec,0xff,0xaf]
 # CHECK: vldr p0, [lr], #-508 @ encoding: [0x7e,0xec,0xff,0xaf]
 [0x7e,0xec,0xff,0xaf]
 
 # CHECK-NOSEC: vldr p0, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xaf]
-# ERROR-NOMVE invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
 # CHECK-NOVFP: vldr p0, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xaf]
 # CHECK: vldr p0, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xaf]
 [0x7d,0xec,0x86,0xaf]
 
 # ERROR-NOSEC: invalid instruction encoding
 # ERROR-NOMVE: potentially undefined instruction encoding
 # ERROR-NOVFP: potentially undefined instruction encoding
 # ERROR: potentially undefined instruction encoding

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt

 0x10 0x43 0x22 0x41
 
 # CHECK: vmul10ecuq 2, 3, 4
 0x10 0x43 0x20 0x41
 
 #CHECK: vabsdub 2, 3, 4
 0x10 0x43 0x24 0x03
 
-#CHECK vabsduh 2, 3, 4
+#CHECK: vabsduh 2, 3, 4
 0x10 0x43 0x24 0x43
 
-#CHECK vabsduw 2, 3, 4
+#CHECK: vabsduw 2, 3, 4
 0x10 0x43 0x24 0x83
 
 # CHECK: bcdcfn. 27, 31, 1
 0x13 0x67 0xff 0x81
 
 # CHECK: bcdcfz. 27, 31, 1
 0x13 0x66 0xff 0x81
 

llvm/test/MC/Mips/mul-macro-variants.s

 # CHECK-TRAP:   multu   $5, $6                  # encoding: [0x00,0xa6,0x00,0x19]
 # CHECK-TRAP:   mfhi    $1                      # encoding: [0x00,0x00,0x08,0x10]
 # CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
 # CHECK-TRAP:   tne     $1, $zero, 6            # encoding: [0x00,0x20,0x01,0xb6]
 
  dmul $4, $5, $6
 # CHECK:        dmultu  $5, $6                  # encoding: [0x00,0xa6,0x00,0x1d]
 # CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
-# CHECK-TRAP    dmultu  $5, $6                  # encoding: [0x00,0xa6,0x00,0x1d]
+# CHECK-TRAP:   dmultu  $5, $6                  # encoding: [0x00,0xa6,0x00,0x1d]
 # CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
  dmul $4, $5, 1
 # CHECK:        addiu   $1, $zero, 1            # encoding: [0x24,0x01,0x00,0x01]
 # CHECK:        dmult   $5, $1                  # encoding: [0x00,0xa1,0x00,0x1c]
 # CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
 # CHECK-TRAP:   addiu   $1, $zero, 1            # encoding: [0x24,0x01,0x00,0x01]
 # CHECK-TRAP:   dmult   $5, $1                  # encoding: [0x00,0xa1,0x00,0x1c]
 # CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]

llvm/test/ObjectYAML/MachO/fat_macho_i386_x86_64.yaml

 #CHECK:     align:           12
 #CHECK:   - cputype:         0x01000007
 #CHECK:     cpusubtype:      0x80000003
 #CHECK:     offset:          0x0000000000005000
 #CHECK:     size:            15380
 #CHECK:     align:           12
 #CHECK: Slices:          
 #CHECK:   - !mach-o
-#CHECK      FileHeader:      
+#CHECK:     FileHeader:      
 #CHECK:       magic:           0xFEEDFACE
 #CHECK:       cputype:         0x00000007
 #CHECK:       cpusubtype:      0x00000003
 #CHECK:       filetype:        0x00000002
 #CHECK:       ncmds:           0
 #CHECK:       sizeofcmds:      0
 #CHECK:       flags:           0x01218085
 #CHECK:   - !mach-o
-#CHECK      FileHeader:        
+#CHECK:     FileHeader:        
 #CHECK:       magic:           0xFEEDFACF
 #CHECK:       cputype:         0x01000007
 #CHECK:       cpusubtype:      0x80000003
 #CHECK:       filetype:        0x00000002
 #CHECK:       ncmds:           0
 #CHECK:       sizeofcmds:      0
 #CHECK:       flags:           0x00218085
 #CHECK:       reserved:        0x00000000
 #CHECK: ...

llvm/test/Transforms/AtomicExpand/SPARC/libcalls.ll

 ; CHECK:  %4 = load i128, i128* %2, align 8
 ; CHECK:  call void @llvm.lifetime.end.p0i8(i64 16, i8* %3)
 ; CHECK:  ret i128 %4
 define i128 @test_load_i128(i128* %arg) {
   %ret = load atomic i128, i128* %arg seq_cst, align 16
   ret i128 %ret
 }
 
-; CHECK-LABEL @test_store_i128(
+; CHECK-LABEL: @test_store_i128(
 ; CHECK:  %1 = bitcast i128* %arg to i8*
 ; CHECK:  %2 = alloca i128, align 8
 ; CHECK:  %3 = bitcast i128* %2 to i8*
 ; CHECK:  call void @llvm.lifetime.start.p0i8(i64 16, i8* %3)
 ; CHECK:  store i128 %val, i128* %2, align 8
 ; CHECK:  call void @__atomic_store(i32 16, i8* %1, i8* %3, i32 5)
 ; CHECK:  call void @llvm.lifetime.end.p0i8(i64 16, i8* %3)
 ; CHECK:  ret void

llvm/test/Transforms/Attributor/nofree.ll

 ; void free_in_scc2(char*p){
 ;    free_in_scc1(p);
 ;    free(p);
 ; }
 
 
 ; ATTRIBUTOR: Function Attrs: noinline nounwind uwtable
 ; ATTRIBUTOR-NOT: nofree
-; ATTRIBUTOR-NEXT :define void @free_in_scc1(i8* nocapture %0) local_unnamed_addr
+; ATTRIBUTOR-NEXT: define void @free_in_scc1(i8* nocapture %0) local_unnamed_addr
 define void @free_in_scc1(i8* nocapture %0) local_unnamed_addr #0 {
   tail call void @free_in_scc2(i8* %0) #1
   ret void
 }
 
 
 ; ATTRIBUTOR: Function Attrs: noinline nounwind uwtable
 ; ATTRIBUTOR-NOT: nofree

llvm/test/Transforms/CallSiteSplitting/callsite-instructions-before-call.ll

 ; CHECK-LABEL: @test_firstnophi
 ; CHECK-LABEL: Header.split:
 ; CHECK-NEXT: store i32 %v, i32* %a
 ; CHECK-NEXT: %[[CALL1:.*]] = call i32 @callee(i32* null, i32 %v, i32 1)
 ; CHECK-NEXT: br label %Tail
 ; CHECK-LABEL: TBB.split:
 ; CHECK-NEXT: store i32 %v, i32* %a
 ; CHECK-NEXT: %[[CALL2:.*]] = call i32 @callee(i32* nonnull %a, i32 1, i32 2)
-; CHECK-NEXT br label %Tail
+; CHECK-NEXT: br label %Tail
 ; CHECK-LABEL: Tail:
 ; CHECK: %[[MERGED:.*]] = phi i32 [ %[[CALL1]], %Header.split ], [ %[[CALL2]], %TBB.split ]
 ; CHECK: ret i32 %[[MERGED]]
 define i32 @callee(i32* %a, i32 %v, i32 %p) {
     ret i32 0
 }
 
 define void @test_no_remove_used_phi(i32* %ptrarg, i32 %i) {

 ; NODUP-LABEL: @test_no_remove_used_phi
 ; NODUP-NOT: split
 ; CHECK-LABEL: @test_no_remove_used_phi
 ; CHECK-LABEL: Header.split:
 ; CHECK: call void @bar(i32* null, i32 %l1)
 ; CHECK-NEXT: br label %CallSite
 ; CHECK-LABEL: TBB.split:
 ; CHECK: call void @bar(i32* nonnull %ptrarg, i32 %l2)
-; CHECK-NEXT br label %CallSite
+; CHECK-NEXT: br label %CallSite
 ; CHECK-LABEL: CallSite:
 ; CHECK-NEXT:  %l = phi i32 [ %l1, %Header.split ], [ %l2, %TBB.split ]
 ; CHECK: call void @bari(i32 %l)
 
 define void @bar(i32*, i32) {
     ret void
 }
 
 define  void @bari(i32) {
     ret void
 }

llvm/test/Transforms/CodeExtractor/PartialInlineLiveAcross.ll

 declare void @foo(...) local_unnamed_addr #1
 
 ; Function Attrs: nounwind uwtable
 define i32 @dummy_caller(i32 %arg) local_unnamed_addr #0 {
 ; CHECK-LABEL: @dummy_caller
 ; CHECK: codeRepl.i:
 ; CHECK:  call void @test.1.bb2()
 ; CHECK-NOT: load
-; CHECK  br
+; CHECK:  br
 
 bb:
   %tmp = tail call i32 @test(i32 %arg)
   ret i32 %tmp
 }
 
 ; CHECK-LABEL: define internal void @test.1.bb2()
 ; CHECK: .exitStub:

llvm/test/Transforms/CodeExtractor/PartialInlineNoLiveOut.ll

 declare void @foo(...) local_unnamed_addr #0
 
 ; Function Attrs: nounwind uwtable
 define i32 @dummy_caller(i32 %arg) local_unnamed_addr #0 {
 ; CHECK-LABEL: @dummy_caller
 ; CHECK: codeRepl.i:
 ; CHECK:  call void @test.1.bb2()
 ; CHECK-NOT: load
-; CHECK  br
+; CHECK:  br
 bb:
   %tmp = tail call i32 @test(i32 %arg)
   ret i32 %tmp
 }
 
 ; CHECK-LABEL: define internal void @test.1.bb2()
 ; CHECK: .exitStub:
 ; CHECK-NOT:  store i32 %tmp7, i32* %tmp7.out

llvm/test/Transforms/EntryExitInstrumenter/mcount.ll

 entry:
   call void @leaf_function()
   ret void
 
 ; CHECK-LABEL: define void @root_function()
 ; CHECK: entry:
 ; CHECK-NEXT: call void @mcount()
 
-; CHECK-NEXT %0 = call i8* @llvm.returnaddress(i32 0)
-; CHECK-NEXT call void @__cyg_profile_func_enter(i8* bitcast (void ()* @root_function to i8*), i8* %0)
+; CHECK-NEXT: %0 = call i8* @llvm.returnaddress(i32 0)
+; CHECK-NEXT: call void @__cyg_profile_func_enter(i8* bitcast (void ()* @root_function to i8*), i8* %0)
 
 ; Entry and exit calls, inlined from @leaf_function()
-; CHECK-NEXT %1 = call i8* @llvm.returnaddress(i32 0)
-; CHECK-NEXT call void @__cyg_profile_func_enter(i8* bitcast (void ()* @leaf_function to i8*), i8* %1)
-; CHECK-NEXT %2 = call i8* @llvm.returnaddress(i32 0)
-; CHECK-NEXT call void @__cyg_profile_func_exit(i8* bitcast (void ()* @leaf_function to i8*), i8* %2)
-; CHECK-NEXT %3 = call i8* @llvm.returnaddress(i32 0)
+; CHECK-NEXT: %1 = call i8* @llvm.returnaddress(i32 0)
+; CHECK-NEXT: call void @__cyg_profile_func_enter(i8* bitcast (void ()* @leaf_function to i8*), i8* %1)
+; CHECK-NEXT: %2 = call i8* @llvm.returnaddress(i32 0)
+; CHECK-NEXT: call void @__cyg_profile_func_exit(i8* bitcast (void ()* @leaf_function to i8*), i8* %2)
+; CHECK-NEXT: %3 = call i8* @llvm.returnaddress(i32 0)
 
-; CHECK-NEXT call void @__cyg_profile_func_exit(i8* bitcast (void ()* @root_function to i8*), i8* %3)
-; CHECK-NEXT ret void
+; CHECK-NEXT: call void @__cyg_profile_func_exit(i8* bitcast (void ()* @root_function to i8*), i8* %3)
+; CHECK-NEXT: ret void
 }
 
 
 
 ; The mcount function has many different names.
 
 define void @f1() #1 { entry: ret void }
 ; CHECK-LABEL: define void @f1

llvm/test/Transforms/GuardWidening/loop-schedule.ll

 ; RUN: opt -S -licm -loop-guard-widening -licm -debug-pass=Structure < %s 2>&1   | FileCheck %s
 
 ; Main point of this test is to check the scheduling -- there should be
 ; no analysis passes needed between LICM and LoopGuardWidening
 
 ; CHECK: Loop Pass Manager
 ; CHECK:   Loop Invariant Code Motion
 ; CHECK:   Widen guards (within a single loop, as a loop pass)
 ; CHECK:   Loop Invariant Code Motion
 
 declare void @llvm.experimental.guard(i1,...)
 
 define void @iter(i32 %a, i32 %b, i1* %c_p) {
-; CHECK-LABEL @iter
+; CHECK-LABEL: @iter
 ; CHECK:  %cond_0 = icmp ult i32 %a, 10
 ; CHECK:  %cond_1 = icmp ult i32 %b, 10
 ; CHECK:  %wide.chk = and i1 %cond_0, %cond_1
 ; CHECK:  call void (i1, ...) @llvm.experimental.guard(i1 %wide.chk) [ "deopt"() ]
 ; CHECK-LABEL: loop:
 
 entry:
   %cond_0 = icmp ult i32 %a, 10

 leave.loopexit:                                   ; preds = %loop
   br label %leave
 
 leave:                                            ; preds = %leave.loopexit, %entry
   ret void
 }
 
 define void @within_loop(i32 %a, i32 %b, i1* %c_p) {
-; CHECK-LABEL @within_loop
+; CHECK-LABEL: @within_loop
 ; CHECK:  %cond_0 = icmp ult i32 %a, 10
 ; CHECK:  %cond_1 = icmp ult i32 %b, 10
 ; CHECK:  %wide.chk = and i1 %cond_0, %cond_1
 ; CHECK:  call void (i1, ...) @llvm.experimental.guard(i1 %wide.chk) [ "deopt"() ]
 ; CHECK-LABEL: loop:
 
 entry:
   br label %loop

llvm/test/Transforms/InferFunctionAttrs/norecurse_debug.ll

 !18 = !DILocation(line: 3, column: 14, scope: !2)
 !19 = !DILocation(line: 7, column: 6, scope: !2)
 !24 = !DILocation(line: 7, column: 14, scope: !2)
 !27 = !DILocation(line: 9, column: 20, scope: !2)
 !28 = !DILocation(line: 9, column: 18, scope: !2)
 !29 = !DILocation(line: 10, column: 1, scope: !2)
 
 ; CHECK: attributes #0 = { nofree norecurse nounwind }
-; CHECK-NOT foo.coefficient1
+; CHECK-NOT: foo.coefficient1

llvm/test/Transforms/InstCombine/atomic.ll

; CHECK: store atomic i64 %l1, i64* %2 seq_cst, align 8
   store atomic i8* %l, i8** %p2 seq_cst, align 8
   ret void
 }
 
 ;; At the moment, we can't form atomic vectors by folding since these are 
 ;; not representable in the IR.  This was pr29121.  The right long term
 ;; solution is to extend the IR to handle this case.
 define <2 x float> @no_atomic_vector_load(i64* %p) {
-; CHECK-LABEL @no_atomic_vector_load
+; CHECK-LABEL: @no_atomic_vector_load
 ; CHECK: load atomic i64, i64* %p unordered, align 8
   %load = load atomic i64, i64* %p unordered, align 8
   %.cast = bitcast i64 %load to <2 x float>
   ret <2 x float> %.cast
 }
 
 define void @no_atomic_vector_store(<2 x float> %p, i8* %p2) {
 ; CHECK-LABEL: @no_atomic_vector_store
 ; CHECK: store atomic i64 %1, i64* %2 unordered, align 8
   %1 = bitcast <2 x float> %p to i64
   %2 = bitcast i8* %p2 to i64*
   store atomic i64 %1, i64* %2 unordered, align 8
   ret void
 }
 
 attributes #0 = { "null-pointer-is-valid"="true" }

llvm/test/Transforms/InstCombine/debuginfo-dce2.ll

entry:
   ret void, !dbg !23
 }
 
 ; CHECK-LABEL: define void @f(i8* %p)
 ; CHECK: call void @llvm.dbg.value(metadata i8* %p, metadata ![[P_VAR:[0-9]+]], metadata !DIExpression())
 ; CHECK-NOT: bitcast
 ; CHECK: call void @llvm.dbg.value(metadata i8* %p, metadata ![[Q_VAR:[0-9]+]], metadata !DIExpression())
 ; CHECK-NOT: bitcast
-; CHECK ret void
+; CHECK: ret void
 
 ; CHECK: ![[P_VAR]] = !DILocalVariable(name: "p", {{.*}})
 ; CHECK: ![[Q_VAR]] = !DILocalVariable(name: "q", {{.*}})
 
 declare void @use_as_void(i8*)
 
 declare void @llvm.dbg.value(metadata, metadata, metadata)
 

llvm/test/Transforms/InstCombine/intptr1.ll

; CHECK-NOT: %b.addr.02 = phi i64
   %tmp = inttoptr i64 %b.addr.02 to float*
 ; CHECK-NOT: inttoptr i64
   %tmp1 = load float, float* %tmp, align 4
 ; CHECK: = load
   %mul.i = fmul float %tmp1, 4.200000e+01
   store float %mul.i, float* %a.addr.03, align 4
   %add = getelementptr inbounds float, float* %tmp, i64 1
   %add.int = ptrtoint float* %add to i64
-; CHECK %add = getelementptr
+; CHECK: %add = getelementptr
 ; CHECK-NOT: ptrtoint float*
   %incdec.ptr = getelementptr inbounds float, float* %a.addr.03, i64 1
 ; CHECK: %incdec.ptr = 
   %cmp = icmp ult float* %incdec.ptr, %a_end
   br i1 %cmp, label %for.body, label %for.end
 
 for.end:                                          ; preds = %for.body, %entry
   ret void

llvm/test/Transforms/LoopUnroll/peel-loop-negative.ll

 ; RUN: opt < %s -S -loop-unroll -unroll-threshold=800 -unroll-peel-max-count=0 | FileCheck %s
 
 ; We should not peel this loop even though we can, because the max count is set
 ; to zero.
 define i32 @invariant_backedge_neg_1(i32 %a, i32 %b) {
 ; CHECK-LABEL: @invariant_backedge_neg_1
-; CHECK-NOT    loop.peel{{.*}}:
+; CHECK-NOT:   loop.peel{{.*}}:
 ; CHECK:       loop:
 ; CHECK:         %i = phi
 ; CHECK:         %sum = phi
 ; CHECK:         %plus = phi
 entry:
   br label %loop
 
 loop:

llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll

 define void @narrowing_load_not_allowed(i8* noalias nocapture %A, i8* noalias nocapture readonly %B, i16* noalias nocapture readonly %C) #0 {
 ; CHECK-LABEL:        narrowing_load_not_allowed(
 ; PREFER-FOLDING:     vector.body:
 ; PREFER-FOLDING-NOT: llvm.masked.load
 ; PREFER-FOLDING-NOT: llvm.masked.store
 ; PREFER-FOLDING:     br i1 %{{.*}}, label %{{.*}}, label %vector.body
 
 ; FOLDING-OPT:        vector.body:
-; FOLDING-OPT         call <8 x i16> @llvm.masked.load.v8i16.p0v8i16
-; FOLDING-OPT         call <8 x i8> @llvm.masked.load.v8i8.p0v8i8
-; FOLDING-OPT         call void @llvm.masked.store.v8i8.p0v8i8
+; FOLDING-OPT:        call <8 x i16> @llvm.masked.load.v8i16.p0v8i16
+; FOLDING-OPT:        call <8 x i8> @llvm.masked.load.v8i8.p0v8i8
+; FOLDING-OPT:        call void @llvm.masked.store.v8i8.p0v8i8
 ; FOLDING-OPT:        br i1 %{{.*}}, label %{{.*}}, label %vector.body
 entry:
   br label %for.body
 
 for.cond.cleanup:                                 ; preds = %for.body
   ret void
 
 for.body:                                         ; preds = %for.body, %entry

llvm/test/Transforms/LoopVectorize/debugloc.ll

 ; CHECK:   load <2 x i32>, <2 x i32>* {{.*}}, !dbg ![[LOC]]
 ; CHECK:   add <2 x i32> {{.*}}, !dbg ![[LOC]]
 ; CHECK:   add i64 %index, 2, !dbg ![[LOC]]
 ; CHECK:   icmp eq i64 %index.next, %n.vec, !dbg ![[LOC]]
 ; CHECK: middle.block
 ; CHECK:   add <2 x i32> %{{.*}}, %rdx.shuf, !dbg ![[BR_LOC:[0-9]+]]
 ; CHECK:   extractelement <2 x i32> %bin.rdx, i32 0, !dbg ![[BR_LOC]]
 ; CHECK: for.body
-; CHECK br i1{{.*}}, label %for.body,{{.*}}, !dbg ![[BR_LOC]],
+; CHECK: br i1{{.*}}, label %for.body,{{.*}}, !dbg ![[BR_LOC]],
 ; CHECK: ![[BR_LOC]] = !DILocation(line: 5,
 
 define i32 @f(i32* nocapture %a, i32 %size) #0 !dbg !4 {
 entry:
   call void @llvm.dbg.value(metadata i32* %a, metadata !13, metadata !DIExpression()), !dbg !19
   call void @llvm.dbg.value(metadata i32 %size, metadata !14, metadata !DIExpression()), !dbg !19
   call void @llvm.dbg.value(metadata i32 0, metadata !15, metadata !DIExpression()), !dbg !20
   call void @llvm.dbg.value(metadata i32 0, metadata !16, metadata !DIExpression()), !dbg !21

llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll

 ; CHECK-LABEL: define void @cannot_sink_with_additional_user(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT:   br label %preheader
 
 ; CHECK-LABEL: preheader:                                        ; preds = %entry
 ; CHECK:  br label %for
 
 ; CHECK-LABEL: for:                                              ; preds = %for, %preheader
-; CHECK  br i1 %exitcond, label %exit, label %for
+; CHECK:  br i1 %exitcond, label %exit, label %for
 
 ; CHECK-LABEL: exit:
 ; CHECK-NEXT:    ret void
 
 entry:
   br label %preheader
 
 preheader:

 ; CHECK-LABEL: define void @cannot_sink_store(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT:   br label %preheader
 
 ; CHECK-LABEL: preheader:                                        ; preds = %entry
 ; CHECK:  br label %for
 
 ; CHECK-LABEL: for:                                              ; preds = %for, %preheader
-; CHECK  br i1 %exitcond, label %exit, label %for
+; CHECK:  br i1 %exitcond, label %exit, label %for
 
 ; CHECK-LABEL: exit:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   br label %preheader
 
 preheader:

llvm/test/Transforms/LoopVectorize/followup.ll

 }
 
 !0 = distinct !{!0, !3, !4, !5}
 !3 = !{!"llvm.loop.vectorize.followup_vectorized", !{!"FollowupVectorized"}}
 !4 = !{!"llvm.loop.vectorize.followup_epilogue", !{!"FollowupEpilogue"}}
 !5 = !{!"llvm.loop.vectorize.followup_all", !{!"FollowupAll"}}
 
 
-; CHECK-LABEL @followup(
+; CHECK-LABEL: @followup(
 
 ; CHECK-LABEL: vector.body:
 ; CHECK: br i1 %13, label %middle.block, label %vector.body, !llvm.loop ![[LOOP_VECTOR:[0-9]+]]
 ; CHECK-LABEL: for.body:
 ; CHECK: br i1 %exitcond, label %for.end.loopexit, label %for.body, !llvm.loop ![[LOOP_EPILOGUE:[0-9]+]]
 
 ; CHECK: ![[LOOP_VECTOR]] = distinct !{![[LOOP_VECTOR]], ![[FOLLOWUP_ALL:[0-9]+]], ![[FOLLOWUP_VECTORIZED:[0-9]+]]}
 ; CHECK: ![[FOLLOWUP_ALL]] = !{!"FollowupAll"}
 ; CHECK: ![[FOLLOWUP_VECTORIZED:[0-9]+]] = !{!"FollowupVectorized"}
 ; CHECK: ![[LOOP_EPILOGUE]] = distinct !{![[LOOP_EPILOGUE]], ![[FOLLOWUP_ALL]], ![[FOLLOWUP_EPILOGUE:[0-9]+]]}
 ; CHECK: ![[FOLLOWUP_EPILOGUE]] = !{!"FollowupEpilogue"}

llvm/test/Transforms/PGOProfile/icp_invoke.ll

 declare i8* @__cxa_begin_catch(i8*)
 
 declare void @__cxa_end_catch()
 
 !0 = !{!"invoke.ll:_ZL4bar1v"}
 !1 = !{!"invoke.ll:_ZL4bar2v"}
 !2 = !{!"VP", i32 0, i64 1, i64 -2732222848796217051, i64 1}
 !3 = !{!"VP", i32 0, i64 1, i64 -6116256810522035449, i64 1}
-; ICP-NOT !3 = !{!"VP", i32 0, i64 1, i64 -2732222848796217051, i64 1}
-; ICP-NOT !4 = !{!"VP", i32 0, i64 1, i64 -6116256810522035449, i64 1}
+; ICP-NOT: !3 = !{!"VP", i32 0, i64 1, i64 -2732222848796217051, i64 1}
+; ICP-NOT: !4 = !{!"VP", i32 0, i64 1, i64 -6116256810522035449, i64 1}
 ; ICP: [[BRANCH_WEIGHT]] = !{!"branch_weights", i32 1, i32 0}

llvm/test/Transforms/PGOProfile/memop_clone.ll

 ; RUN: opt < %s -pgo-memop-opt -verify-dom-info -S | FileCheck %s
 
 define i32 @test(i8* %a, i8* %b) !prof !1 {
 ; CHECK_LABEL: test
 ; CHECK: MemOP.Case.3:
 ; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* %a, i32 3, i1 false)
 ; CHECK: MemOP.Case.2:
 ; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* %a, i32 2, i1 false)
 ; CHECK: MemOP.Default:
 ; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* %a, i32 undef, i1 false)
 ; CHECK: MemOP.Case.33:
 ; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* %b, i64 3, i1 false)
-; CHECK  MemOP.Case.24:
+; CHECK: MemOP.Case.24:
 ; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* %b, i64 2, i1 false)
 ; CHECK: MemOP.Default2:
 ; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* %b, i64 undef, i1 false)
   tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* %a, i32 undef, i1 false), !prof !2
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* %b, i64 undef, i1 false), !prof !2
   unreachable
 }
 
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1)
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1)
 
 !1 = !{!"function_entry_count", i64 5170}
 !2 = !{!"VP", i32 1, i64 2585, i64 3, i64 1802, i64 2, i64 783}
 

llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll

 ; RUN: opt -S -O2 < %s | FileCheck %s -check-prefix=ENABLE
 ; RUN: opt -S -hexagon-emit-lookup-tables=true -O2 < %s | FileCheck %s -check-prefix=ENABLE
 ; RUN: opt -S -hexagon-emit-lookup-tables=false -O2 < %s | FileCheck %s -check-prefix=DISABLE
 
 
 ; ENABLE: @{{.*}} = private unnamed_addr constant [6 x i32] [i32 9, i32 20, i32 14, i32 22, i32 12, i32 5]
 ; DISABLE-NOT: @{{.*}} = private unnamed_addr constant [6 x i32] [i32 9, i32 20, i32 14, i32 22, i32 12, i32 5]
-; DISABLE : = phi i32 [ 19, %{{.*}} ], [ 5, %{{.*}} ], [ 12, %{{.*}} ], [ 22, %{{.*}} ], [ 14, %{{.*}} ], [ 20, %{{.*}} ], [ 9, %{{.*}} ]
+; DISABLE: = phi i32 [ 19, %{{.*}} ], [ 5, %{{.*}} ], [ 12, %{{.*}} ], [ 22, %{{.*}} ], [ 14, %{{.*}} ], [ 20, %{{.*}} ], [ 9, %{{.*}} ]
 
 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
 target triple = "hexagon-unknown--elf"
 
 ; Function Attrs: noinline nounwind
 define i32 @foo(i32 %x) #0 section ".tcm_text" {
 entry:
   %retval = alloca i32, align 4

llvm/test/Transforms/SimplifyCFG/pr33605.ll

 ; CHECK-NEXT: %i.0 = phi i32 [ 2, %entry ], [ %dec, %if.end ]
 ; CHECK: for.body:
 ; CHECK: br i1 %cmp, label %if.end, label %if.then
 ; CHECK-NOT: br i1 %cmp, label %for.cond, label %if.then
 ; CHECK: if.then:
 ; CHECK: br label %if.end
 ; CHECK-NOT: br label %for.cond
 ; CHECK: if.end:
-; CHECK br label %for.cond
+; CHECK: br label %for.cond
 define i1 @test(i32 %a, i32 %b, i32* %c) {
 entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %if.end, %entry
   %i.0 = phi i32 [ 2, %entry ], [ %dec, %if.end ]
   %changed.0.off0 = phi i1 [ false, %entry ], [ %changed.1.off0, %if.end ]
   %dec = add nsw i32 %i.0, -1

llvm/test/tools/llvm-dwarfdump/X86/statistics.ll

 ; +1 extra inline i.
 ; CHECK: "source variables":10
 ; -1 square::i
 ; CHECK: "variables with location":9
 ; CHECK: "scope bytes total":[[BYTES:[0-9]+]]
 ; Because of the dbg.value in the middle of the function, the pc range coverage
 ; must be below 100%.
 ; CHECK-NOT: "scope bytes covered":0
-; CHECK-NOT "scope bytes covered":[[BYTES]]
+; CHECK-NOT: "scope bytes covered":[[BYTES]]
 ; CHECK: "scope bytes covered":
 ; CHECK: "total function size":[[FUNCSIZE:[0-9]+]]
 ; CHECK: "total inlined function size":[[INLINESIZE:[0-9]+]]
 ; CHECK: "size of __debug_info":380
 ; CHECK: "size of __debug_loc":35
 ; CHECK: "size of __debug_abbrev":303
 ; CHECK: "size of __debug_line":117
 ; CHECK: "size of __debug_str":204

llvm/test/tools/llvm-profdata/value-prof.proftext

 999000
 359800
 
 #ICSUM: Statistics for indirect call sites profile:
 #ICSUM: Total number of sites: 3
 #ICSUM: Total number of sites with values: 2
 #ICSUM: Total number of profiled values: 3
 #ICSUM: NumTargets, SiteCount
-#ICSUM    1, 1
-#ICSUM    2, 1
+#ICSUM:   1, 1
+#ICSUM:   2, 1

llvm/test/tools/llvm-symbolizer/sym.test

 # CHECK-NEXT: main
 # CHECK-NEXT: {{[/\]+}}tmp{{[/\]+}}x.c:14:0
 # CHECK-EMPTY:
 # CHECK-NEXT: some text2
 #
 #PRETTY: some text
 #PRETTY: {{[0x]+}}40054d: inctwo at {{[/\]+}}tmp{{[/\]+}}x.c:3:3
 #PRETTY:  (inlined by) inc at {{[/\]+}}tmp{{[/\]+}}x.c:7:0
-#PRETTY   (inlined by) main at {{[/\]+}}tmp{{[/\]+}}x.c:14:0
+#PRETTY:  (inlined by) main at {{[/\]+}}tmp{{[/\]+}}x.c:14:0
 #PRETTY: some text2
 #
 #ZERO: ??
 #ZERO: ??:0:0
 #
 #A2L:         some text
 #A2L_A-NEXT:  0x40054d
 #A2L_F-NEXT:  inctwo