diff --git a/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp b/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
--- a/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
@@ -140,6 +140,9 @@
     assert(MO.getReg() > PPC::NoRegister &&
            MO.getReg() < PPC::NUM_TARGET_REGS &&
            "Invalid register for this target!");
+    // Ignore all implicit register operands.
+    if (MO.isImplicit())
+      return false;
     OutMO = MCOperand::createReg(MO.getReg());
     return true;
   case MachineOperand::MO_Immediate:
diff --git a/llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir b/llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir
--- a/llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir
+++ b/llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir
@@ -94,7 +94,7 @@
     renamable $cr5lt = CRNOR renamable $cr0lt, renamable $cr1gt, implicit killed $cr0
     renamable $cr5gt = COPY renamable $cr1gt, implicit $cr1
     ; CHECK: crnor 4*cr5+lt, lt, 4*cr1+gt
-    ; CHECK: cror 4*cr5+gt, 4*cr1+gt, 4*cr1+gt
+    ; CHECK: crmove 4*cr5+gt, 4*cr1+gt
     SPILL_CRBIT killed renamable $cr5lt, 0, %stack.0 :: (store 4 into %stack.0)
     renamable $cr1 = CMPW renamable $r4, renamable $r5, implicit killed $x5, implicit killed $x4
     SPILL_CRBIT killed renamable $cr5gt, 0, %stack.1 :: (store 4 into %stack.1)
diff --git a/llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll b/llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll
--- a/llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll
+++ b/llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll
@@ -13,7 +13,7 @@
 ; CHECK-P8:  # %bb.0: # %entry
 ; CHECK-P8:    lfiwzx f0, 0, r3
 ; CHECK-P8:    ld r4, .LC0@toc@l(r4)
-; CHECK-P8:    xxpermdi vs0, f0, f0, 2
+; CHECK-P8:    xxswapd vs0, f0
 ; CHECK-P8:    xxspltw v2, vs0, 3
 ; CHECK-P8:    stvx v2, 0, r4
 ; CHECK-P8:    lis r4, 1024
diff --git a/llvm/test/CodeGen/PowerPC/atomics-regression.ll b/llvm/test/CodeGen/PowerPC/atomics-regression.ll
--- a/llvm/test/CodeGen/PowerPC/atomics-regression.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics-regression.ll
@@ -400,12 +400,12 @@
 define void @test40(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test40:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
-; PPC64LE-NEXT:  .LBB40_1:
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
+; PPC64LE-NEXT:  .LBB40_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB40_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB40_1
@@ -419,12 +419,12 @@
 define void @test41(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test41:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
-; PPC64LE-NEXT:  .LBB41_1:
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
+; PPC64LE-NEXT:  .LBB41_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB41_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB41_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -441,12 +441,12 @@
 define void @test42(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test42:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
-; PPC64LE-NEXT:  .LBB42_1:
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
+; PPC64LE-NEXT:  .LBB42_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB42_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB42_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -463,13 +463,13 @@
 define void @test43(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test43:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB43_1:
+; PPC64LE-NEXT:  .LBB43_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB43_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB43_1
@@ -483,13 +483,13 @@
 define void @test44(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test44:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB44_1:
+; PPC64LE-NEXT:  .LBB44_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB44_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB44_1
@@ -503,13 +503,13 @@
 define void @test45(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test45:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB45_1:
+; PPC64LE-NEXT:  .LBB45_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB45_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB45_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -526,13 +526,13 @@
 define void @test46(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test46:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB46_1:
+; PPC64LE-NEXT:  .LBB46_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB46_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB46_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -549,13 +549,13 @@
 define void @test47(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test47:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB47_1:
+; PPC64LE-NEXT:  .LBB47_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB47_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB47_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -572,13 +572,13 @@
 define void @test48(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test48:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB48_1:
+; PPC64LE-NEXT:  .LBB48_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB48_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB48_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -595,13 +595,13 @@
 define void @test49(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test49:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB49_1:
+; PPC64LE-NEXT:  .LBB49_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB49_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB49_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -618,12 +618,12 @@
 define void @test50(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test50:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
-; PPC64LE-NEXT:  .LBB50_1:
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
+; PPC64LE-NEXT:  .LBB50_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB50_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB50_1
@@ -637,12 +637,12 @@
 define void @test51(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test51:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
-; PPC64LE-NEXT:  .LBB51_1:
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
+; PPC64LE-NEXT:  .LBB51_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB51_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB51_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -659,12 +659,12 @@
 define void @test52(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test52:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
-; PPC64LE-NEXT:  .LBB52_1:
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
+; PPC64LE-NEXT:  .LBB52_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB52_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB52_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -681,13 +681,13 @@
 define void @test53(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test53:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB53_1:
+; PPC64LE-NEXT:  .LBB53_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB53_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB53_1
@@ -701,13 +701,13 @@
 define void @test54(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test54:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB54_1:
+; PPC64LE-NEXT:  .LBB54_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB54_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB54_1
@@ -721,13 +721,13 @@
 define void @test55(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test55:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB55_1:
+; PPC64LE-NEXT:  .LBB55_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB55_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB55_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -744,13 +744,13 @@
 define void @test56(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test56:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB56_1:
+; PPC64LE-NEXT:  .LBB56_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB56_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB56_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -767,13 +767,13 @@
 define void @test57(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test57:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB57_1:
+; PPC64LE-NEXT:  .LBB57_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB57_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB57_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -790,13 +790,13 @@
 define void @test58(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test58:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB58_1:
+; PPC64LE-NEXT:  .LBB58_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB58_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB58_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -813,13 +813,13 @@
 define void @test59(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test59:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB59_1:
+; PPC64LE-NEXT:  .LBB59_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB59_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB59_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -836,11 +836,11 @@
 define void @test60(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test60:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB60_1:
+; PPC64LE-NEXT:  .LBB60_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB60_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB60_1
@@ -854,11 +854,11 @@
 define void @test61(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test61:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB61_1:
+; PPC64LE-NEXT:  .LBB61_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB61_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB61_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -875,11 +875,11 @@
 define void @test62(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test62:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB62_1:
+; PPC64LE-NEXT:  .LBB62_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB62_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB62_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -897,11 +897,11 @@
 ; PPC64LE-LABEL: test63:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB63_1:
+; PPC64LE-NEXT:  .LBB63_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB63_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB63_1
@@ -916,11 +916,11 @@
 ; PPC64LE-LABEL: test64:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB64_1:
+; PPC64LE-NEXT:  .LBB64_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB64_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB64_1
@@ -935,11 +935,11 @@
 ; PPC64LE-LABEL: test65:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB65_1:
+; PPC64LE-NEXT:  .LBB65_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB65_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB65_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -957,11 +957,11 @@
 ; PPC64LE-LABEL: test66:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB66_1:
+; PPC64LE-NEXT:  .LBB66_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB66_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB66_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -979,11 +979,11 @@
 ; PPC64LE-LABEL: test67:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB67_1:
+; PPC64LE-NEXT:  .LBB67_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB67_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB67_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1001,11 +1001,11 @@
 ; PPC64LE-LABEL: test68:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB68_1:
+; PPC64LE-NEXT:  .LBB68_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB68_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB68_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1023,11 +1023,11 @@
 ; PPC64LE-LABEL: test69:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB69_1:
+; PPC64LE-NEXT:  .LBB69_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB69_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB69_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1044,11 +1044,11 @@
 define void @test70(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test70:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB70_1:
+; PPC64LE-NEXT:  .LBB70_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB70_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB70_1
@@ -1062,11 +1062,11 @@
 define void @test71(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test71:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB71_1:
+; PPC64LE-NEXT:  .LBB71_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB71_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB71_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1083,11 +1083,11 @@
 define void @test72(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test72:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB72_1:
+; PPC64LE-NEXT:  .LBB72_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB72_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB72_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1105,11 +1105,11 @@
 ; PPC64LE-LABEL: test73:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB73_1:
+; PPC64LE-NEXT:  .LBB73_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB73_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB73_1
@@ -1124,11 +1124,11 @@
 ; PPC64LE-LABEL: test74:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB74_1:
+; PPC64LE-NEXT:  .LBB74_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB74_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB74_1
@@ -1143,11 +1143,11 @@
 ; PPC64LE-LABEL: test75:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB75_1:
+; PPC64LE-NEXT:  .LBB75_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB75_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB75_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1165,11 +1165,11 @@
 ; PPC64LE-LABEL: test76:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB76_1:
+; PPC64LE-NEXT:  .LBB76_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB76_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB76_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1187,11 +1187,11 @@
 ; PPC64LE-LABEL: test77:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB77_1:
+; PPC64LE-NEXT:  .LBB77_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB77_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB77_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1209,11 +1209,11 @@
 ; PPC64LE-LABEL: test78:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB78_1:
+; PPC64LE-NEXT:  .LBB78_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB78_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB78_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1231,11 +1231,11 @@
 ; PPC64LE-LABEL: test79:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB79_1:
+; PPC64LE-NEXT:  .LBB79_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB79_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB79_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1252,12 +1252,12 @@
 define void @test80(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test80:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
-; PPC64LE-NEXT:  .LBB80_1:
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
+; PPC64LE-NEXT:  .LBB80_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB80_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB80_1
@@ -1271,12 +1271,12 @@
 define void @test81(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test81:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
-; PPC64LE-NEXT:  .LBB81_1:
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
+; PPC64LE-NEXT:  .LBB81_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB81_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB81_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1293,12 +1293,12 @@
 define void @test82(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test82:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
-; PPC64LE-NEXT:  .LBB82_1:
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
+; PPC64LE-NEXT:  .LBB82_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB82_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB82_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1315,13 +1315,13 @@
 define void @test83(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test83:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB83_1:
+; PPC64LE-NEXT:  .LBB83_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB83_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB83_1
@@ -1335,13 +1335,13 @@
 define void @test84(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test84:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB84_1:
+; PPC64LE-NEXT:  .LBB84_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB84_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB84_1
@@ -1355,13 +1355,13 @@
 define void @test85(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test85:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB85_1:
+; PPC64LE-NEXT:  .LBB85_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB85_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB85_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1378,13 +1378,13 @@
 define void @test86(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test86:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB86_1:
+; PPC64LE-NEXT:  .LBB86_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB86_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB86_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1401,13 +1401,13 @@
 define void @test87(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test87:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB87_1:
+; PPC64LE-NEXT:  .LBB87_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB87_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB87_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1424,13 +1424,13 @@
 define void @test88(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test88:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB88_1:
+; PPC64LE-NEXT:  .LBB88_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB88_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB88_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1447,13 +1447,13 @@
 define void @test89(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test89:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 24, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB89_1:
+; PPC64LE-NEXT:  .LBB89_1: #
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB89_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB89_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1470,15 +1470,15 @@
 define void @test90(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test90:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
-; PPC64LE-NEXT:  .LBB90_1:
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
+; PPC64LE-NEXT:  .LBB90_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB90_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b 
+; PPC64LE-NEXT:    b .LBB90_1
 ; PPC64LE-NEXT:  .LBB90_3:
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
@@ -1489,12 +1489,12 @@
 define void @test91(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test91:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
-; PPC64LE-NEXT:  .LBB91_1:
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
+; PPC64LE-NEXT:  .LBB91_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB91_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB91_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1511,12 +1511,12 @@
 define void @test92(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test92:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
-; PPC64LE-NEXT:  .LBB92_1:
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
+; PPC64LE-NEXT:  .LBB92_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB92_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB92_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1533,13 +1533,13 @@
 define void @test93(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test93:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB93_1:
+; PPC64LE-NEXT:  .LBB93_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB93_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB93_1
@@ -1553,13 +1553,13 @@
 define void @test94(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test94:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB94_1:
+; PPC64LE-NEXT:  .LBB94_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB94_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB94_1
@@ -1573,13 +1573,13 @@
 define void @test95(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test95:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB95_1:
+; PPC64LE-NEXT:  .LBB95_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB95_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB95_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1596,13 +1596,13 @@
 define void @test96(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test96:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB96_1:
+; PPC64LE-NEXT:  .LBB96_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB96_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB96_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1619,13 +1619,13 @@
 define void @test97(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test97:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB97_1:
+; PPC64LE-NEXT:  .LBB97_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB97_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB97_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1642,13 +1642,13 @@
 define void @test98(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test98:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB98_1:
+; PPC64LE-NEXT:  .LBB98_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB98_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB98_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1665,13 +1665,13 @@
 define void @test99(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test99:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:    rlwinm 4, 4, 0, 16, 31
+; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB99_1:
+; PPC64LE-NEXT:  .LBB99_1: #
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB99_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB99_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1688,11 +1688,11 @@
 define void @test100(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test100:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB100_1:
+; PPC64LE-NEXT:  .LBB100_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB100_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB100_1
@@ -1706,11 +1706,11 @@
 define void @test101(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test101:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB101_1:
+; PPC64LE-NEXT:  .LBB101_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB101_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB101_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1727,11 +1727,11 @@
 define void @test102(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test102:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB102_1:
+; PPC64LE-NEXT:  .LBB102_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB102_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB102_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1749,11 +1749,11 @@
 ; PPC64LE-LABEL: test103:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB103_1:
+; PPC64LE-NEXT:  .LBB103_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB103_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB103_1
@@ -1768,11 +1768,11 @@
 ; PPC64LE-LABEL: test104:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB104_1:
+; PPC64LE-NEXT:  .LBB104_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB104_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB104_1
@@ -1787,11 +1787,11 @@
 ; PPC64LE-LABEL: test105:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB105_1:
+; PPC64LE-NEXT:  .LBB105_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB105_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB105_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1809,11 +1809,11 @@
 ; PPC64LE-LABEL: test106:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB106_1:
+; PPC64LE-NEXT:  .LBB106_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB106_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB106_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1831,11 +1831,11 @@
 ; PPC64LE-LABEL: test107:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB107_1:
+; PPC64LE-NEXT:  .LBB107_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB107_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB107_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1853,11 +1853,11 @@
 ; PPC64LE-LABEL: test108:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB108_1:
+; PPC64LE-NEXT:  .LBB108_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB108_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB108_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1875,11 +1875,11 @@
 ; PPC64LE-LABEL: test109:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB109_1:
+; PPC64LE-NEXT:  .LBB109_1: #
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB109_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB109_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1896,11 +1896,11 @@
 define void @test110(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test110:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB110_1:
+; PPC64LE-NEXT:  .LBB110_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB110_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB110_1
@@ -1914,11 +1914,11 @@
 define void @test111(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test111:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB111_1:
+; PPC64LE-NEXT:  .LBB111_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB111_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB111_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1935,11 +1935,11 @@
 define void @test112(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test112:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB112_1:
+; PPC64LE-NEXT:  .LBB112_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB112_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB112_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -1957,11 +1957,11 @@
 ; PPC64LE-LABEL: test113:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB113_1:
+; PPC64LE-NEXT:  .LBB113_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB113_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB113_1
@@ -1976,11 +1976,11 @@
 ; PPC64LE-LABEL: test114:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB114_1:
+; PPC64LE-NEXT:  .LBB114_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB114_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    beqlr 0
 ; PPC64LE-NEXT:    b .LBB114_1
@@ -1995,11 +1995,11 @@
 ; PPC64LE-LABEL: test115:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB115_1:
+; PPC64LE-NEXT:  .LBB115_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB115_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB115_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -2017,11 +2017,11 @@
 ; PPC64LE-LABEL: test116:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB116_1:
+; PPC64LE-NEXT:  .LBB116_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB116_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB116_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -2039,11 +2039,11 @@
 ; PPC64LE-LABEL: test117:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB117_1:
+; PPC64LE-NEXT:  .LBB117_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB117_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB117_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -2061,11 +2061,11 @@
 ; PPC64LE-LABEL: test118:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB118_1:
+; PPC64LE-NEXT:  .LBB118_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB118_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB118_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -2083,11 +2083,11 @@
 ; PPC64LE-LABEL: test119:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB119_1:
+; PPC64LE-NEXT:  .LBB119_1: #
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB119_4
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB119_1
 ; PPC64LE-NEXT:  # %bb.3:
@@ -2104,7 +2104,7 @@
 define i8 @test120(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test120:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB120_1:
+; PPC64LE-NEXT:  .LBB120_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB120_1
@@ -2119,7 +2119,7 @@
 ; PPC64LE-LABEL: test121:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB121_1:
+; PPC64LE-NEXT:  .LBB121_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB121_1
@@ -2134,7 +2134,7 @@
 ; PPC64LE-LABEL: test122:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB122_1:
+; PPC64LE-NEXT:  .LBB122_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB122_1
@@ -2149,7 +2149,7 @@
 ; PPC64LE-LABEL: test123:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB123_1:
+; PPC64LE-NEXT:  .LBB123_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB123_1
@@ -2165,7 +2165,7 @@
 ; PPC64LE-LABEL: test124:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB124_1:
+; PPC64LE-NEXT:  .LBB124_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB124_1
@@ -2180,7 +2180,7 @@
 define i16 @test125(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test125:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB125_1:
+; PPC64LE-NEXT:  .LBB125_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB125_1
@@ -2195,7 +2195,7 @@
 ; PPC64LE-LABEL: test126:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB126_1:
+; PPC64LE-NEXT:  .LBB126_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB126_1
@@ -2210,7 +2210,7 @@
 ; PPC64LE-LABEL: test127:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB127_1:
+; PPC64LE-NEXT:  .LBB127_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB127_1
@@ -2225,7 +2225,7 @@
 ; PPC64LE-LABEL: test128:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB128_1:
+; PPC64LE-NEXT:  .LBB128_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB128_1
@@ -2241,7 +2241,7 @@
 ; PPC64LE-LABEL: test129:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB129_1:
+; PPC64LE-NEXT:  .LBB129_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB129_1
@@ -2256,7 +2256,7 @@
 define i32 @test130(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test130:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB130_1:
+; PPC64LE-NEXT:  .LBB130_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB130_1
@@ -2271,7 +2271,7 @@
 ; PPC64LE-LABEL: test131:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB131_1:
+; PPC64LE-NEXT:  .LBB131_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB131_1
@@ -2286,7 +2286,7 @@
 ; PPC64LE-LABEL: test132:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB132_1:
+; PPC64LE-NEXT:  .LBB132_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB132_1
@@ -2301,7 +2301,7 @@
 ; PPC64LE-LABEL: test133:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB133_1:
+; PPC64LE-NEXT:  .LBB133_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB133_1
@@ -2317,7 +2317,7 @@
 ; PPC64LE-LABEL: test134:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB134_1:
+; PPC64LE-NEXT:  .LBB134_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB134_1
@@ -2332,7 +2332,7 @@
 define i64 @test135(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test135:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB135_1:
+; PPC64LE-NEXT:  .LBB135_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB135_1
@@ -2347,7 +2347,7 @@
 ; PPC64LE-LABEL: test136:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB136_1:
+; PPC64LE-NEXT:  .LBB136_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB136_1
@@ -2362,7 +2362,7 @@
 ; PPC64LE-LABEL: test137:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB137_1:
+; PPC64LE-NEXT:  .LBB137_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB137_1
@@ -2377,7 +2377,7 @@
 ; PPC64LE-LABEL: test138:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB138_1:
+; PPC64LE-NEXT:  .LBB138_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB138_1
@@ -2393,7 +2393,7 @@
 ; PPC64LE-LABEL: test139:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB139_1:
+; PPC64LE-NEXT:  .LBB139_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB139_1
@@ -2408,7 +2408,7 @@
 define i8 @test140(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test140:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB140_1:
+; PPC64LE-NEXT:  .LBB140_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -2424,7 +2424,7 @@
 ; PPC64LE-LABEL: test141:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB141_1:
+; PPC64LE-NEXT:  .LBB141_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    add 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
@@ -2440,7 +2440,7 @@
 ; PPC64LE-LABEL: test142:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB142_1:
+; PPC64LE-NEXT:  .LBB142_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -2456,7 +2456,7 @@
 ; PPC64LE-LABEL: test143:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB143_1:
+; PPC64LE-NEXT:  .LBB143_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -2473,7 +2473,7 @@
 ; PPC64LE-LABEL: test144:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB144_1:
+; PPC64LE-NEXT:  .LBB144_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -2489,7 +2489,7 @@
 define i16 @test145(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test145:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB145_1:
+; PPC64LE-NEXT:  .LBB145_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -2505,7 +2505,7 @@
 ; PPC64LE-LABEL: test146:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB146_1:
+; PPC64LE-NEXT:  .LBB146_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    add 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
@@ -2521,7 +2521,7 @@
 ; PPC64LE-LABEL: test147:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB147_1:
+; PPC64LE-NEXT:  .LBB147_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -2537,7 +2537,7 @@
 ; PPC64LE-LABEL: test148:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB148_1:
+; PPC64LE-NEXT:  .LBB148_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -2554,7 +2554,7 @@
 ; PPC64LE-LABEL: test149:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB149_1:
+; PPC64LE-NEXT:  .LBB149_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -2570,7 +2570,7 @@
 define i32 @test150(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test150:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB150_1:
+; PPC64LE-NEXT:  .LBB150_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -2586,7 +2586,7 @@
 ; PPC64LE-LABEL: test151:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB151_1:
+; PPC64LE-NEXT:  .LBB151_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    add 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
@@ -2602,7 +2602,7 @@
 ; PPC64LE-LABEL: test152:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB152_1:
+; PPC64LE-NEXT:  .LBB152_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -2618,7 +2618,7 @@
 ; PPC64LE-LABEL: test153:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB153_1:
+; PPC64LE-NEXT:  .LBB153_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -2635,7 +2635,7 @@
 ; PPC64LE-LABEL: test154:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB154_1:
+; PPC64LE-NEXT:  .LBB154_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -2651,7 +2651,7 @@
 define i64 @test155(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test155:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB155_1:
+; PPC64LE-NEXT:  .LBB155_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -2667,7 +2667,7 @@
 ; PPC64LE-LABEL: test156:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB156_1:
+; PPC64LE-NEXT:  .LBB156_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    add 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
@@ -2683,7 +2683,7 @@
 ; PPC64LE-LABEL: test157:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB157_1:
+; PPC64LE-NEXT:  .LBB157_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -2699,7 +2699,7 @@
 ; PPC64LE-LABEL: test158:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB158_1:
+; PPC64LE-NEXT:  .LBB158_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -2716,7 +2716,7 @@
 ; PPC64LE-LABEL: test159:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB159_1:
+; PPC64LE-NEXT:  .LBB159_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -2732,7 +2732,7 @@
 define i8 @test160(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test160:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB160_1:
+; PPC64LE-NEXT:  .LBB160_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -2748,7 +2748,7 @@
 ; PPC64LE-LABEL: test161:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB161_1:
+; PPC64LE-NEXT:  .LBB161_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    subf 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
@@ -2764,7 +2764,7 @@
 ; PPC64LE-LABEL: test162:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB162_1:
+; PPC64LE-NEXT:  .LBB162_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -2780,7 +2780,7 @@
 ; PPC64LE-LABEL: test163:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB163_1:
+; PPC64LE-NEXT:  .LBB163_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -2797,7 +2797,7 @@
 ; PPC64LE-LABEL: test164:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB164_1:
+; PPC64LE-NEXT:  .LBB164_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -2813,7 +2813,7 @@
 define i16 @test165(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test165:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB165_1:
+; PPC64LE-NEXT:  .LBB165_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -2829,7 +2829,7 @@
 ; PPC64LE-LABEL: test166:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB166_1:
+; PPC64LE-NEXT:  .LBB166_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    subf 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
@@ -2845,7 +2845,7 @@
 ; PPC64LE-LABEL: test167:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB167_1:
+; PPC64LE-NEXT:  .LBB167_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -2861,7 +2861,7 @@
 ; PPC64LE-LABEL: test168:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB168_1:
+; PPC64LE-NEXT:  .LBB168_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -2878,7 +2878,7 @@
 ; PPC64LE-LABEL: test169:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB169_1:
+; PPC64LE-NEXT:  .LBB169_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -2894,7 +2894,7 @@
 define i32 @test170(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test170:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB170_1:
+; PPC64LE-NEXT:  .LBB170_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -2910,7 +2910,7 @@
 ; PPC64LE-LABEL: test171:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB171_1:
+; PPC64LE-NEXT:  .LBB171_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    subf 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
@@ -2926,7 +2926,7 @@
 ; PPC64LE-LABEL: test172:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB172_1:
+; PPC64LE-NEXT:  .LBB172_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -2942,7 +2942,7 @@
 ; PPC64LE-LABEL: test173:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB173_1:
+; PPC64LE-NEXT:  .LBB173_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -2959,7 +2959,7 @@
 ; PPC64LE-LABEL: test174:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB174_1:
+; PPC64LE-NEXT:  .LBB174_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -2975,7 +2975,7 @@
 define i64 @test175(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test175:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB175_1:
+; PPC64LE-NEXT:  .LBB175_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -2991,7 +2991,7 @@
 ; PPC64LE-LABEL: test176:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB176_1:
+; PPC64LE-NEXT:  .LBB176_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
@@ -3007,7 +3007,7 @@
 ; PPC64LE-LABEL: test177:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB177_1:
+; PPC64LE-NEXT:  .LBB177_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -3023,7 +3023,7 @@
 ; PPC64LE-LABEL: test178:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB178_1:
+; PPC64LE-NEXT:  .LBB178_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -3040,7 +3040,7 @@
 ; PPC64LE-LABEL: test179:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB179_1:
+; PPC64LE-NEXT:  .LBB179_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -3056,7 +3056,7 @@
 define i8 @test180(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test180:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB180_1:
+; PPC64LE-NEXT:  .LBB180_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -3072,7 +3072,7 @@
 ; PPC64LE-LABEL: test181:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB181_1:
+; PPC64LE-NEXT:  .LBB181_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    and 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
@@ -3088,7 +3088,7 @@
 ; PPC64LE-LABEL: test182:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB182_1:
+; PPC64LE-NEXT:  .LBB182_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -3104,7 +3104,7 @@
 ; PPC64LE-LABEL: test183:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB183_1:
+; PPC64LE-NEXT:  .LBB183_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -3121,7 +3121,7 @@
 ; PPC64LE-LABEL: test184:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB184_1:
+; PPC64LE-NEXT:  .LBB184_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -3137,7 +3137,7 @@
 define i16 @test185(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test185:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB185_1:
+; PPC64LE-NEXT:  .LBB185_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -3153,7 +3153,7 @@
 ; PPC64LE-LABEL: test186:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB186_1:
+; PPC64LE-NEXT:  .LBB186_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    and 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
@@ -3169,7 +3169,7 @@
 ; PPC64LE-LABEL: test187:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB187_1:
+; PPC64LE-NEXT:  .LBB187_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -3185,7 +3185,7 @@
 ; PPC64LE-LABEL: test188:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB188_1:
+; PPC64LE-NEXT:  .LBB188_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -3202,7 +3202,7 @@
 ; PPC64LE-LABEL: test189:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB189_1:
+; PPC64LE-NEXT:  .LBB189_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -3218,7 +3218,7 @@
 define i32 @test190(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test190:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB190_1:
+; PPC64LE-NEXT:  .LBB190_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -3234,7 +3234,7 @@
 ; PPC64LE-LABEL: test191:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB191_1:
+; PPC64LE-NEXT:  .LBB191_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    and 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
@@ -3250,7 +3250,7 @@
 ; PPC64LE-LABEL: test192:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB192_1:
+; PPC64LE-NEXT:  .LBB192_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -3266,7 +3266,7 @@
 ; PPC64LE-LABEL: test193:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB193_1:
+; PPC64LE-NEXT:  .LBB193_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -3283,7 +3283,7 @@
 ; PPC64LE-LABEL: test194:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB194_1:
+; PPC64LE-NEXT:  .LBB194_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -3299,7 +3299,7 @@
 define i64 @test195(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test195:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB195_1:
+; PPC64LE-NEXT:  .LBB195_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -3315,7 +3315,7 @@
 ; PPC64LE-LABEL: test196:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB196_1:
+; PPC64LE-NEXT:  .LBB196_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    and 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
@@ -3331,7 +3331,7 @@
 ; PPC64LE-LABEL: test197:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB197_1:
+; PPC64LE-NEXT:  .LBB197_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -3347,7 +3347,7 @@
 ; PPC64LE-LABEL: test198:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB198_1:
+; PPC64LE-NEXT:  .LBB198_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -3364,7 +3364,7 @@
 ; PPC64LE-LABEL: test199:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB199_1:
+; PPC64LE-NEXT:  .LBB199_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -3380,7 +3380,7 @@
 define i8 @test200(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test200:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB200_1:
+; PPC64LE-NEXT:  .LBB200_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -3396,7 +3396,7 @@
 ; PPC64LE-LABEL: test201:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB201_1:
+; PPC64LE-NEXT:  .LBB201_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    nand 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
@@ -3412,7 +3412,7 @@
 ; PPC64LE-LABEL: test202:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB202_1:
+; PPC64LE-NEXT:  .LBB202_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -3428,7 +3428,7 @@
 ; PPC64LE-LABEL: test203:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB203_1:
+; PPC64LE-NEXT:  .LBB203_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -3445,7 +3445,7 @@
 ; PPC64LE-LABEL: test204:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB204_1:
+; PPC64LE-NEXT:  .LBB204_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -3461,7 +3461,7 @@
 define i16 @test205(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test205:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB205_1:
+; PPC64LE-NEXT:  .LBB205_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -3477,7 +3477,7 @@
 ; PPC64LE-LABEL: test206:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB206_1:
+; PPC64LE-NEXT:  .LBB206_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    nand 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
@@ -3493,7 +3493,7 @@
 ; PPC64LE-LABEL: test207:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB207_1:
+; PPC64LE-NEXT:  .LBB207_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -3509,7 +3509,7 @@
 ; PPC64LE-LABEL: test208:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB208_1:
+; PPC64LE-NEXT:  .LBB208_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -3526,7 +3526,7 @@
 ; PPC64LE-LABEL: test209:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB209_1:
+; PPC64LE-NEXT:  .LBB209_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -3542,7 +3542,7 @@
 define i32 @test210(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test210:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB210_1:
+; PPC64LE-NEXT:  .LBB210_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -3558,7 +3558,7 @@
 ; PPC64LE-LABEL: test211:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB211_1:
+; PPC64LE-NEXT:  .LBB211_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    nand 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
@@ -3574,7 +3574,7 @@
 ; PPC64LE-LABEL: test212:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB212_1:
+; PPC64LE-NEXT:  .LBB212_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -3590,7 +3590,7 @@
 ; PPC64LE-LABEL: test213:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB213_1:
+; PPC64LE-NEXT:  .LBB213_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -3607,7 +3607,7 @@
 ; PPC64LE-LABEL: test214:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB214_1:
+; PPC64LE-NEXT:  .LBB214_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -3623,7 +3623,7 @@
 define i64 @test215(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test215:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB215_1:
+; PPC64LE-NEXT:  .LBB215_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -3639,7 +3639,7 @@
 ; PPC64LE-LABEL: test216:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB216_1:
+; PPC64LE-NEXT:  .LBB216_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    nand 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
@@ -3655,7 +3655,7 @@
 ; PPC64LE-LABEL: test217:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB217_1:
+; PPC64LE-NEXT:  .LBB217_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -3671,7 +3671,7 @@
 ; PPC64LE-LABEL: test218:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB218_1:
+; PPC64LE-NEXT:  .LBB218_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -3688,7 +3688,7 @@
 ; PPC64LE-LABEL: test219:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB219_1:
+; PPC64LE-NEXT:  .LBB219_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -3704,7 +3704,7 @@
 define i8 @test220(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test220:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB220_1:
+; PPC64LE-NEXT:  .LBB220_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -3720,7 +3720,7 @@
 ; PPC64LE-LABEL: test221:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB221_1:
+; PPC64LE-NEXT:  .LBB221_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    or 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
@@ -3736,7 +3736,7 @@
 ; PPC64LE-LABEL: test222:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB222_1:
+; PPC64LE-NEXT:  .LBB222_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -3752,7 +3752,7 @@
 ; PPC64LE-LABEL: test223:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB223_1:
+; PPC64LE-NEXT:  .LBB223_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -3769,7 +3769,7 @@
 ; PPC64LE-LABEL: test224:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB224_1:
+; PPC64LE-NEXT:  .LBB224_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -3785,7 +3785,7 @@
 define i16 @test225(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test225:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB225_1:
+; PPC64LE-NEXT:  .LBB225_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -3801,7 +3801,7 @@
 ; PPC64LE-LABEL: test226:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB226_1:
+; PPC64LE-NEXT:  .LBB226_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    or 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
@@ -3817,7 +3817,7 @@
 ; PPC64LE-LABEL: test227:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB227_1:
+; PPC64LE-NEXT:  .LBB227_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -3833,7 +3833,7 @@
 ; PPC64LE-LABEL: test228:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB228_1:
+; PPC64LE-NEXT:  .LBB228_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -3850,7 +3850,7 @@
 ; PPC64LE-LABEL: test229:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB229_1:
+; PPC64LE-NEXT:  .LBB229_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -3866,7 +3866,7 @@
 define i32 @test230(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test230:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB230_1:
+; PPC64LE-NEXT:  .LBB230_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -3882,7 +3882,7 @@
 ; PPC64LE-LABEL: test231:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB231_1:
+; PPC64LE-NEXT:  .LBB231_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    or 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
@@ -3898,7 +3898,7 @@
 ; PPC64LE-LABEL: test232:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB232_1:
+; PPC64LE-NEXT:  .LBB232_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -3914,7 +3914,7 @@
 ; PPC64LE-LABEL: test233:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB233_1:
+; PPC64LE-NEXT:  .LBB233_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -3931,7 +3931,7 @@
 ; PPC64LE-LABEL: test234:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB234_1:
+; PPC64LE-NEXT:  .LBB234_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -3947,7 +3947,7 @@
 define i64 @test235(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test235:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB235_1:
+; PPC64LE-NEXT:  .LBB235_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -3963,7 +3963,7 @@
 ; PPC64LE-LABEL: test236:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB236_1:
+; PPC64LE-NEXT:  .LBB236_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    or 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
@@ -3979,7 +3979,7 @@
 ; PPC64LE-LABEL: test237:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB237_1:
+; PPC64LE-NEXT:  .LBB237_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -3995,7 +3995,7 @@
 ; PPC64LE-LABEL: test238:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB238_1:
+; PPC64LE-NEXT:  .LBB238_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -4012,7 +4012,7 @@
 ; PPC64LE-LABEL: test239:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB239_1:
+; PPC64LE-NEXT:  .LBB239_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -4028,7 +4028,7 @@
 define i8 @test240(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test240:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB240_1:
+; PPC64LE-NEXT:  .LBB240_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -4044,7 +4044,7 @@
 ; PPC64LE-LABEL: test241:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB241_1:
+; PPC64LE-NEXT:  .LBB241_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    xor 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
@@ -4060,7 +4060,7 @@
 ; PPC64LE-LABEL: test242:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB242_1:
+; PPC64LE-NEXT:  .LBB242_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -4076,7 +4076,7 @@
 ; PPC64LE-LABEL: test243:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB243_1:
+; PPC64LE-NEXT:  .LBB243_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -4093,7 +4093,7 @@
 ; PPC64LE-LABEL: test244:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB244_1:
+; PPC64LE-NEXT:  .LBB244_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -4109,7 +4109,7 @@
 define i16 @test245(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test245:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB245_1:
+; PPC64LE-NEXT:  .LBB245_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -4125,7 +4125,7 @@
 ; PPC64LE-LABEL: test246:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB246_1:
+; PPC64LE-NEXT:  .LBB246_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    xor 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
@@ -4141,7 +4141,7 @@
 ; PPC64LE-LABEL: test247:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB247_1:
+; PPC64LE-NEXT:  .LBB247_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -4157,7 +4157,7 @@
 ; PPC64LE-LABEL: test248:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB248_1:
+; PPC64LE-NEXT:  .LBB248_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -4174,7 +4174,7 @@
 ; PPC64LE-LABEL: test249:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB249_1:
+; PPC64LE-NEXT:  .LBB249_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -4190,7 +4190,7 @@
 define i32 @test250(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test250:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB250_1:
+; PPC64LE-NEXT:  .LBB250_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -4206,7 +4206,7 @@
 ; PPC64LE-LABEL: test251:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB251_1:
+; PPC64LE-NEXT:  .LBB251_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    xor 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
@@ -4222,7 +4222,7 @@
 ; PPC64LE-LABEL: test252:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB252_1:
+; PPC64LE-NEXT:  .LBB252_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -4238,7 +4238,7 @@
 ; PPC64LE-LABEL: test253:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB253_1:
+; PPC64LE-NEXT:  .LBB253_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -4255,7 +4255,7 @@
 ; PPC64LE-LABEL: test254:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB254_1:
+; PPC64LE-NEXT:  .LBB254_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -4271,7 +4271,7 @@
 define i64 @test255(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test255:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB255_1:
+; PPC64LE-NEXT:  .LBB255_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -4287,7 +4287,7 @@
 ; PPC64LE-LABEL: test256:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB256_1:
+; PPC64LE-NEXT:  .LBB256_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    xor 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
@@ -4303,7 +4303,7 @@
 ; PPC64LE-LABEL: test257:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB257_1:
+; PPC64LE-NEXT:  .LBB257_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -4319,7 +4319,7 @@
 ; PPC64LE-LABEL: test258:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB258_1:
+; PPC64LE-NEXT:  .LBB258_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -4336,7 +4336,7 @@
 ; PPC64LE-LABEL: test259:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB259_1:
+; PPC64LE-NEXT:  .LBB259_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -4352,12 +4352,12 @@
 define i8 @test260(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test260:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB260_1:
+; PPC64LE-NEXT:  .LBB260_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB260_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB260_1
 ; PPC64LE-NEXT:  .LBB260_3:
@@ -4371,12 +4371,12 @@
 ; PPC64LE-LABEL: test261:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB261_1:
+; PPC64LE-NEXT:  .LBB261_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    extsb 6, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB261_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB261_1
 ; PPC64LE-NEXT:  .LBB261_3:
@@ -4390,12 +4390,12 @@
 ; PPC64LE-LABEL: test262:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB262_1:
+; PPC64LE-NEXT:  .LBB262_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB262_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB262_1
 ; PPC64LE-NEXT:  .LBB262_3:
@@ -4409,12 +4409,12 @@
 ; PPC64LE-LABEL: test263:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB263_1:
+; PPC64LE-NEXT:  .LBB263_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB263_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB263_1
 ; PPC64LE-NEXT:  .LBB263_3:
@@ -4429,12 +4429,12 @@
 ; PPC64LE-LABEL: test264:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB264_1:
+; PPC64LE-NEXT:  .LBB264_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB264_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB264_1
 ; PPC64LE-NEXT:  .LBB264_3:
@@ -4448,12 +4448,12 @@
 define i16 @test265(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test265:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB265_1:
+; PPC64LE-NEXT:  .LBB265_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB265_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB265_1
 ; PPC64LE-NEXT:  .LBB265_3:
@@ -4467,12 +4467,12 @@
 ; PPC64LE-LABEL: test266:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB266_1:
+; PPC64LE-NEXT:  .LBB266_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    extsh 6, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB266_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB266_1
 ; PPC64LE-NEXT:  .LBB266_3:
@@ -4486,12 +4486,12 @@
 ; PPC64LE-LABEL: test267:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB267_1:
+; PPC64LE-NEXT:  .LBB267_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB267_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB267_1
 ; PPC64LE-NEXT:  .LBB267_3:
@@ -4505,12 +4505,12 @@
 ; PPC64LE-LABEL: test268:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB268_1:
+; PPC64LE-NEXT:  .LBB268_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB268_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB268_1
 ; PPC64LE-NEXT:  .LBB268_3:
@@ -4525,12 +4525,12 @@
 ; PPC64LE-LABEL: test269:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB269_1:
+; PPC64LE-NEXT:  .LBB269_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB269_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB269_1
 ; PPC64LE-NEXT:  .LBB269_3:
@@ -4544,11 +4544,11 @@
 define i32 @test270(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test270:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB270_1:
+; PPC64LE-NEXT:  .LBB270_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB270_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB270_1
 ; PPC64LE-NEXT:  .LBB270_3:
@@ -4562,11 +4562,11 @@
 ; PPC64LE-LABEL: test271:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB271_1:
+; PPC64LE-NEXT:  .LBB271_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpw 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB271_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB271_1
 ; PPC64LE-NEXT:  .LBB271_3:
@@ -4580,11 +4580,11 @@
 ; PPC64LE-LABEL: test272:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB272_1:
+; PPC64LE-NEXT:  .LBB272_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB272_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB272_1
 ; PPC64LE-NEXT:  .LBB272_3:
@@ -4598,11 +4598,11 @@
 ; PPC64LE-LABEL: test273:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB273_1:
+; PPC64LE-NEXT:  .LBB273_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB273_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB273_1
 ; PPC64LE-NEXT:  .LBB273_3:
@@ -4617,11 +4617,11 @@
 ; PPC64LE-LABEL: test274:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB274_1:
+; PPC64LE-NEXT:  .LBB274_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB274_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB274_1
 ; PPC64LE-NEXT:  .LBB274_3:
@@ -4635,11 +4635,11 @@
 define i64 @test275(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test275:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB275_1:
+; PPC64LE-NEXT:  .LBB275_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB275_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB275_1
 ; PPC64LE-NEXT:  .LBB275_3:
@@ -4653,11 +4653,11 @@
 ; PPC64LE-LABEL: test276:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB276_1:
+; PPC64LE-NEXT:  .LBB276_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpd 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB276_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB276_1
 ; PPC64LE-NEXT:  .LBB276_3:
@@ -4671,11 +4671,11 @@
 ; PPC64LE-LABEL: test277:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB277_1:
+; PPC64LE-NEXT:  .LBB277_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB277_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB277_1
 ; PPC64LE-NEXT:  .LBB277_3:
@@ -4689,11 +4689,11 @@
 ; PPC64LE-LABEL: test278:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB278_1:
+; PPC64LE-NEXT:  .LBB278_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB278_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB278_1
 ; PPC64LE-NEXT:  .LBB278_3:
@@ -4708,11 +4708,11 @@
 ; PPC64LE-LABEL: test279:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB279_1:
+; PPC64LE-NEXT:  .LBB279_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB279_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB279_1
 ; PPC64LE-NEXT:  .LBB279_3:
@@ -4726,12 +4726,12 @@
 define i8 @test280(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test280:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB280_1:
+; PPC64LE-NEXT:  .LBB280_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB280_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB280_1
 ; PPC64LE-NEXT:  .LBB280_3:
@@ -4745,12 +4745,12 @@
 ; PPC64LE-LABEL: test281:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB281_1:
+; PPC64LE-NEXT:  .LBB281_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    extsb 6, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB281_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB281_1
 ; PPC64LE-NEXT:  .LBB281_3:
@@ -4764,12 +4764,12 @@
 ; PPC64LE-LABEL: test282:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB282_1:
+; PPC64LE-NEXT:  .LBB282_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB282_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB282_1
 ; PPC64LE-NEXT:  .LBB282_3:
@@ -4783,12 +4783,12 @@
 ; PPC64LE-LABEL: test283:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB283_1:
+; PPC64LE-NEXT:  .LBB283_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB283_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB283_1
 ; PPC64LE-NEXT:  .LBB283_3:
@@ -4803,12 +4803,12 @@
 ; PPC64LE-LABEL: test284:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB284_1:
+; PPC64LE-NEXT:  .LBB284_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB284_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB284_1
 ; PPC64LE-NEXT:  .LBB284_3:
@@ -4822,12 +4822,12 @@
 define i16 @test285(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test285:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB285_1:
+; PPC64LE-NEXT:  .LBB285_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB285_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB285_1
 ; PPC64LE-NEXT:  .LBB285_3:
@@ -4841,12 +4841,12 @@
 ; PPC64LE-LABEL: test286:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB286_1:
+; PPC64LE-NEXT:  .LBB286_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    extsh 6, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB286_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB286_1
 ; PPC64LE-NEXT:  .LBB286_3:
@@ -4860,12 +4860,12 @@
 ; PPC64LE-LABEL: test287:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB287_1:
+; PPC64LE-NEXT:  .LBB287_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB287_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB287_1
 ; PPC64LE-NEXT:  .LBB287_3:
@@ -4879,12 +4879,12 @@
 ; PPC64LE-LABEL: test288:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB288_1:
+; PPC64LE-NEXT:  .LBB288_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB288_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB288_1
 ; PPC64LE-NEXT:  .LBB288_3:
@@ -4899,12 +4899,12 @@
 ; PPC64LE-LABEL: test289:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB289_1:
+; PPC64LE-NEXT:  .LBB289_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB289_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB289_1
 ; PPC64LE-NEXT:  .LBB289_3:
@@ -4918,11 +4918,11 @@
 define i32 @test290(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test290:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB290_1:
+; PPC64LE-NEXT:  .LBB290_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB290_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB290_1
 ; PPC64LE-NEXT:  .LBB290_3:
@@ -4936,11 +4936,11 @@
 ; PPC64LE-LABEL: test291:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB291_1:
+; PPC64LE-NEXT:  .LBB291_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpw 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB291_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB291_1
 ; PPC64LE-NEXT:  .LBB291_3:
@@ -4954,11 +4954,11 @@
 ; PPC64LE-LABEL: test292:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB292_1:
+; PPC64LE-NEXT:  .LBB292_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB292_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB292_1
 ; PPC64LE-NEXT:  .LBB292_3:
@@ -4972,11 +4972,11 @@
 ; PPC64LE-LABEL: test293:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB293_1:
+; PPC64LE-NEXT:  .LBB293_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB293_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB293_1
 ; PPC64LE-NEXT:  .LBB293_3:
@@ -4991,11 +4991,11 @@
 ; PPC64LE-LABEL: test294:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB294_1:
+; PPC64LE-NEXT:  .LBB294_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB294_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB294_1
 ; PPC64LE-NEXT:  .LBB294_3:
@@ -5009,11 +5009,11 @@
 define i64 @test295(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test295:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB295_1:
+; PPC64LE-NEXT:  .LBB295_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB295_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB295_1
 ; PPC64LE-NEXT:  .LBB295_3:
@@ -5027,11 +5027,11 @@
 ; PPC64LE-LABEL: test296:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB296_1:
+; PPC64LE-NEXT:  .LBB296_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpd 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB296_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB296_1
 ; PPC64LE-NEXT:  .LBB296_3:
@@ -5045,11 +5045,11 @@
 ; PPC64LE-LABEL: test297:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB297_1:
+; PPC64LE-NEXT:  .LBB297_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB297_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB297_1
 ; PPC64LE-NEXT:  .LBB297_3:
@@ -5063,11 +5063,11 @@
 ; PPC64LE-LABEL: test298:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB298_1:
+; PPC64LE-NEXT:  .LBB298_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB298_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB298_1
 ; PPC64LE-NEXT:  .LBB298_3:
@@ -5082,11 +5082,11 @@
 ; PPC64LE-LABEL: test299:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB299_1:
+; PPC64LE-NEXT:  .LBB299_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB299_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB299_1
 ; PPC64LE-NEXT:  .LBB299_3:
@@ -5100,11 +5100,11 @@
 define i8 @test300(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test300:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB300_1:
+; PPC64LE-NEXT:  .LBB300_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB300_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB300_1
 ; PPC64LE-NEXT:  .LBB300_3:
@@ -5118,11 +5118,11 @@
 ; PPC64LE-LABEL: test301:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB301_1:
+; PPC64LE-NEXT:  .LBB301_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB301_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB301_1
 ; PPC64LE-NEXT:  .LBB301_3:
@@ -5136,11 +5136,11 @@
 ; PPC64LE-LABEL: test302:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB302_1:
+; PPC64LE-NEXT:  .LBB302_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB302_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB302_1
 ; PPC64LE-NEXT:  .LBB302_3:
@@ -5154,11 +5154,11 @@
 ; PPC64LE-LABEL: test303:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB303_1:
+; PPC64LE-NEXT:  .LBB303_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB303_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB303_1
 ; PPC64LE-NEXT:  .LBB303_3:
@@ -5173,11 +5173,11 @@
 ; PPC64LE-LABEL: test304:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB304_1:
+; PPC64LE-NEXT:  .LBB304_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB304_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB304_1
 ; PPC64LE-NEXT:  .LBB304_3:
@@ -5191,11 +5191,11 @@
 define i16 @test305(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test305:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB305_1:
+; PPC64LE-NEXT:  .LBB305_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB305_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB305_1
 ; PPC64LE-NEXT:  .LBB305_3:
@@ -5209,11 +5209,11 @@
 ; PPC64LE-LABEL: test306:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB306_1:
+; PPC64LE-NEXT:  .LBB306_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB306_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB306_1
 ; PPC64LE-NEXT:  .LBB306_3:
@@ -5227,11 +5227,11 @@
 ; PPC64LE-LABEL: test307:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB307_1:
+; PPC64LE-NEXT:  .LBB307_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB307_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB307_1
 ; PPC64LE-NEXT:  .LBB307_3:
@@ -5245,11 +5245,11 @@
 ; PPC64LE-LABEL: test308:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB308_1:
+; PPC64LE-NEXT:  .LBB308_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB308_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB308_1
 ; PPC64LE-NEXT:  .LBB308_3:
@@ -5264,11 +5264,11 @@
 ; PPC64LE-LABEL: test309:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB309_1:
+; PPC64LE-NEXT:  .LBB309_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB309_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB309_1
 ; PPC64LE-NEXT:  .LBB309_3:
@@ -5282,11 +5282,11 @@
 define i32 @test310(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test310:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB310_1:
+; PPC64LE-NEXT:  .LBB310_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB310_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB310_1
 ; PPC64LE-NEXT:  .LBB310_3:
@@ -5300,11 +5300,11 @@
 ; PPC64LE-LABEL: test311:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB311_1:
+; PPC64LE-NEXT:  .LBB311_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB311_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB311_1
 ; PPC64LE-NEXT:  .LBB311_3:
@@ -5318,11 +5318,11 @@
 ; PPC64LE-LABEL: test312:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB312_1:
+; PPC64LE-NEXT:  .LBB312_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB312_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB312_1
 ; PPC64LE-NEXT:  .LBB312_3:
@@ -5336,11 +5336,11 @@
 ; PPC64LE-LABEL: test313:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB313_1:
+; PPC64LE-NEXT:  .LBB313_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB313_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB313_1
 ; PPC64LE-NEXT:  .LBB313_3:
@@ -5355,11 +5355,11 @@
 ; PPC64LE-LABEL: test314:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB314_1:
+; PPC64LE-NEXT:  .LBB314_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB314_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB314_1
 ; PPC64LE-NEXT:  .LBB314_3:
@@ -5373,11 +5373,11 @@
 define i64 @test315(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test315:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB315_1:
+; PPC64LE-NEXT:  .LBB315_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB315_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB315_1
 ; PPC64LE-NEXT:  .LBB315_3:
@@ -5391,11 +5391,11 @@
 ; PPC64LE-LABEL: test316:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB316_1:
+; PPC64LE-NEXT:  .LBB316_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpld 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB316_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB316_1
 ; PPC64LE-NEXT:  .LBB316_3:
@@ -5409,11 +5409,11 @@
 ; PPC64LE-LABEL: test317:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB317_1:
+; PPC64LE-NEXT:  .LBB317_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB317_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB317_1
 ; PPC64LE-NEXT:  .LBB317_3:
@@ -5427,11 +5427,11 @@
 ; PPC64LE-LABEL: test318:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB318_1:
+; PPC64LE-NEXT:  .LBB318_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB318_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB318_1
 ; PPC64LE-NEXT:  .LBB318_3:
@@ -5446,11 +5446,11 @@
 ; PPC64LE-LABEL: test319:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB319_1:
+; PPC64LE-NEXT:  .LBB319_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB319_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB319_1
 ; PPC64LE-NEXT:  .LBB319_3:
@@ -5464,11 +5464,11 @@
 define i8 @test320(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test320:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB320_1:
+; PPC64LE-NEXT:  .LBB320_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB320_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB320_1
 ; PPC64LE-NEXT:  .LBB320_3:
@@ -5482,11 +5482,11 @@
 ; PPC64LE-LABEL: test321:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB321_1:
+; PPC64LE-NEXT:  .LBB321_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB321_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB321_1
 ; PPC64LE-NEXT:  .LBB321_3:
@@ -5500,11 +5500,11 @@
 ; PPC64LE-LABEL: test322:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB322_1:
+; PPC64LE-NEXT:  .LBB322_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB322_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB322_1
 ; PPC64LE-NEXT:  .LBB322_3:
@@ -5518,11 +5518,11 @@
 ; PPC64LE-LABEL: test323:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB323_1:
+; PPC64LE-NEXT:  .LBB323_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB323_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB323_1
 ; PPC64LE-NEXT:  .LBB323_3:
@@ -5537,11 +5537,11 @@
 ; PPC64LE-LABEL: test324:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB324_1:
+; PPC64LE-NEXT:  .LBB324_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB324_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB324_1
 ; PPC64LE-NEXT:  .LBB324_3:
@@ -5555,11 +5555,11 @@
 define i16 @test325(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test325:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB325_1:
+; PPC64LE-NEXT:  .LBB325_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB325_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB325_1
 ; PPC64LE-NEXT:  .LBB325_3:
@@ -5573,11 +5573,11 @@
 ; PPC64LE-LABEL: test326:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB326_1:
+; PPC64LE-NEXT:  .LBB326_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB326_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB326_1
 ; PPC64LE-NEXT:  .LBB326_3:
@@ -5591,11 +5591,11 @@
 ; PPC64LE-LABEL: test327:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB327_1:
+; PPC64LE-NEXT:  .LBB327_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB327_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB327_1
 ; PPC64LE-NEXT:  .LBB327_3:
@@ -5609,11 +5609,11 @@
 ; PPC64LE-LABEL: test328:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB328_1:
+; PPC64LE-NEXT:  .LBB328_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB328_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB328_1
 ; PPC64LE-NEXT:  .LBB328_3:
@@ -5628,11 +5628,11 @@
 ; PPC64LE-LABEL: test329:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB329_1:
+; PPC64LE-NEXT:  .LBB329_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB329_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB329_1
 ; PPC64LE-NEXT:  .LBB329_3:
@@ -5646,11 +5646,11 @@
 define i32 @test330(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test330:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB330_1:
+; PPC64LE-NEXT:  .LBB330_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB330_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB330_1
 ; PPC64LE-NEXT:  .LBB330_3:
@@ -5664,11 +5664,11 @@
 ; PPC64LE-LABEL: test331:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB331_1:
+; PPC64LE-NEXT:  .LBB331_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB331_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB331_1
 ; PPC64LE-NEXT:  .LBB331_3:
@@ -5682,11 +5682,11 @@
 ; PPC64LE-LABEL: test332:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB332_1:
+; PPC64LE-NEXT:  .LBB332_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB332_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB332_1
 ; PPC64LE-NEXT:  .LBB332_3:
@@ -5700,11 +5700,11 @@
 ; PPC64LE-LABEL: test333:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB333_1:
+; PPC64LE-NEXT:  .LBB333_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB333_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB333_1
 ; PPC64LE-NEXT:  .LBB333_3:
@@ -5719,11 +5719,11 @@
 ; PPC64LE-LABEL: test334:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB334_1:
+; PPC64LE-NEXT:  .LBB334_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB334_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB334_1
 ; PPC64LE-NEXT:  .LBB334_3:
@@ -5737,11 +5737,11 @@
 define i64 @test335(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test335:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB335_1:
+; PPC64LE-NEXT:  .LBB335_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB335_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB335_1
 ; PPC64LE-NEXT:  .LBB335_3:
@@ -5755,11 +5755,11 @@
 ; PPC64LE-LABEL: test336:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB336_1:
+; PPC64LE-NEXT:  .LBB336_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpld 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB336_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB336_1
 ; PPC64LE-NEXT:  .LBB336_3:
@@ -5773,11 +5773,11 @@
 ; PPC64LE-LABEL: test337:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB337_1:
+; PPC64LE-NEXT:  .LBB337_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB337_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB337_1
 ; PPC64LE-NEXT:  .LBB337_3:
@@ -5791,11 +5791,11 @@
 ; PPC64LE-LABEL: test338:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB338_1:
+; PPC64LE-NEXT:  .LBB338_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB338_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB338_1
 ; PPC64LE-NEXT:  .LBB338_3:
@@ -5810,11 +5810,11 @@
 ; PPC64LE-LABEL: test339:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB339_1:
+; PPC64LE-NEXT:  .LBB339_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB339_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB339_1
 ; PPC64LE-NEXT:  .LBB339_3:
@@ -5828,7 +5828,7 @@
 define i8 @test340(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test340:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB340_1:
+; PPC64LE-NEXT:  .LBB340_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB340_1
@@ -5843,7 +5843,7 @@
 ; PPC64LE-LABEL: test341:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB341_1:
+; PPC64LE-NEXT:  .LBB341_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB341_1
@@ -5858,7 +5858,7 @@
 ; PPC64LE-LABEL: test342:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB342_1:
+; PPC64LE-NEXT:  .LBB342_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB342_1
@@ -5873,7 +5873,7 @@
 ; PPC64LE-LABEL: test343:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB343_1:
+; PPC64LE-NEXT:  .LBB343_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB343_1
@@ -5889,7 +5889,7 @@
 ; PPC64LE-LABEL: test344:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB344_1:
+; PPC64LE-NEXT:  .LBB344_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB344_1
@@ -5904,7 +5904,7 @@
 define i16 @test345(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test345:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB345_1:
+; PPC64LE-NEXT:  .LBB345_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB345_1
@@ -5919,7 +5919,7 @@
 ; PPC64LE-LABEL: test346:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB346_1:
+; PPC64LE-NEXT:  .LBB346_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB346_1
@@ -5934,7 +5934,7 @@
 ; PPC64LE-LABEL: test347:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB347_1:
+; PPC64LE-NEXT:  .LBB347_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB347_1
@@ -5949,7 +5949,7 @@
 ; PPC64LE-LABEL: test348:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB348_1:
+; PPC64LE-NEXT:  .LBB348_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB348_1
@@ -5965,7 +5965,7 @@
 ; PPC64LE-LABEL: test349:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB349_1:
+; PPC64LE-NEXT:  .LBB349_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB349_1
@@ -5980,7 +5980,7 @@
 define i32 @test350(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test350:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB350_1:
+; PPC64LE-NEXT:  .LBB350_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB350_1
@@ -5995,7 +5995,7 @@
 ; PPC64LE-LABEL: test351:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB351_1:
+; PPC64LE-NEXT:  .LBB351_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB351_1
@@ -6010,7 +6010,7 @@
 ; PPC64LE-LABEL: test352:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB352_1:
+; PPC64LE-NEXT:  .LBB352_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB352_1
@@ -6025,7 +6025,7 @@
 ; PPC64LE-LABEL: test353:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB353_1:
+; PPC64LE-NEXT:  .LBB353_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB353_1
@@ -6041,7 +6041,7 @@
 ; PPC64LE-LABEL: test354:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB354_1:
+; PPC64LE-NEXT:  .LBB354_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB354_1
@@ -6056,7 +6056,7 @@
 define i64 @test355(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test355:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB355_1:
+; PPC64LE-NEXT:  .LBB355_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB355_1
@@ -6071,7 +6071,7 @@
 ; PPC64LE-LABEL: test356:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB356_1:
+; PPC64LE-NEXT:  .LBB356_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB356_1
@@ -6086,7 +6086,7 @@
 ; PPC64LE-LABEL: test357:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB357_1:
+; PPC64LE-NEXT:  .LBB357_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB357_1
@@ -6101,7 +6101,7 @@
 ; PPC64LE-LABEL: test358:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB358_1:
+; PPC64LE-NEXT:  .LBB358_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB358_1
@@ -6117,7 +6117,7 @@
 ; PPC64LE-LABEL: test359:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB359_1:
+; PPC64LE-NEXT:  .LBB359_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB359_1
@@ -6132,7 +6132,7 @@
 define i8 @test360(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test360:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB360_1:
+; PPC64LE-NEXT:  .LBB360_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -6148,7 +6148,7 @@
 ; PPC64LE-LABEL: test361:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB361_1:
+; PPC64LE-NEXT:  .LBB361_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    add 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
@@ -6164,7 +6164,7 @@
 ; PPC64LE-LABEL: test362:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB362_1:
+; PPC64LE-NEXT:  .LBB362_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -6180,7 +6180,7 @@
 ; PPC64LE-LABEL: test363:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB363_1:
+; PPC64LE-NEXT:  .LBB363_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -6197,7 +6197,7 @@
 ; PPC64LE-LABEL: test364:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB364_1:
+; PPC64LE-NEXT:  .LBB364_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -6213,7 +6213,7 @@
 define i16 @test365(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test365:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB365_1:
+; PPC64LE-NEXT:  .LBB365_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -6229,7 +6229,7 @@
 ; PPC64LE-LABEL: test366:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB366_1:
+; PPC64LE-NEXT:  .LBB366_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    add 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
@@ -6245,7 +6245,7 @@
 ; PPC64LE-LABEL: test367:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB367_1:
+; PPC64LE-NEXT:  .LBB367_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -6261,7 +6261,7 @@
 ; PPC64LE-LABEL: test368:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB368_1:
+; PPC64LE-NEXT:  .LBB368_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -6278,7 +6278,7 @@
 ; PPC64LE-LABEL: test369:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB369_1:
+; PPC64LE-NEXT:  .LBB369_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -6294,7 +6294,7 @@
 define i32 @test370(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test370:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB370_1:
+; PPC64LE-NEXT:  .LBB370_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -6310,7 +6310,7 @@
 ; PPC64LE-LABEL: test371:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB371_1:
+; PPC64LE-NEXT:  .LBB371_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    add 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
@@ -6326,7 +6326,7 @@
 ; PPC64LE-LABEL: test372:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB372_1:
+; PPC64LE-NEXT:  .LBB372_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -6342,7 +6342,7 @@
 ; PPC64LE-LABEL: test373:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB373_1:
+; PPC64LE-NEXT:  .LBB373_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -6359,7 +6359,7 @@
 ; PPC64LE-LABEL: test374:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB374_1:
+; PPC64LE-NEXT:  .LBB374_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -6375,7 +6375,7 @@
 define i64 @test375(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test375:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB375_1:
+; PPC64LE-NEXT:  .LBB375_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -6391,7 +6391,7 @@
 ; PPC64LE-LABEL: test376:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB376_1:
+; PPC64LE-NEXT:  .LBB376_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    add 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
@@ -6407,7 +6407,7 @@
 ; PPC64LE-LABEL: test377:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB377_1:
+; PPC64LE-NEXT:  .LBB377_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -6423,7 +6423,7 @@
 ; PPC64LE-LABEL: test378:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB378_1:
+; PPC64LE-NEXT:  .LBB378_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -6440,7 +6440,7 @@
 ; PPC64LE-LABEL: test379:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB379_1:
+; PPC64LE-NEXT:  .LBB379_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -6456,7 +6456,7 @@
 define i8 @test380(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test380:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB380_1:
+; PPC64LE-NEXT:  .LBB380_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -6472,7 +6472,7 @@
 ; PPC64LE-LABEL: test381:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB381_1:
+; PPC64LE-NEXT:  .LBB381_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    subf 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
@@ -6488,7 +6488,7 @@
 ; PPC64LE-LABEL: test382:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB382_1:
+; PPC64LE-NEXT:  .LBB382_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -6504,7 +6504,7 @@
 ; PPC64LE-LABEL: test383:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB383_1:
+; PPC64LE-NEXT:  .LBB383_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -6521,7 +6521,7 @@
 ; PPC64LE-LABEL: test384:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB384_1:
+; PPC64LE-NEXT:  .LBB384_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -6537,7 +6537,7 @@
 define i16 @test385(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test385:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB385_1:
+; PPC64LE-NEXT:  .LBB385_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -6553,7 +6553,7 @@
 ; PPC64LE-LABEL: test386:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB386_1:
+; PPC64LE-NEXT:  .LBB386_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    subf 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
@@ -6569,7 +6569,7 @@
 ; PPC64LE-LABEL: test387:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB387_1:
+; PPC64LE-NEXT:  .LBB387_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -6585,7 +6585,7 @@
 ; PPC64LE-LABEL: test388:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB388_1:
+; PPC64LE-NEXT:  .LBB388_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -6602,7 +6602,7 @@
 ; PPC64LE-LABEL: test389:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB389_1:
+; PPC64LE-NEXT:  .LBB389_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -6618,7 +6618,7 @@
 define i32 @test390(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test390:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB390_1:
+; PPC64LE-NEXT:  .LBB390_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -6634,7 +6634,7 @@
 ; PPC64LE-LABEL: test391:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB391_1:
+; PPC64LE-NEXT:  .LBB391_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    subf 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
@@ -6650,7 +6650,7 @@
 ; PPC64LE-LABEL: test392:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB392_1:
+; PPC64LE-NEXT:  .LBB392_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -6666,7 +6666,7 @@
 ; PPC64LE-LABEL: test393:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB393_1:
+; PPC64LE-NEXT:  .LBB393_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -6683,7 +6683,7 @@
 ; PPC64LE-LABEL: test394:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB394_1:
+; PPC64LE-NEXT:  .LBB394_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -6699,7 +6699,7 @@
 define i64 @test395(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test395:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB395_1:
+; PPC64LE-NEXT:  .LBB395_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -6715,7 +6715,7 @@
 ; PPC64LE-LABEL: test396:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB396_1:
+; PPC64LE-NEXT:  .LBB396_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
@@ -6731,7 +6731,7 @@
 ; PPC64LE-LABEL: test397:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB397_1:
+; PPC64LE-NEXT:  .LBB397_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -6747,7 +6747,7 @@
 ; PPC64LE-LABEL: test398:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB398_1:
+; PPC64LE-NEXT:  .LBB398_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -6764,7 +6764,7 @@
 ; PPC64LE-LABEL: test399:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB399_1:
+; PPC64LE-NEXT:  .LBB399_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -6780,7 +6780,7 @@
 define i8 @test400(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test400:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB400_1:
+; PPC64LE-NEXT:  .LBB400_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -6796,7 +6796,7 @@
 ; PPC64LE-LABEL: test401:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB401_1:
+; PPC64LE-NEXT:  .LBB401_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    and 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
@@ -6812,7 +6812,7 @@
 ; PPC64LE-LABEL: test402:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB402_1:
+; PPC64LE-NEXT:  .LBB402_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -6828,7 +6828,7 @@
 ; PPC64LE-LABEL: test403:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB403_1:
+; PPC64LE-NEXT:  .LBB403_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -6845,7 +6845,7 @@
 ; PPC64LE-LABEL: test404:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB404_1:
+; PPC64LE-NEXT:  .LBB404_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -6861,7 +6861,7 @@
 define i16 @test405(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test405:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB405_1:
+; PPC64LE-NEXT:  .LBB405_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -6877,7 +6877,7 @@
 ; PPC64LE-LABEL: test406:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB406_1:
+; PPC64LE-NEXT:  .LBB406_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    and 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
@@ -6893,7 +6893,7 @@
 ; PPC64LE-LABEL: test407:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB407_1:
+; PPC64LE-NEXT:  .LBB407_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -6909,7 +6909,7 @@
 ; PPC64LE-LABEL: test408:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB408_1:
+; PPC64LE-NEXT:  .LBB408_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -6926,7 +6926,7 @@
 ; PPC64LE-LABEL: test409:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB409_1:
+; PPC64LE-NEXT:  .LBB409_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -6942,7 +6942,7 @@
 define i32 @test410(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test410:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB410_1:
+; PPC64LE-NEXT:  .LBB410_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -6958,7 +6958,7 @@
 ; PPC64LE-LABEL: test411:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB411_1:
+; PPC64LE-NEXT:  .LBB411_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    and 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
@@ -6974,7 +6974,7 @@
 ; PPC64LE-LABEL: test412:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB412_1:
+; PPC64LE-NEXT:  .LBB412_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -6990,7 +6990,7 @@
 ; PPC64LE-LABEL: test413:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB413_1:
+; PPC64LE-NEXT:  .LBB413_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -7007,7 +7007,7 @@
 ; PPC64LE-LABEL: test414:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB414_1:
+; PPC64LE-NEXT:  .LBB414_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -7023,7 +7023,7 @@
 define i64 @test415(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test415:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB415_1:
+; PPC64LE-NEXT:  .LBB415_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -7039,7 +7039,7 @@
 ; PPC64LE-LABEL: test416:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB416_1:
+; PPC64LE-NEXT:  .LBB416_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    and 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
@@ -7055,7 +7055,7 @@
 ; PPC64LE-LABEL: test417:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB417_1:
+; PPC64LE-NEXT:  .LBB417_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -7071,7 +7071,7 @@
 ; PPC64LE-LABEL: test418:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB418_1:
+; PPC64LE-NEXT:  .LBB418_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -7088,7 +7088,7 @@
 ; PPC64LE-LABEL: test419:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB419_1:
+; PPC64LE-NEXT:  .LBB419_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -7104,7 +7104,7 @@
 define i8 @test420(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test420:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB420_1:
+; PPC64LE-NEXT:  .LBB420_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -7120,7 +7120,7 @@
 ; PPC64LE-LABEL: test421:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB421_1:
+; PPC64LE-NEXT:  .LBB421_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    nand 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
@@ -7136,7 +7136,7 @@
 ; PPC64LE-LABEL: test422:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB422_1:
+; PPC64LE-NEXT:  .LBB422_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -7152,7 +7152,7 @@
 ; PPC64LE-LABEL: test423:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB423_1:
+; PPC64LE-NEXT:  .LBB423_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -7169,7 +7169,7 @@
 ; PPC64LE-LABEL: test424:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB424_1:
+; PPC64LE-NEXT:  .LBB424_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -7185,7 +7185,7 @@
 define i16 @test425(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test425:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB425_1:
+; PPC64LE-NEXT:  .LBB425_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -7201,7 +7201,7 @@
 ; PPC64LE-LABEL: test426:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB426_1:
+; PPC64LE-NEXT:  .LBB426_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    nand 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
@@ -7217,7 +7217,7 @@
 ; PPC64LE-LABEL: test427:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB427_1:
+; PPC64LE-NEXT:  .LBB427_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -7233,7 +7233,7 @@
 ; PPC64LE-LABEL: test428:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB428_1:
+; PPC64LE-NEXT:  .LBB428_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -7250,7 +7250,7 @@
 ; PPC64LE-LABEL: test429:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB429_1:
+; PPC64LE-NEXT:  .LBB429_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -7266,7 +7266,7 @@
 define i32 @test430(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test430:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB430_1:
+; PPC64LE-NEXT:  .LBB430_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -7282,7 +7282,7 @@
 ; PPC64LE-LABEL: test431:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB431_1:
+; PPC64LE-NEXT:  .LBB431_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    nand 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
@@ -7298,7 +7298,7 @@
 ; PPC64LE-LABEL: test432:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB432_1:
+; PPC64LE-NEXT:  .LBB432_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -7314,7 +7314,7 @@
 ; PPC64LE-LABEL: test433:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB433_1:
+; PPC64LE-NEXT:  .LBB433_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -7331,7 +7331,7 @@
 ; PPC64LE-LABEL: test434:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB434_1:
+; PPC64LE-NEXT:  .LBB434_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -7347,7 +7347,7 @@
 define i64 @test435(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test435:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB435_1:
+; PPC64LE-NEXT:  .LBB435_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -7363,7 +7363,7 @@
 ; PPC64LE-LABEL: test436:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB436_1:
+; PPC64LE-NEXT:  .LBB436_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    nand 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
@@ -7379,7 +7379,7 @@
 ; PPC64LE-LABEL: test437:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB437_1:
+; PPC64LE-NEXT:  .LBB437_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -7395,7 +7395,7 @@
 ; PPC64LE-LABEL: test438:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB438_1:
+; PPC64LE-NEXT:  .LBB438_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -7412,7 +7412,7 @@
 ; PPC64LE-LABEL: test439:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB439_1:
+; PPC64LE-NEXT:  .LBB439_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -7428,7 +7428,7 @@
 define i8 @test440(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test440:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB440_1:
+; PPC64LE-NEXT:  .LBB440_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -7444,7 +7444,7 @@
 ; PPC64LE-LABEL: test441:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB441_1:
+; PPC64LE-NEXT:  .LBB441_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    or 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
@@ -7460,7 +7460,7 @@
 ; PPC64LE-LABEL: test442:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB442_1:
+; PPC64LE-NEXT:  .LBB442_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -7476,7 +7476,7 @@
 ; PPC64LE-LABEL: test443:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB443_1:
+; PPC64LE-NEXT:  .LBB443_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -7493,7 +7493,7 @@
 ; PPC64LE-LABEL: test444:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB444_1:
+; PPC64LE-NEXT:  .LBB444_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -7509,7 +7509,7 @@
 define i16 @test445(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test445:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB445_1:
+; PPC64LE-NEXT:  .LBB445_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -7525,7 +7525,7 @@
 ; PPC64LE-LABEL: test446:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB446_1:
+; PPC64LE-NEXT:  .LBB446_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    or 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
@@ -7541,7 +7541,7 @@
 ; PPC64LE-LABEL: test447:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB447_1:
+; PPC64LE-NEXT:  .LBB447_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -7557,7 +7557,7 @@
 ; PPC64LE-LABEL: test448:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB448_1:
+; PPC64LE-NEXT:  .LBB448_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -7574,7 +7574,7 @@
 ; PPC64LE-LABEL: test449:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB449_1:
+; PPC64LE-NEXT:  .LBB449_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -7590,7 +7590,7 @@
 define i32 @test450(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test450:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB450_1:
+; PPC64LE-NEXT:  .LBB450_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -7606,7 +7606,7 @@
 ; PPC64LE-LABEL: test451:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB451_1:
+; PPC64LE-NEXT:  .LBB451_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    or 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
@@ -7622,7 +7622,7 @@
 ; PPC64LE-LABEL: test452:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB452_1:
+; PPC64LE-NEXT:  .LBB452_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -7638,7 +7638,7 @@
 ; PPC64LE-LABEL: test453:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB453_1:
+; PPC64LE-NEXT:  .LBB453_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -7655,7 +7655,7 @@
 ; PPC64LE-LABEL: test454:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB454_1:
+; PPC64LE-NEXT:  .LBB454_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -7671,7 +7671,7 @@
 define i64 @test455(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test455:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB455_1:
+; PPC64LE-NEXT:  .LBB455_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -7687,7 +7687,7 @@
 ; PPC64LE-LABEL: test456:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB456_1:
+; PPC64LE-NEXT:  .LBB456_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    or 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
@@ -7703,7 +7703,7 @@
 ; PPC64LE-LABEL: test457:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB457_1:
+; PPC64LE-NEXT:  .LBB457_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -7719,7 +7719,7 @@
 ; PPC64LE-LABEL: test458:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB458_1:
+; PPC64LE-NEXT:  .LBB458_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -7736,7 +7736,7 @@
 ; PPC64LE-LABEL: test459:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB459_1:
+; PPC64LE-NEXT:  .LBB459_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -7752,7 +7752,7 @@
 define i8 @test460(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test460:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB460_1:
+; PPC64LE-NEXT:  .LBB460_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -7768,7 +7768,7 @@
 ; PPC64LE-LABEL: test461:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB461_1:
+; PPC64LE-NEXT:  .LBB461_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    xor 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
@@ -7784,7 +7784,7 @@
 ; PPC64LE-LABEL: test462:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB462_1:
+; PPC64LE-NEXT:  .LBB462_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -7800,7 +7800,7 @@
 ; PPC64LE-LABEL: test463:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB463_1:
+; PPC64LE-NEXT:  .LBB463_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -7817,7 +7817,7 @@
 ; PPC64LE-LABEL: test464:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB464_1:
+; PPC64LE-NEXT:  .LBB464_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
@@ -7833,7 +7833,7 @@
 define i16 @test465(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test465:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB465_1:
+; PPC64LE-NEXT:  .LBB465_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -7849,7 +7849,7 @@
 ; PPC64LE-LABEL: test466:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB466_1:
+; PPC64LE-NEXT:  .LBB466_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    xor 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
@@ -7865,7 +7865,7 @@
 ; PPC64LE-LABEL: test467:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB467_1:
+; PPC64LE-NEXT:  .LBB467_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -7881,7 +7881,7 @@
 ; PPC64LE-LABEL: test468:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB468_1:
+; PPC64LE-NEXT:  .LBB468_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -7898,7 +7898,7 @@
 ; PPC64LE-LABEL: test469:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB469_1:
+; PPC64LE-NEXT:  .LBB469_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
@@ -7914,7 +7914,7 @@
 define i32 @test470(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test470:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB470_1:
+; PPC64LE-NEXT:  .LBB470_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -7930,7 +7930,7 @@
 ; PPC64LE-LABEL: test471:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB471_1:
+; PPC64LE-NEXT:  .LBB471_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    xor 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
@@ -7946,7 +7946,7 @@
 ; PPC64LE-LABEL: test472:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB472_1:
+; PPC64LE-NEXT:  .LBB472_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -7962,7 +7962,7 @@
 ; PPC64LE-LABEL: test473:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB473_1:
+; PPC64LE-NEXT:  .LBB473_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -7979,7 +7979,7 @@
 ; PPC64LE-LABEL: test474:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB474_1:
+; PPC64LE-NEXT:  .LBB474_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
@@ -7995,7 +7995,7 @@
 define i64 @test475(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test475:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB475_1:
+; PPC64LE-NEXT:  .LBB475_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -8011,7 +8011,7 @@
 ; PPC64LE-LABEL: test476:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB476_1:
+; PPC64LE-NEXT:  .LBB476_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    xor 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
@@ -8027,7 +8027,7 @@
 ; PPC64LE-LABEL: test477:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB477_1:
+; PPC64LE-NEXT:  .LBB477_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -8043,7 +8043,7 @@
 ; PPC64LE-LABEL: test478:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB478_1:
+; PPC64LE-NEXT:  .LBB478_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -8060,7 +8060,7 @@
 ; PPC64LE-LABEL: test479:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB479_1:
+; PPC64LE-NEXT:  .LBB479_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
@@ -8076,12 +8076,12 @@
 define i8 @test480(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test480:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB480_1:
+; PPC64LE-NEXT:  .LBB480_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB480_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB480_1
 ; PPC64LE-NEXT:  .LBB480_3:
@@ -8095,12 +8095,12 @@
 ; PPC64LE-LABEL: test481:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB481_1:
+; PPC64LE-NEXT:  .LBB481_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    extsb 6, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB481_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB481_1
 ; PPC64LE-NEXT:  .LBB481_3:
@@ -8114,12 +8114,12 @@
 ; PPC64LE-LABEL: test482:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB482_1:
+; PPC64LE-NEXT:  .LBB482_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB482_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB482_1
 ; PPC64LE-NEXT:  .LBB482_3:
@@ -8133,12 +8133,12 @@
 ; PPC64LE-LABEL: test483:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB483_1:
+; PPC64LE-NEXT:  .LBB483_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB483_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB483_1
 ; PPC64LE-NEXT:  .LBB483_3:
@@ -8153,12 +8153,12 @@
 ; PPC64LE-LABEL: test484:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB484_1:
+; PPC64LE-NEXT:  .LBB484_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB484_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB484_1
 ; PPC64LE-NEXT:  .LBB484_3:
@@ -8172,12 +8172,12 @@
 define i16 @test485(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test485:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB485_1:
+; PPC64LE-NEXT:  .LBB485_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB485_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB485_1
 ; PPC64LE-NEXT:  .LBB485_3:
@@ -8191,12 +8191,12 @@
 ; PPC64LE-LABEL: test486:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB486_1:
+; PPC64LE-NEXT:  .LBB486_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    extsh 6, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB486_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB486_1
 ; PPC64LE-NEXT:  .LBB486_3:
@@ -8210,12 +8210,12 @@
 ; PPC64LE-LABEL: test487:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB487_1:
+; PPC64LE-NEXT:  .LBB487_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB487_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB487_1
 ; PPC64LE-NEXT:  .LBB487_3:
@@ -8229,12 +8229,12 @@
 ; PPC64LE-LABEL: test488:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB488_1:
+; PPC64LE-NEXT:  .LBB488_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB488_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB488_1
 ; PPC64LE-NEXT:  .LBB488_3:
@@ -8249,12 +8249,12 @@
 ; PPC64LE-LABEL: test489:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB489_1:
+; PPC64LE-NEXT:  .LBB489_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB489_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB489_1
 ; PPC64LE-NEXT:  .LBB489_3:
@@ -8268,11 +8268,11 @@
 define i32 @test490(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test490:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB490_1:
+; PPC64LE-NEXT:  .LBB490_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB490_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB490_1
 ; PPC64LE-NEXT:  .LBB490_3:
@@ -8286,11 +8286,11 @@
 ; PPC64LE-LABEL: test491:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB491_1:
+; PPC64LE-NEXT:  .LBB491_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpw 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB491_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB491_1
 ; PPC64LE-NEXT:  .LBB491_3:
@@ -8304,11 +8304,11 @@
 ; PPC64LE-LABEL: test492:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB492_1:
+; PPC64LE-NEXT:  .LBB492_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB492_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB492_1
 ; PPC64LE-NEXT:  .LBB492_3:
@@ -8322,11 +8322,11 @@
 ; PPC64LE-LABEL: test493:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB493_1:
+; PPC64LE-NEXT:  .LBB493_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB493_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB493_1
 ; PPC64LE-NEXT:  .LBB493_3:
@@ -8341,11 +8341,11 @@
 ; PPC64LE-LABEL: test494:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB494_1:
+; PPC64LE-NEXT:  .LBB494_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB494_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB494_1
 ; PPC64LE-NEXT:  .LBB494_3:
@@ -8359,11 +8359,11 @@
 define i64 @test495(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test495:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB495_1:
+; PPC64LE-NEXT:  .LBB495_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB495_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB495_1
 ; PPC64LE-NEXT:  .LBB495_3:
@@ -8377,11 +8377,11 @@
 ; PPC64LE-LABEL: test496:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB496_1:
+; PPC64LE-NEXT:  .LBB496_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpd 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB496_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB496_1
 ; PPC64LE-NEXT:  .LBB496_3:
@@ -8395,11 +8395,11 @@
 ; PPC64LE-LABEL: test497:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB497_1:
+; PPC64LE-NEXT:  .LBB497_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB497_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB497_1
 ; PPC64LE-NEXT:  .LBB497_3:
@@ -8413,11 +8413,11 @@
 ; PPC64LE-LABEL: test498:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB498_1:
+; PPC64LE-NEXT:  .LBB498_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB498_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB498_1
 ; PPC64LE-NEXT:  .LBB498_3:
@@ -8432,11 +8432,11 @@
 ; PPC64LE-LABEL: test499:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB499_1:
+; PPC64LE-NEXT:  .LBB499_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB499_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB499_1
 ; PPC64LE-NEXT:  .LBB499_3:
@@ -8450,12 +8450,12 @@
 define i8 @test500(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test500:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB500_1:
+; PPC64LE-NEXT:  .LBB500_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB500_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB500_1
 ; PPC64LE-NEXT:  .LBB500_3:
@@ -8469,12 +8469,12 @@
 ; PPC64LE-LABEL: test501:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB501_1:
+; PPC64LE-NEXT:  .LBB501_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    extsb 6, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB501_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB501_1
 ; PPC64LE-NEXT:  .LBB501_3:
@@ -8488,12 +8488,12 @@
 ; PPC64LE-LABEL: test502:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB502_1:
+; PPC64LE-NEXT:  .LBB502_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB502_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB502_1
 ; PPC64LE-NEXT:  .LBB502_3:
@@ -8507,12 +8507,12 @@
 ; PPC64LE-LABEL: test503:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB503_1:
+; PPC64LE-NEXT:  .LBB503_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB503_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB503_1
 ; PPC64LE-NEXT:  .LBB503_3:
@@ -8527,12 +8527,12 @@
 ; PPC64LE-LABEL: test504:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB504_1:
+; PPC64LE-NEXT:  .LBB504_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB504_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB504_1
 ; PPC64LE-NEXT:  .LBB504_3:
@@ -8546,12 +8546,12 @@
 define i16 @test505(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test505:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB505_1:
+; PPC64LE-NEXT:  .LBB505_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB505_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB505_1
 ; PPC64LE-NEXT:  .LBB505_3:
@@ -8565,12 +8565,12 @@
 ; PPC64LE-LABEL: test506:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB506_1:
+; PPC64LE-NEXT:  .LBB506_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    extsh 6, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB506_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB506_1
 ; PPC64LE-NEXT:  .LBB506_3:
@@ -8584,12 +8584,12 @@
 ; PPC64LE-LABEL: test507:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB507_1:
+; PPC64LE-NEXT:  .LBB507_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB507_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB507_1
 ; PPC64LE-NEXT:  .LBB507_3:
@@ -8603,12 +8603,12 @@
 ; PPC64LE-LABEL: test508:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB508_1:
+; PPC64LE-NEXT:  .LBB508_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB508_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB508_1
 ; PPC64LE-NEXT:  .LBB508_3:
@@ -8623,12 +8623,12 @@
 ; PPC64LE-LABEL: test509:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB509_1:
+; PPC64LE-NEXT:  .LBB509_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB509_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB509_1
 ; PPC64LE-NEXT:  .LBB509_3:
@@ -8642,11 +8642,11 @@
 define i32 @test510(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test510:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB510_1:
+; PPC64LE-NEXT:  .LBB510_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB510_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB510_1
 ; PPC64LE-NEXT:  .LBB510_3:
@@ -8660,11 +8660,11 @@
 ; PPC64LE-LABEL: test511:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB511_1:
+; PPC64LE-NEXT:  .LBB511_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpw 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB511_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB511_1
 ; PPC64LE-NEXT:  .LBB511_3:
@@ -8678,11 +8678,11 @@
 ; PPC64LE-LABEL: test512:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB512_1:
+; PPC64LE-NEXT:  .LBB512_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB512_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB512_1
 ; PPC64LE-NEXT:  .LBB512_3:
@@ -8696,11 +8696,11 @@
 ; PPC64LE-LABEL: test513:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB513_1:
+; PPC64LE-NEXT:  .LBB513_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB513_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB513_1
 ; PPC64LE-NEXT:  .LBB513_3:
@@ -8715,11 +8715,11 @@
 ; PPC64LE-LABEL: test514:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB514_1:
+; PPC64LE-NEXT:  .LBB514_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB514_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB514_1
 ; PPC64LE-NEXT:  .LBB514_3:
@@ -8733,11 +8733,11 @@
 define i64 @test515(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test515:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB515_1:
+; PPC64LE-NEXT:  .LBB515_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB515_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB515_1
 ; PPC64LE-NEXT:  .LBB515_3:
@@ -8751,11 +8751,11 @@
 ; PPC64LE-LABEL: test516:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB516_1:
+; PPC64LE-NEXT:  .LBB516_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpd 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB516_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB516_1
 ; PPC64LE-NEXT:  .LBB516_3:
@@ -8769,11 +8769,11 @@
 ; PPC64LE-LABEL: test517:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB517_1:
+; PPC64LE-NEXT:  .LBB517_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB517_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB517_1
 ; PPC64LE-NEXT:  .LBB517_3:
@@ -8787,11 +8787,11 @@
 ; PPC64LE-LABEL: test518:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB518_1:
+; PPC64LE-NEXT:  .LBB518_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB518_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB518_1
 ; PPC64LE-NEXT:  .LBB518_3:
@@ -8806,11 +8806,11 @@
 ; PPC64LE-LABEL: test519:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB519_1:
+; PPC64LE-NEXT:  .LBB519_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB519_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB519_1
 ; PPC64LE-NEXT:  .LBB519_3:
@@ -8824,11 +8824,11 @@
 define i8 @test520(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test520:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB520_1:
+; PPC64LE-NEXT:  .LBB520_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB520_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB520_1
 ; PPC64LE-NEXT:  .LBB520_3:
@@ -8842,11 +8842,11 @@
 ; PPC64LE-LABEL: test521:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB521_1:
+; PPC64LE-NEXT:  .LBB521_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB521_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB521_1
 ; PPC64LE-NEXT:  .LBB521_3:
@@ -8860,11 +8860,11 @@
 ; PPC64LE-LABEL: test522:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB522_1:
+; PPC64LE-NEXT:  .LBB522_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB522_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB522_1
 ; PPC64LE-NEXT:  .LBB522_3:
@@ -8878,11 +8878,11 @@
 ; PPC64LE-LABEL: test523:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB523_1:
+; PPC64LE-NEXT:  .LBB523_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB523_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB523_1
 ; PPC64LE-NEXT:  .LBB523_3:
@@ -8897,11 +8897,11 @@
 ; PPC64LE-LABEL: test524:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB524_1:
+; PPC64LE-NEXT:  .LBB524_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB524_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB524_1
 ; PPC64LE-NEXT:  .LBB524_3:
@@ -8915,11 +8915,11 @@
 define i16 @test525(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test525:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB525_1:
+; PPC64LE-NEXT:  .LBB525_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB525_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB525_1
 ; PPC64LE-NEXT:  .LBB525_3:
@@ -8933,11 +8933,11 @@
 ; PPC64LE-LABEL: test526:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB526_1:
+; PPC64LE-NEXT:  .LBB526_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB526_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB526_1
 ; PPC64LE-NEXT:  .LBB526_3:
@@ -8951,11 +8951,11 @@
 ; PPC64LE-LABEL: test527:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB527_1:
+; PPC64LE-NEXT:  .LBB527_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB527_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB527_1
 ; PPC64LE-NEXT:  .LBB527_3:
@@ -8969,11 +8969,11 @@
 ; PPC64LE-LABEL: test528:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB528_1:
+; PPC64LE-NEXT:  .LBB528_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB528_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB528_1
 ; PPC64LE-NEXT:  .LBB528_3:
@@ -8988,11 +8988,11 @@
 ; PPC64LE-LABEL: test529:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB529_1:
+; PPC64LE-NEXT:  .LBB529_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB529_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB529_1
 ; PPC64LE-NEXT:  .LBB529_3:
@@ -9006,11 +9006,11 @@
 define i32 @test530(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test530:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB530_1:
+; PPC64LE-NEXT:  .LBB530_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB530_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB530_1
 ; PPC64LE-NEXT:  .LBB530_3:
@@ -9024,11 +9024,11 @@
 ; PPC64LE-LABEL: test531:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB531_1:
+; PPC64LE-NEXT:  .LBB531_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB531_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB531_1
 ; PPC64LE-NEXT:  .LBB531_3:
@@ -9042,11 +9042,11 @@
 ; PPC64LE-LABEL: test532:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB532_1:
+; PPC64LE-NEXT:  .LBB532_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB532_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB532_1
 ; PPC64LE-NEXT:  .LBB532_3:
@@ -9060,11 +9060,11 @@
 ; PPC64LE-LABEL: test533:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB533_1:
+; PPC64LE-NEXT:  .LBB533_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB533_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB533_1
 ; PPC64LE-NEXT:  .LBB533_3:
@@ -9079,11 +9079,11 @@
 ; PPC64LE-LABEL: test534:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB534_1:
+; PPC64LE-NEXT:  .LBB534_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB534_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB534_1
 ; PPC64LE-NEXT:  .LBB534_3:
@@ -9097,11 +9097,11 @@
 define i64 @test535(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test535:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB535_1:
+; PPC64LE-NEXT:  .LBB535_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB535_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB535_1
 ; PPC64LE-NEXT:  .LBB535_3:
@@ -9115,11 +9115,11 @@
 ; PPC64LE-LABEL: test536:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB536_1:
+; PPC64LE-NEXT:  .LBB536_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpld 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB536_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB536_1
 ; PPC64LE-NEXT:  .LBB536_3:
@@ -9133,11 +9133,11 @@
 ; PPC64LE-LABEL: test537:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB537_1:
+; PPC64LE-NEXT:  .LBB537_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB537_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB537_1
 ; PPC64LE-NEXT:  .LBB537_3:
@@ -9151,11 +9151,11 @@
 ; PPC64LE-LABEL: test538:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB538_1:
+; PPC64LE-NEXT:  .LBB538_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB538_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB538_1
 ; PPC64LE-NEXT:  .LBB538_3:
@@ -9170,11 +9170,11 @@
 ; PPC64LE-LABEL: test539:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB539_1:
+; PPC64LE-NEXT:  .LBB539_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB539_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB539_1
 ; PPC64LE-NEXT:  .LBB539_3:
@@ -9188,11 +9188,11 @@
 define i8 @test540(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test540:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB540_1:
+; PPC64LE-NEXT:  .LBB540_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB540_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB540_1
 ; PPC64LE-NEXT:  .LBB540_3:
@@ -9206,11 +9206,11 @@
 ; PPC64LE-LABEL: test541:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB541_1:
+; PPC64LE-NEXT:  .LBB541_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB541_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB541_1
 ; PPC64LE-NEXT:  .LBB541_3:
@@ -9224,11 +9224,11 @@
 ; PPC64LE-LABEL: test542:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB542_1:
+; PPC64LE-NEXT:  .LBB542_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB542_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB542_1
 ; PPC64LE-NEXT:  .LBB542_3:
@@ -9242,11 +9242,11 @@
 ; PPC64LE-LABEL: test543:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB543_1:
+; PPC64LE-NEXT:  .LBB543_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB543_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB543_1
 ; PPC64LE-NEXT:  .LBB543_3:
@@ -9261,11 +9261,11 @@
 ; PPC64LE-LABEL: test544:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB544_1:
+; PPC64LE-NEXT:  .LBB544_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB544_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB544_1
 ; PPC64LE-NEXT:  .LBB544_3:
@@ -9279,11 +9279,11 @@
 define i16 @test545(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test545:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB545_1:
+; PPC64LE-NEXT:  .LBB545_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB545_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB545_1
 ; PPC64LE-NEXT:  .LBB545_3:
@@ -9297,11 +9297,11 @@
 ; PPC64LE-LABEL: test546:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB546_1:
+; PPC64LE-NEXT:  .LBB546_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB546_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB546_1
 ; PPC64LE-NEXT:  .LBB546_3:
@@ -9315,11 +9315,11 @@
 ; PPC64LE-LABEL: test547:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB547_1:
+; PPC64LE-NEXT:  .LBB547_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB547_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB547_1
 ; PPC64LE-NEXT:  .LBB547_3:
@@ -9333,11 +9333,11 @@
 ; PPC64LE-LABEL: test548:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB548_1:
+; PPC64LE-NEXT:  .LBB548_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB548_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB548_1
 ; PPC64LE-NEXT:  .LBB548_3:
@@ -9352,11 +9352,11 @@
 ; PPC64LE-LABEL: test549:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB549_1:
+; PPC64LE-NEXT:  .LBB549_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB549_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB549_1
 ; PPC64LE-NEXT:  .LBB549_3:
@@ -9370,11 +9370,11 @@
 define i32 @test550(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test550:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB550_1:
+; PPC64LE-NEXT:  .LBB550_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB550_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB550_1
 ; PPC64LE-NEXT:  .LBB550_3:
@@ -9388,11 +9388,11 @@
 ; PPC64LE-LABEL: test551:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB551_1:
+; PPC64LE-NEXT:  .LBB551_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB551_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB551_1
 ; PPC64LE-NEXT:  .LBB551_3:
@@ -9406,11 +9406,11 @@
 ; PPC64LE-LABEL: test552:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB552_1:
+; PPC64LE-NEXT:  .LBB552_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB552_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB552_1
 ; PPC64LE-NEXT:  .LBB552_3:
@@ -9424,11 +9424,11 @@
 ; PPC64LE-LABEL: test553:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB553_1:
+; PPC64LE-NEXT:  .LBB553_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB553_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB553_1
 ; PPC64LE-NEXT:  .LBB553_3:
@@ -9443,11 +9443,11 @@
 ; PPC64LE-LABEL: test554:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB554_1:
+; PPC64LE-NEXT:  .LBB554_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB554_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB554_1
 ; PPC64LE-NEXT:  .LBB554_3:
@@ -9461,11 +9461,11 @@
 define i64 @test555(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test555:
 ; PPC64LE:       # %bb.0:
-; PPC64LE-NEXT:  .LBB555_1:
+; PPC64LE-NEXT:  .LBB555_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB555_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB555_1
 ; PPC64LE-NEXT:  .LBB555_3:
@@ -9479,11 +9479,11 @@
 ; PPC64LE-LABEL: test556:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
-; PPC64LE-NEXT:  .LBB556_1:
+; PPC64LE-NEXT:  .LBB556_1: #
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpld 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB556_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB556_1
 ; PPC64LE-NEXT:  .LBB556_3:
@@ -9497,11 +9497,11 @@
 ; PPC64LE-LABEL: test557:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB557_1:
+; PPC64LE-NEXT:  .LBB557_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB557_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB557_1
 ; PPC64LE-NEXT:  .LBB557_3:
@@ -9515,11 +9515,11 @@
 ; PPC64LE-LABEL: test558:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:  .LBB558_1:
+; PPC64LE-NEXT:  .LBB558_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB558_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB558_1
 ; PPC64LE-NEXT:  .LBB558_3:
@@ -9534,11 +9534,11 @@
 ; PPC64LE-LABEL: test559:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
-; PPC64LE-NEXT:  .LBB559_1:
+; PPC64LE-NEXT:  .LBB559_1: #
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB559_3
-; PPC64LE-NEXT:  # %bb.2:
+; PPC64LE-NEXT:  # %bb.2: #
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB559_1
 ; PPC64LE-NEXT:  .LBB559_3:
diff --git a/llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll b/llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
--- a/llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
+++ b/llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
@@ -11,7 +11,7 @@
 ; CHECK-P7: lwa 3,
 ; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
 ; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
-; CHECK: mfvsrwz 3, [[SHIFTREG]]
+; CHECK: mffprwz 3, [[SHIFTREG]]
 }
 
 define i64 @f64toi64(double %a) {
@@ -29,7 +29,7 @@
   ret float %0
 ; CHECK-P7: stw 3,
 ; CHECK-P7: lfs 1,
-; CHECK: mtvsrd [[MOVEREG:[0-9]+]], 3
+; CHECK: mtfprd [[MOVEREG:[0-9]+]], 3
 ; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1
 ; CHECK: xscvspdpn 1, [[SHIFTREG]]
 }
@@ -51,7 +51,7 @@
 ; CHECK-P7: lwz 3,
 ; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
 ; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
-; CHECK: mfvsrwz 3, [[SHIFTREG]]
+; CHECK: mffprwz 3, [[SHIFTREG]]
 }
 
 define i64 @f64toi64u(double %a) {
@@ -69,7 +69,7 @@
   ret float %0
 ; CHECK-P7: stw 3,
 ; CHECK-P7: lfs 1,
-; CHECK: mtvsrd [[MOVEREG:[0-9]+]], 3
+; CHECK: mtfprd [[MOVEREG:[0-9]+]], 3
 ; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1
 ; CHECK: xscvspdpn 1, [[SHIFTREG]]
 }
diff --git a/llvm/test/CodeGen/PowerPC/bool-math.ll b/llvm/test/CodeGen/PowerPC/bool-math.ll
--- a/llvm/test/CodeGen/PowerPC/bool-math.ll
+++ b/llvm/test/CodeGen/PowerPC/bool-math.ll
@@ -44,7 +44,7 @@
 define i8 @add_zext_cmp_mask_same_size_result(i8 %x) {
 ; CHECK-LABEL: add_zext_cmp_mask_same_size_result:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 3, 3, 0, 31, 31
+; CHECK-NEXT:    clrlwi 3, 3, 31
 ; CHECK-NEXT:    subfic 3, 3, 27
 ; CHECK-NEXT:    blr
   %a = and i8 %x, 1
@@ -57,7 +57,7 @@
 define i32 @add_zext_cmp_mask_wider_result(i8 %x) {
 ; CHECK-LABEL: add_zext_cmp_mask_wider_result:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 3, 3, 0, 31, 31
+; CHECK-NEXT:    clrlwi 3, 3, 31
 ; CHECK-NEXT:    subfic 3, 3, 27
 ; CHECK-NEXT:    blr
   %a = and i8 %x, 1
@@ -70,7 +70,7 @@
 define i8 @add_zext_cmp_mask_narrower_result(i32 %x) {
 ; CHECK-LABEL: add_zext_cmp_mask_narrower_result:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 3, 3, 0, 31, 31
+; CHECK-NEXT:    clrlwi 3, 3, 31
 ; CHECK-NEXT:    subfic 3, 3, 43
 ; CHECK-NEXT:    blr
   %a = and i32 %x, 1
diff --git a/llvm/test/CodeGen/PowerPC/branch_coalesce.ll b/llvm/test/CodeGen/PowerPC/branch_coalesce.ll
--- a/llvm/test/CodeGen/PowerPC/branch_coalesce.ll
+++ b/llvm/test/CodeGen/PowerPC/branch_coalesce.ll
@@ -7,8 +7,8 @@
 define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
 
 ; CHECK-LABEL: @testBranchCoal
-; CHECK: cmplwi [[CMPR:[0-7]+]], 6, 0
-; CHECK: beq [[CMPR]], .LBB[[LAB1:[0-9_]+]]
+; CHECK: cmplwi 6, 0
+; CHECK: beq 0, .LBB[[LAB1:[0-9_]+]]
 ; CHECK-DAG: addis [[LD1REG:[0-9]+]], 2, .LCPI0_0@toc@ha
 ; CHECK-DAG: addis [[LD2REG:[0-9]+]], 2, .LCPI0_1@toc@ha
 ; CHECK-DAG: xxlxor 2, 2, 2
@@ -22,7 +22,7 @@
 
 ; CHECK-NOCOALESCE-LABEL: testBranchCoal:
 ; CHECK-NOCOALESCE:       # %bb.0: # %entry
-; CHECK-NOCOALESCE-NEXT:    cmplwi 0, 6, 0
+; CHECK-NOCOALESCE-NEXT:    cmplwi 6, 0
 ; CHECK-NOCOALESCE-NEXT:    bne 0, .LBB0_5
 ; CHECK-NOCOALESCE-NEXT:  # %bb.1: # %entry
 ; CHECK-NOCOALESCE-NEXT:    bne 0, .LBB0_6
diff --git a/llvm/test/CodeGen/PowerPC/bswap64.ll b/llvm/test/CodeGen/PowerPC/bswap64.ll
--- a/llvm/test/CodeGen/PowerPC/bswap64.ll
+++ b/llvm/test/CodeGen/PowerPC/bswap64.ll
@@ -11,7 +11,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mtvsrdd 34, 3, 3
 ; CHECK-NEXT:    xxbrd 0, 34
-; CHECK-NEXT:    mfvsrd 3, 0
+; CHECK-NEXT:    mffprd 3, 0
 ; CHECK-NEXT:    blr
 ;
 ; NO-ALTIVEC-LABEL: bswap64:
diff --git a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
--- a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
+++ b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
@@ -832,8 +832,8 @@
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    rldimi r6, r5, 32, 0
 ; P8BE-NEXT:    rldimi r4, r3, 32, 0
-; P8BE-NEXT:    mtvsrd f0, r6
-; P8BE-NEXT:    mtvsrd f1, r4
+; P8BE-NEXT:    mtfprd f0, r6
+; P8BE-NEXT:    mtfprd f1, r4
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8BE-NEXT:    blr
 ;
@@ -841,8 +841,8 @@
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    rldimi r3, r4, 32, 0
 ; P8LE-NEXT:    rldimi r5, r6, 32, 0
-; P8LE-NEXT:    mtvsrd f0, r3
-; P8LE-NEXT:    mtvsrd f1, r5
+; P8LE-NEXT:    mtfprd f0, r3
+; P8LE-NEXT:    mtfprd f1, r5
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8LE-NEXT:    blr
 entry:
@@ -1120,8 +1120,8 @@
 ; P8BE-NEXT:    lwz r3, 72(r3)
 ; P8BE-NEXT:    rldimi r5, r4, 32, 0
 ; P8BE-NEXT:    rldimi r3, r6, 32, 0
-; P8BE-NEXT:    mtvsrd f0, r5
-; P8BE-NEXT:    mtvsrd f1, r3
+; P8BE-NEXT:    mtfprd f0, r5
+; P8BE-NEXT:    mtfprd f1, r3
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8BE-NEXT:    blr
 ;
@@ -1133,8 +1133,8 @@
 ; P8LE-NEXT:    lwz r3, 352(r3)
 ; P8LE-NEXT:    rldimi r4, r5, 32, 0
 ; P8LE-NEXT:    rldimi r6, r3, 32, 0
-; P8LE-NEXT:    mtvsrd f0, r4
-; P8LE-NEXT:    mtvsrd f1, r6
+; P8LE-NEXT:    mtfprd f0, r4
+; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8LE-NEXT:    blr
 entry:
@@ -1190,8 +1190,8 @@
 ; P8BE-NEXT:    lwz r3, 4(r3)
 ; P8BE-NEXT:    rldimi r5, r4, 32, 0
 ; P8BE-NEXT:    rldimi r3, r6, 32, 0
-; P8BE-NEXT:    mtvsrd f0, r5
-; P8BE-NEXT:    mtvsrd f1, r3
+; P8BE-NEXT:    mtfprd f0, r5
+; P8BE-NEXT:    mtfprd f1, r3
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8BE-NEXT:    blr
 ;
@@ -1205,8 +1205,8 @@
 ; P8LE-NEXT:    lwz r3, 32(r3)
 ; P8LE-NEXT:    rldimi r4, r5, 32, 0
 ; P8LE-NEXT:    rldimi r6, r3, 32, 0
-; P8LE-NEXT:    mtvsrd f0, r4
-; P8LE-NEXT:    mtvsrd f1, r6
+; P8LE-NEXT:    mtfprd f0, r4
+; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8LE-NEXT:    blr
 entry:
@@ -1246,13 +1246,13 @@
 ;
 ; P8BE-LABEL: spltRegVali:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    mtvsrwz f0, r3
+; P8BE-NEXT:    mtfprwz f0, r3
 ; P8BE-NEXT:    xxspltw v2, vs0, 1
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltRegVali:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    mtvsrwz f0, r3
+; P8LE-NEXT:    mtfprwz f0, r3
 ; P8LE-NEXT:    xxspltw v2, vs0, 1
 ; P8LE-NEXT:    blr
 entry:
@@ -1282,7 +1282,7 @@
 ; P8LE-LABEL: spltMemVali:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
-; P8LE-NEXT:    xxpermdi vs0, f0, f0, 2
+; P8LE-NEXT:    xxswapd vs0, f0
 ; P8LE-NEXT:    xxspltw v2, vs0, 3
 ; P8LE-NEXT:    blr
 entry:
@@ -2351,8 +2351,8 @@
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    rldimi r6, r5, 32, 0
 ; P8BE-NEXT:    rldimi r4, r3, 32, 0
-; P8BE-NEXT:    mtvsrd f0, r6
-; P8BE-NEXT:    mtvsrd f1, r4
+; P8BE-NEXT:    mtfprd f0, r6
+; P8BE-NEXT:    mtfprd f1, r4
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8BE-NEXT:    blr
 ;
@@ -2360,8 +2360,8 @@
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    rldimi r3, r4, 32, 0
 ; P8LE-NEXT:    rldimi r5, r6, 32, 0
-; P8LE-NEXT:    mtvsrd f0, r3
-; P8LE-NEXT:    mtvsrd f1, r5
+; P8LE-NEXT:    mtfprd f0, r3
+; P8LE-NEXT:    mtfprd f1, r5
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8LE-NEXT:    blr
 entry:
@@ -2639,8 +2639,8 @@
 ; P8BE-NEXT:    lwz r3, 72(r3)
 ; P8BE-NEXT:    rldimi r5, r4, 32, 0
 ; P8BE-NEXT:    rldimi r3, r6, 32, 0
-; P8BE-NEXT:    mtvsrd f0, r5
-; P8BE-NEXT:    mtvsrd f1, r3
+; P8BE-NEXT:    mtfprd f0, r5
+; P8BE-NEXT:    mtfprd f1, r3
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8BE-NEXT:    blr
 ;
@@ -2652,8 +2652,8 @@
 ; P8LE-NEXT:    lwz r3, 352(r3)
 ; P8LE-NEXT:    rldimi r4, r5, 32, 0
 ; P8LE-NEXT:    rldimi r6, r3, 32, 0
-; P8LE-NEXT:    mtvsrd f0, r4
-; P8LE-NEXT:    mtvsrd f1, r6
+; P8LE-NEXT:    mtfprd f0, r4
+; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8LE-NEXT:    blr
 entry:
@@ -2709,8 +2709,8 @@
 ; P8BE-NEXT:    lwz r3, 4(r3)
 ; P8BE-NEXT:    rldimi r5, r4, 32, 0
 ; P8BE-NEXT:    rldimi r3, r6, 32, 0
-; P8BE-NEXT:    mtvsrd f0, r5
-; P8BE-NEXT:    mtvsrd f1, r3
+; P8BE-NEXT:    mtfprd f0, r5
+; P8BE-NEXT:    mtfprd f1, r3
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8BE-NEXT:    blr
 ;
@@ -2724,8 +2724,8 @@
 ; P8LE-NEXT:    lwz r3, 32(r3)
 ; P8LE-NEXT:    rldimi r4, r5, 32, 0
 ; P8LE-NEXT:    rldimi r6, r3, 32, 0
-; P8LE-NEXT:    mtvsrd f0, r4
-; P8LE-NEXT:    mtvsrd f1, r6
+; P8LE-NEXT:    mtfprd f0, r4
+; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8LE-NEXT:    blr
 entry:
@@ -2765,13 +2765,13 @@
 ;
 ; P8BE-LABEL: spltRegValui:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    mtvsrwz f0, r3
+; P8BE-NEXT:    mtfprwz f0, r3
 ; P8BE-NEXT:    xxspltw v2, vs0, 1
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltRegValui:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    mtvsrwz f0, r3
+; P8LE-NEXT:    mtfprwz f0, r3
 ; P8LE-NEXT:    xxspltw v2, vs0, 1
 ; P8LE-NEXT:    blr
 entry:
@@ -2801,7 +2801,7 @@
 ; P8LE-LABEL: spltMemValui:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
-; P8LE-NEXT:    xxpermdi vs0, f0, f0, 2
+; P8LE-NEXT:    xxswapd vs0, f0
 ; P8LE-NEXT:    xxspltw v2, vs0, 3
 ; P8LE-NEXT:    blr
 entry:
@@ -3884,15 +3884,15 @@
 ;
 ; P8BE-LABEL: fromRegsll:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    mtvsrd f0, r4
-; P8BE-NEXT:    mtvsrd f1, r3
+; P8BE-NEXT:    mtfprd f0, r4
+; P8BE-NEXT:    mtfprd f1, r3
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromRegsll:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    mtvsrd f0, r3
-; P8LE-NEXT:    mtvsrd f1, r4
+; P8LE-NEXT:    mtfprd f0, r3
+; P8LE-NEXT:    mtfprd f1, r4
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8LE-NEXT:    blr
 entry:
@@ -4103,8 +4103,8 @@
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    ld r4, 144(r3)
 ; P8BE-NEXT:    ld r3, 32(r3)
-; P8BE-NEXT:    mtvsrd f0, r4
-; P8BE-NEXT:    mtvsrd f1, r3
+; P8BE-NEXT:    mtfprd f0, r4
+; P8BE-NEXT:    mtfprd f1, r3
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8BE-NEXT:    blr
 ;
@@ -4112,8 +4112,8 @@
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    ld r4, 32(r3)
 ; P8LE-NEXT:    ld r3, 144(r3)
-; P8LE-NEXT:    mtvsrd f0, r4
-; P8LE-NEXT:    mtvsrd f1, r3
+; P8LE-NEXT:    mtfprd f0, r4
+; P8LE-NEXT:    mtfprd f1, r3
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8LE-NEXT:    blr
 entry:
@@ -4151,8 +4151,8 @@
 ; P8BE-NEXT:    add r3, r3, r4
 ; P8BE-NEXT:    ld r4, 8(r3)
 ; P8BE-NEXT:    ld r3, 32(r3)
-; P8BE-NEXT:    mtvsrd f0, r4
-; P8BE-NEXT:    mtvsrd f1, r3
+; P8BE-NEXT:    mtfprd f0, r4
+; P8BE-NEXT:    mtfprd f1, r3
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8BE-NEXT:    blr
 ;
@@ -4162,8 +4162,8 @@
 ; P8LE-NEXT:    add r3, r3, r4
 ; P8LE-NEXT:    ld r4, 32(r3)
 ; P8LE-NEXT:    ld r3, 8(r3)
-; P8LE-NEXT:    mtvsrd f0, r4
-; P8LE-NEXT:    mtvsrd f1, r3
+; P8LE-NEXT:    mtfprd f0, r4
+; P8LE-NEXT:    mtfprd f1, r3
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8LE-NEXT:    blr
 entry:
@@ -4193,13 +4193,13 @@
 ;
 ; P8BE-LABEL: spltRegValll:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    mtvsrd f0, r3
+; P8BE-NEXT:    mtfprd f0, r3
 ; P8BE-NEXT:    xxspltd v2, vs0, 0
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltRegValll:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    mtvsrd f0, r3
+; P8LE-NEXT:    mtfprd f0, r3
 ; P8LE-NEXT:    xxspltd v2, vs0, 0
 ; P8LE-NEXT:    blr
 entry:
@@ -5072,15 +5072,15 @@
 ;
 ; P8BE-LABEL: fromRegsull:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    mtvsrd f0, r4
-; P8BE-NEXT:    mtvsrd f1, r3
+; P8BE-NEXT:    mtfprd f0, r4
+; P8BE-NEXT:    mtfprd f1, r3
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromRegsull:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    mtvsrd f0, r3
-; P8LE-NEXT:    mtvsrd f1, r4
+; P8LE-NEXT:    mtfprd f0, r3
+; P8LE-NEXT:    mtfprd f1, r4
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8LE-NEXT:    blr
 entry:
@@ -5291,8 +5291,8 @@
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    ld r4, 144(r3)
 ; P8BE-NEXT:    ld r3, 32(r3)
-; P8BE-NEXT:    mtvsrd f0, r4
-; P8BE-NEXT:    mtvsrd f1, r3
+; P8BE-NEXT:    mtfprd f0, r4
+; P8BE-NEXT:    mtfprd f1, r3
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8BE-NEXT:    blr
 ;
@@ -5300,8 +5300,8 @@
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    ld r4, 32(r3)
 ; P8LE-NEXT:    ld r3, 144(r3)
-; P8LE-NEXT:    mtvsrd f0, r4
-; P8LE-NEXT:    mtvsrd f1, r3
+; P8LE-NEXT:    mtfprd f0, r4
+; P8LE-NEXT:    mtfprd f1, r3
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8LE-NEXT:    blr
 entry:
@@ -5339,8 +5339,8 @@
 ; P8BE-NEXT:    add r3, r3, r4
 ; P8BE-NEXT:    ld r4, 8(r3)
 ; P8BE-NEXT:    ld r3, 32(r3)
-; P8BE-NEXT:    mtvsrd f0, r4
-; P8BE-NEXT:    mtvsrd f1, r3
+; P8BE-NEXT:    mtfprd f0, r4
+; P8BE-NEXT:    mtfprd f1, r3
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8BE-NEXT:    blr
 ;
@@ -5350,8 +5350,8 @@
 ; P8LE-NEXT:    add r3, r3, r4
 ; P8LE-NEXT:    ld r4, 32(r3)
 ; P8LE-NEXT:    ld r3, 8(r3)
-; P8LE-NEXT:    mtvsrd f0, r4
-; P8LE-NEXT:    mtvsrd f1, r3
+; P8LE-NEXT:    mtfprd f0, r4
+; P8LE-NEXT:    mtfprd f1, r3
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
 ; P8LE-NEXT:    blr
 entry:
@@ -5381,13 +5381,13 @@
 ;
 ; P8BE-LABEL: spltRegValull:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    mtvsrd f0, r3
+; P8BE-NEXT:    mtfprd f0, r3
 ; P8BE-NEXT:    xxspltd v2, vs0, 0
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltRegValull:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    mtvsrd f0, r3
+; P8LE-NEXT:    mtfprd f0, r3
 ; P8LE-NEXT:    xxspltd v2, vs0, 0
 ; P8LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
@@ -891,7 +891,7 @@
     %3 = LI -37
     %4 = RLDCL_rec %0, killed %3, 0, implicit-def $cr0
     ; CHECK: RLDICL_rec %0, 27, 0, implicit-def $cr0
-    ; CHECK-LATE: rldicl. 5, 3, 27, 0
+    ; CHECK-LATE: rotldi. 5, 3, 27
     %5 = COPY killed $cr0
     %6 = ISEL8 %2, %0, %5.sub_eq
     $x3 = COPY %6
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
@@ -3728,7 +3728,7 @@
     %3 = LI 37
     %4 = RLDCL_rec %0, killed %3, 0, implicit-def $cr0
     ; CHECK: RLDICL_rec %0, 37, 0, implicit-def $cr0
-    ; CHECK-LATE: rldicl. 5, 3, 37, 0
+    ; CHECK-LATE: rotldi. 5, 3, 37
     %5 = COPY killed $cr0
     %6 = ISEL8 %2, %0, %5.sub_eq
     $x3 = COPY %6
diff --git a/llvm/test/CodeGen/PowerPC/crbits.ll b/llvm/test/CodeGen/PowerPC/crbits.ll
--- a/llvm/test/CodeGen/PowerPC/crbits.ll
+++ b/llvm/test/CodeGen/PowerPC/crbits.ll
@@ -145,7 +145,7 @@
   ret i32 %cond
 
 ; CHECK-LABEL: @exttest7
-; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 5
+; CHECK-DAG: cmpwi 3, 5
 ; CHECK-DAG: li [[REG1:[0-9]+]], 8
 ; CHECK-DAG: li [[REG2:[0-9]+]], 7
 ; CHECK: isel 3, [[REG2]], [[REG1]],
diff --git a/llvm/test/CodeGen/PowerPC/dform-adjust.ll b/llvm/test/CodeGen/PowerPC/dform-adjust.ll
--- a/llvm/test/CodeGen/PowerPC/dform-adjust.ll
+++ b/llvm/test/CodeGen/PowerPC/dform-adjust.ll
@@ -19,7 +19,7 @@
 ; CHECK-NEXT:    ldx 3, 3, 8
 ; CHECK-NEXT:    mffprd 8, 0
 ; CHECK-NEXT:    mfvsrld 10, 1
-; CHECK-NEXT:    mfvsrd 11, 1
+; CHECK-NEXT:    mffprd 11, 1
 ; CHECK-NEXT:    mulld 8, 9, 8
 ; CHECK-NEXT:    mulld 5, 8, 5
 ; CHECK-NEXT:    mulld 5, 5, 10
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel.ll b/llvm/test/CodeGen/PowerPC/expand-isel.ll
--- a/llvm/test/CodeGen/PowerPC/expand-isel.ll
+++ b/llvm/test/CodeGen/PowerPC/expand-isel.ll
@@ -11,7 +11,7 @@
 
 ; CHECK-LABEL: @testExpandISELToIfElse
 ; CHECK: addi r5, r3, 1
-; CHECK-NEXT: cmpwi cr0, r3, 0
+; CHECK-NEXT: cmpwi r3, 0
 ; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
@@ -101,7 +101,7 @@
   ret i32 %add
 
 ; CHECK-LABEL: @testExpandISELsTo2ORIs1ADDI
-; CHECK: cmpwi cr0, r7, 0
+; CHECK: cmpwi r7, 0
 ; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: ori r4, r6, 0
@@ -127,7 +127,7 @@
   ret i32 %add2
 
 ; CHECK-LABEL: @testExpandISELsTo1ORI1ADDI
-; CHECK: cmpwi cr0, r7, 0
+; CHECK: cmpwi r7, 0
 ; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r5, r6, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
@@ -154,7 +154,7 @@
   ret i32 %sub1
 
 ; CHECK-LABEL: @testExpandISELsTo0ORI2ADDIs
-; CHECK: cmpwi cr0, r7, 0
+; CHECK: cmpwi r7, 0
 ; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT:  [[TRUE]]
diff --git a/llvm/test/CodeGen/PowerPC/extract-and-store.ll b/llvm/test/CodeGen/PowerPC/extract-and-store.ll
--- a/llvm/test/CodeGen/PowerPC/extract-and-store.ll
+++ b/llvm/test/CodeGen/PowerPC/extract-and-store.ll
@@ -645,7 +645,7 @@
 ; CHECK-NEXT:    mfvsrd r3, vs34
 ; CHECK-NEXT:    rldicl r6, r3, 32, 56
 ; CHECK-NEXT:    rldicl r3, r3, 56, 56
-; CHECK-NEXT:    mfvsrd r4, f0
+; CHECK-NEXT:    mffprd r4, f0
 ; CHECK-NEXT:    stb r6, 1(r5)
 ; CHECK-NEXT:    stb r3, 2(r5)
 ; CHECK-NEXT:    rldicl r6, r4, 32, 56
@@ -661,7 +661,7 @@
 ; CHECK-BE-NEXT:    xxswapd vs0, vs34
 ; CHECK-BE-NEXT:    mfvsrd r3, vs34
 ; CHECK-BE-NEXT:    rldicl r6, r3, 40, 56
-; CHECK-BE-NEXT:    mfvsrd r4, f0
+; CHECK-BE-NEXT:    mffprd r4, f0
 ; CHECK-BE-NEXT:    stb r6, 0(r5)
 ; CHECK-BE-NEXT:    rldicl r6, r4, 40, 56
 ; CHECK-BE-NEXT:    rldicl r4, r4, 16, 56
@@ -734,7 +734,7 @@
 ; CHECK-NEXT:    rldicl r6, r3, 56, 56
 ; CHECK-NEXT:    stb r4, 1(r5)
 ; CHECK-NEXT:    rldicl r4, r3, 40, 56
-; CHECK-NEXT:    mfvsrd r7, f0
+; CHECK-NEXT:    mffprd r7, f0
 ; CHECK-NEXT:    stb r6, 2(r5)
 ; CHECK-NEXT:    rldicl r6, r3, 24, 56
 ; CHECK-NEXT:    stb r4, 6(r5)
@@ -767,7 +767,7 @@
 ; CHECK-BE-NEXT:    clrldi r6, r3, 56
 ; CHECK-BE-NEXT:    stb r4, 0(r5)
 ; CHECK-BE-NEXT:    rldicl r4, r3, 56, 56
-; CHECK-BE-NEXT:    mfvsrd r7, f0
+; CHECK-BE-NEXT:    mffprd r7, f0
 ; CHECK-BE-NEXT:    stb r6, 3(r5)
 ; CHECK-BE-NEXT:    rldicl r6, r3, 8, 56
 ; CHECK-BE-NEXT:    stb r4, 4(r5)
diff --git a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll
--- a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll
@@ -343,7 +343,7 @@
 ; CHECK-DAG:     std r7, 64(r1)
 ; CHECK-DAG:     std r6, 56(r1)
 ; CHECK-DAG:     std r4, 40(r1)
-; CHECK-DAG:     cmpwi cr0, r3, 1
+; CHECK-DAG:     cmpwi r3, 1
 ; CHECK-DAG:     std r5, 48(r1)
 ; CHECK-DAG:     addis [[REG:r[0-9]+]], r2, .LCPI17_0@toc@ha
 ; CHECK-DAG:     addi [[REG1:r[0-9]+]], [[REG]], .LCPI17_0@toc@l
diff --git a/llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll b/llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
--- a/llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
@@ -10,7 +10,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfs f1, -4(r1)
-; CHECK-NEXT:    mfvsrwz r3, f0
+; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
@@ -43,7 +43,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfd f1, -8(r1)
-; CHECK-NEXT:    mfvsrwz r3, f0
+; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
@@ -76,7 +76,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfs f1, -4(r1)
-; CHECK-NEXT:    mfvsrwz r3, f0
+; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
@@ -109,7 +109,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfd f1, -8(r1)
-; CHECK-NEXT:    mfvsrwz r3, f0
+; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
@@ -208,7 +208,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfs f1, -4(r1)
-; CHECK-NEXT:    mfvsrwz r3, f0
+; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
@@ -241,7 +241,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfd f1, -8(r1)
-; CHECK-NEXT:    mfvsrwz r3, f0
+; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
@@ -340,7 +340,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpuxws f0, f1
 ; CHECK-NEXT:    stfs f1, -4(r1)
-; CHECK-NEXT:    mfvsrwz r3, f0
+; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
@@ -373,7 +373,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpuxws f0, f1
 ; CHECK-NEXT:    stfd f1, -8(r1)
-; CHECK-NEXT:    mfvsrwz r3, f0
+; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll b/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
--- a/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
+++ b/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
@@ -18,7 +18,7 @@
 define i8 @rotl_i8_const_shift(i8 %x) {
 ; CHECK-LABEL: rotl_i8_const_shift:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 4, 3, 27, 0, 31
+; CHECK-NEXT:    rotlwi 4, 3, 27
 ; CHECK-NEXT:    rlwimi 4, 3, 3, 0, 28
 ; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
@@ -42,7 +42,7 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    neg 5, 4
 ; CHECK-NEXT:    clrlwi 6, 3, 16
-; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 31
+; CHECK-NEXT:    clrlwi 4, 4, 28
 ; CHECK-NEXT:    clrlwi 5, 5, 28
 ; CHECK-NEXT:    slw 3, 3, 4
 ; CHECK-NEXT:    srw 4, 6, 5
@@ -55,7 +55,7 @@
 define i32 @rotl_i32(i32 %x, i32 %z) {
 ; CHECK-LABEL: rotl_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwnm 3, 3, 4, 0, 31
+; CHECK-NEXT:    rotlw 3, 3, 4
 ; CHECK-NEXT:    blr
   %f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %z)
   ret i32 %f
@@ -64,7 +64,7 @@
 define i64 @rotl_i64(i64 %x, i64 %z) {
 ; CHECK-LABEL: rotl_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rldcl 3, 3, 4, 0
+; CHECK-NEXT:    rotld 3, 3, 4
 ; CHECK-NEXT:    blr
   %f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)
   ret i64 %f
@@ -98,7 +98,7 @@
 define i8 @rotr_i8_const_shift(i8 %x) {
 ; CHECK-LABEL: rotr_i8_const_shift:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 4, 3, 29, 0, 31
+; CHECK-NEXT:    rotlwi 4, 3, 29
 ; CHECK-NEXT:    rlwimi 4, 3, 5, 0, 26
 ; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
@@ -109,7 +109,7 @@
 define i32 @rotr_i32_const_shift(i32 %x) {
 ; CHECK-LABEL: rotr_i32_const_shift:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 3, 3, 29, 0, 31
+; CHECK-NEXT:    rotlwi 3, 3, 29
 ; CHECK-NEXT:    blr
   %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 3)
   ret i32 %f
@@ -122,7 +122,7 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    neg 5, 4
 ; CHECK-NEXT:    clrlwi 6, 3, 16
-; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 31
+; CHECK-NEXT:    clrlwi 4, 4, 28
 ; CHECK-NEXT:    clrlwi 5, 5, 28
 ; CHECK-NEXT:    srw 4, 6, 4
 ; CHECK-NEXT:    slw 3, 3, 5
@@ -136,7 +136,7 @@
 ; CHECK-LABEL: rotr_i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    neg 4, 4
-; CHECK-NEXT:    rlwnm 3, 3, 4, 0, 31
+; CHECK-NEXT:    rotlw 3, 3, 4
 ; CHECK-NEXT:    blr
   %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z)
   ret i32 %f
@@ -146,7 +146,7 @@
 ; CHECK-LABEL: rotr_i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    neg 4, 4
-; CHECK-NEXT:    rldcl 3, 3, 4, 0
+; CHECK-NEXT:    rotld 3, 3, 4
 ; CHECK-NEXT:    blr
   %f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %z)
   ret i64 %f
diff --git a/llvm/test/CodeGen/PowerPC/funnel-shift.ll b/llvm/test/CodeGen/PowerPC/funnel-shift.ll
--- a/llvm/test/CodeGen/PowerPC/funnel-shift.ll
+++ b/llvm/test/CodeGen/PowerPC/funnel-shift.ll
@@ -44,7 +44,7 @@
 ; CHECK-NEXT:    mulhdu 6, 5, 6
 ; CHECK-NEXT:    rldicl 6, 6, 59, 5
 ; CHECK-NEXT:    mulli 6, 6, 37
-; CHECK-NEXT:    subf. 5, 6, 5
+; CHECK-NEXT:    sub. 5, 5, 6
 ; CHECK-NEXT:    subfic 6, 5, 37
 ; CHECK-NEXT:    sld 5, 3, 5
 ; CHECK-NEXT:    srd 4, 4, 6
@@ -72,7 +72,7 @@
 define i32 @fshl_i32_const_shift(i32 %x, i32 %y) {
 ; CHECK-LABEL: fshl_i32_const_shift:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 4, 4, 9, 0, 31
+; CHECK-NEXT:    rotlwi 4, 4, 9
 ; CHECK-NEXT:    rlwimi 4, 3, 9, 0, 22
 ; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
@@ -85,7 +85,7 @@
 define i32 @fshl_i32_const_overshift(i32 %x, i32 %y) {
 ; CHECK-LABEL: fshl_i32_const_overshift:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 4, 4, 9, 0, 31
+; CHECK-NEXT:    rotlwi 4, 4, 9
 ; CHECK-NEXT:    rlwimi 4, 3, 9, 0, 22
 ; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
@@ -149,7 +149,7 @@
 ; CHECK-NEXT:    mulhdu 6, 5, 6
 ; CHECK-NEXT:    rldicl 6, 6, 59, 5
 ; CHECK-NEXT:    mulli 6, 6, 37
-; CHECK-NEXT:    subf. 5, 6, 5
+; CHECK-NEXT:    sub. 5, 5, 6
 ; CHECK-NEXT:    clrldi 6, 4, 27
 ; CHECK-NEXT:    subfic 7, 5, 37
 ; CHECK-NEXT:    srd 5, 6, 5
@@ -178,7 +178,7 @@
 define i32 @fshr_i32_const_shift(i32 %x, i32 %y) {
 ; CHECK-LABEL: fshr_i32_const_shift:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 4, 4, 23, 0, 31
+; CHECK-NEXT:    rotlwi 4, 4, 23
 ; CHECK-NEXT:    rlwimi 4, 3, 23, 0, 8
 ; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
@@ -191,7 +191,7 @@
 define i32 @fshr_i32_const_overshift(i32 %x, i32 %y) {
 ; CHECK-LABEL: fshr_i32_const_overshift:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 4, 4, 23, 0, 31
+; CHECK-NEXT:    rotlwi 4, 4, 23
 ; CHECK-NEXT:    rlwimi 4, 3, 23, 0, 8
 ; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/inlineasm-i64-reg.ll b/llvm/test/CodeGen/PowerPC/inlineasm-i64-reg.ll
--- a/llvm/test/CodeGen/PowerPC/inlineasm-i64-reg.ll
+++ b/llvm/test/CodeGen/PowerPC/inlineasm-i64-reg.ll
@@ -81,7 +81,7 @@
 ; CHECK:     sc
 ; CHECK:     #NO_APP
                                       
-; CHECK:     cmpwi {{[0-9]+}}, [[REG]], 1
+; CHECK:     cmpwi [[REG]], 1
 
 ; CHECK: blr
 
diff --git a/llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll b/llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll
--- a/llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll
+++ b/llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll
@@ -20,7 +20,7 @@
 define dso_local signext i32 @spillCRSET(i32 signext %p1, i32 signext %p2) {
 ; CHECK-LABEL: spillCRSET:
 ; CHECK:        # %bb.2:
-; CHECK-DAG:    crnor [[CREG:.*]]*cr5+lt, eq, eq
+; CHECK-DAG:    crnot [[CREG:.*]]*cr5+lt, eq
 ; CHECK-DAG:    mfocrf [[REG2:.*]], [[CREG]]
 ; CHECK-DAG:    rlwinm [[REG2]], [[REG2]]
 ; CHECK:        .LBB0_3:
diff --git a/llvm/test/CodeGen/PowerPC/load-and-splat.ll b/llvm/test/CodeGen/PowerPC/load-and-splat.ll
--- a/llvm/test/CodeGen/PowerPC/load-and-splat.ll
+++ b/llvm/test/CodeGen/PowerPC/load-and-splat.ll
@@ -40,7 +40,7 @@
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    addi r4, r4, 12
 ; P8-NEXT:    lfiwzx f0, 0, r4
-; P8-NEXT:    xxpermdi vs0, f0, f0, 2
+; P8-NEXT:    xxswapd vs0, f0
 ; P8-NEXT:    xxspltw v2, vs0, 3
 ; P8-NEXT:    stvx v2, 0, r3
 ; P8-NEXT:    blr
@@ -65,7 +65,7 @@
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    addi r4, r4, 12
 ; P8-NEXT:    lfiwzx f0, 0, r4
-; P8-NEXT:    xxpermdi vs0, f0, f0, 2
+; P8-NEXT:    xxswapd vs0, f0
 ; P8-NEXT:    xxspltw v2, vs0, 3
 ; P8-NEXT:    stvx v2, 0, r3
 ; P8-NEXT:    blr
@@ -110,7 +110,7 @@
 ; P8-LABEL: unadjusted_lxvwsx:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    lfiwzx f0, 0, r3
-; P8-NEXT:    xxpermdi vs0, f0, f0, 2
+; P8-NEXT:    xxswapd vs0, f0
 ; P8-NEXT:    xxspltw v2, vs0, 3
 ; P8-NEXT:    blr
   entry:
@@ -130,7 +130,7 @@
 ; P8-LABEL: adjusted_lxvwsx:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    ld r3, 0(r3)
-; P8-NEXT:    mtvsrd f0, r3
+; P8-NEXT:    mtfprd f0, r3
 ; P8-NEXT:    xxswapd v2, vs0
 ; P8-NEXT:    xxspltw v2, v2, 2
 ; P8-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/load-v4i8-improved.ll b/llvm/test/CodeGen/PowerPC/load-v4i8-improved.ll
--- a/llvm/test/CodeGen/PowerPC/load-v4i8-improved.ll
+++ b/llvm/test/CodeGen/PowerPC/load-v4i8-improved.ll
@@ -9,7 +9,7 @@
 ; CHECK-LE-LABEL: test:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    lfiwzx f0, 0, r3
-; CHECK-LE-NEXT:    xxpermdi vs0, f0, f0, 2
+; CHECK-LE-NEXT:    xxswapd vs0, f0
 ; CHECK-LE-NEXT:    xxspltw v2, vs0, 3
 ; CHECK-LE-NEXT:    blr
 
diff --git a/llvm/test/CodeGen/PowerPC/memcmp.ll b/llvm/test/CodeGen/PowerPC/memcmp.ll
--- a/llvm/test/CodeGen/PowerPC/memcmp.ll
+++ b/llvm/test/CodeGen/PowerPC/memcmp.ll
@@ -6,9 +6,9 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ldbrx 3, 0, 3
 ; CHECK-NEXT:    ldbrx 4, 0, 4
-; CHECK-NEXT:    subfc 5, 3, 4
+; CHECK-NEXT:    subc 5, 4, 3
 ; CHECK-NEXT:    subfe 5, 4, 4
-; CHECK-NEXT:    subfc 4, 4, 3
+; CHECK-NEXT:    subc 4, 3, 4
 ; CHECK-NEXT:    subfe 3, 3, 3
 ; CHECK-NEXT:    neg 4, 5
 ; CHECK-NEXT:    neg 3, 3
diff --git a/llvm/test/CodeGen/PowerPC/optcmp.ll b/llvm/test/CodeGen/PowerPC/optcmp.ll
--- a/llvm/test/CodeGen/PowerPC/optcmp.ll
+++ b/llvm/test/CodeGen/PowerPC/optcmp.ll
@@ -37,7 +37,7 @@
 
 ; CHECK-LABEL: @fool
 ; CHECK-NO-ISEL-LABEL: @fool
-; CHECK: subf. [[REG:[0-9]+]], 4, 3
+; CHECK: sub. [[REG:[0-9]+]], 3, 4
 ; CHECK: isel 3, 3, 4, 1
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: ori 3, 4, 0
@@ -56,7 +56,7 @@
 
 ; CHECK-LABEL: @foolb
 ; CHECK-NO-ISEL-LABEL: @foolb
-; CHECK: subf. [[REG:[0-9]+]], 4, 3
+; CHECK: sub. [[REG:[0-9]+]], 3, 4
 ; CHECK: isel 3, 4, 3, 1
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL-NEXT: b .LBB
@@ -74,7 +74,7 @@
 
 ; CHECK-LABEL: @foolc
 ; CHECK-NO-ISEL-LABEL: @foolc
-; CHECK: subf. [[REG:[0-9]+]], 3, 4
+; CHECK: sub. [[REG:[0-9]+]], 4, 3
 ; CHECK: isel 3, 3, 4, 0
 ; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: ori 3, 4, 0
@@ -92,7 +92,7 @@
 
 ; CHECK-LABEL: @foold
 ; CHECK-NO-ISEL-LABEL: @foold
-; CHECK: subf. [[REG:[0-9]+]], 3, 4
+; CHECK: sub. [[REG:[0-9]+]], 4, 3
 ; CHECK: isel 3, 3, 4, 1
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: ori 3, 4, 0
@@ -110,7 +110,7 @@
 
 ; CHECK-LABEL: @foold2
 ; CHECK-NO-ISEL-LABEL: @foold2
-; CHECK: subf. [[REG:[0-9]+]], 4, 3
+; CHECK: sub. [[REG:[0-9]+]], 3, 4
 ; CHECK: isel 3, 3, 4, 0
 ; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: ori 3, 4, 0
diff --git a/llvm/test/CodeGen/PowerPC/optimize-andiso.ll b/llvm/test/CodeGen/PowerPC/optimize-andiso.ll
--- a/llvm/test/CodeGen/PowerPC/optimize-andiso.ll
+++ b/llvm/test/CodeGen/PowerPC/optimize-andiso.ll
@@ -15,8 +15,8 @@
 ; CHECK-NEXT:    li r4, 3
 ; CHECK-NEXT:    isel r4, r5, r4, eq
 ; CHECK-NEXT:    srd r3, r3, r4
-; CHECK-NEXT:    rlwinm r3, r3, 0, 9, 31
-; CHECK-NEXT:    mtvsrd f0, r3
+; CHECK-NEXT:    clrlwi r3, r3, 9
+; CHECK-NEXT:    mtfprd f0, r3
 ; CHECK-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-NEXT:    xscvspdpn f1, vs0
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
--- a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
+++ b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
@@ -21,7 +21,7 @@
 ; CHECK: sldi r3, r3, 56
 ; CHECK: mtvsrd v2, r3
 ; CHECK-LE-LABEL: buildc
-; CHECK-LE: mtvsrd f0, r3
+; CHECK-LE: mtfprd f0, r3
 ; CHECK-LE: xxswapd v2, vs0
 }
 
@@ -35,7 +35,7 @@
 ; CHECK: sldi r3, r3, 48
 ; CHECK: mtvsrd v2, r3
 ; CHECK-LE-LABEL: builds
-; CHECK-LE: mtvsrd f0, r3
+; CHECK-LE: mtfprd f0, r3
 ; CHECK-LE: xxswapd v2, vs0
 }
 
@@ -46,10 +46,10 @@
   %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
   ret <4 x i32> %splat.splat
 ; CHECK-LABEL: buildi
-; CHECK: mtvsrwz f0, r3
+; CHECK: mtfprwz f0, r3
 ; CHECK: xxspltw v2, vs0, 1
 ; CHECK-LE-LABEL: buildi
-; CHECK-LE: mtvsrwz f0, r3
+; CHECK-LE: mtfprwz f0, r3
 ; CHECK-LE: xxspltw v2, vs0, 1
 }
 
@@ -60,9 +60,9 @@
   %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %splat.splat
 ; CHECK-LABEL: buildl
-; CHECK: mtvsrd f0, r3
+; CHECK: mtfprd f0, r3
 ; CHECK-LE-LABEL: buildl
-; CHECK-LE: mtvsrd f0, r3
+; CHECK-LE: mtfprd f0, r3
 ; CHECK-LE: xxspltd v2, vs0, 0
 }
 
@@ -107,7 +107,7 @@
 ; CHECK: rldicl r3, r3, 8, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc0
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: clrldi r3, r3, 56
 ; CHECK-LE: extsb r3, r3
 }
@@ -122,7 +122,7 @@
 ; CHECK: rldicl r3, r3, 16, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc1
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 56, 56
 ; CHECK-LE: extsb r3, r3
 }
@@ -137,7 +137,7 @@
 ; CHECK: rldicl r3, r3, 24, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc2
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 48, 56
 ; CHECK-LE: extsb r3, r3
 }
@@ -152,7 +152,7 @@
 ; CHECK: rldicl r3, r3, 32, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc3
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 40, 56
 ; CHECK-LE: extsb r3, r3
 }
@@ -167,7 +167,7 @@
 ; CHECK: rldicl r3, r3, 40, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc4
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 32, 56
 ; CHECK-LE: extsb r3, r3
 }
@@ -182,7 +182,7 @@
 ; CHECK: rldicl r3, r3, 48, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc5
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 24, 56
 ; CHECK-LE: extsb r3, r3
 }
@@ -197,7 +197,7 @@
 ; CHECK: rldicl r3, r3, 56, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc6
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 16, 56
 ; CHECK-LE: extsb r3, r3
 }
@@ -212,7 +212,7 @@
 ; CHECK: clrldi r3, r3, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc7
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 8, 56
 ; CHECK-LE: extsb r3, r3
 }
@@ -223,7 +223,7 @@
   %vecext = extractelement <16 x i8> %vsc, i32 8
   ret i8 %vecext
 ; CHECK-LABEL: @getsc8
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 8, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc8
@@ -238,7 +238,7 @@
   %vecext = extractelement <16 x i8> %vsc, i32 9
   ret i8 %vecext
 ; CHECK-LABEL: @getsc9
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 16, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc9
@@ -253,7 +253,7 @@
   %vecext = extractelement <16 x i8> %vsc, i32 10
   ret i8 %vecext
 ; CHECK-LABEL: @getsc10
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 24, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc10
@@ -268,7 +268,7 @@
   %vecext = extractelement <16 x i8> %vsc, i32 11
   ret i8 %vecext
 ; CHECK-LABEL: @getsc11
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 32, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc11
@@ -283,7 +283,7 @@
   %vecext = extractelement <16 x i8> %vsc, i32 12
   ret i8 %vecext
 ; CHECK-LABEL: @getsc12
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 40, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc12
@@ -298,7 +298,7 @@
   %vecext = extractelement <16 x i8> %vsc, i32 13
   ret i8 %vecext
 ; CHECK-LABEL: @getsc13
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 48, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc13
@@ -313,7 +313,7 @@
   %vecext = extractelement <16 x i8> %vsc, i32 14
   ret i8 %vecext
 ; CHECK-LABEL: @getsc14
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 56, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc14
@@ -328,7 +328,7 @@
   %vecext = extractelement <16 x i8> %vsc, i32 15
   ret i8 %vecext
 ; CHECK-LABEL: @getsc15
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: clrldi  r3, r3, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc15
@@ -346,7 +346,7 @@
 ; CHECK: mfvsrd r3, v2
 ; CHECK: rldicl r3, r3, 8, 56
 ; CHECK-LE-LABEL: @getuc0
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: clrldi r3, r3, 56
 }
 
@@ -359,7 +359,7 @@
 ; CHECK: mfvsrd r3, v2
 ; CHECK: rldicl r3, r3, 16, 56
 ; CHECK-LE-LABEL: @getuc1
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 56, 56
 }
 
@@ -372,7 +372,7 @@
 ; CHECK: mfvsrd r3, v2
 ; CHECK: rldicl r3, r3, 24, 56
 ; CHECK-LE-LABEL: @getuc2
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 48, 56
 }
 
@@ -385,7 +385,7 @@
 ; CHECK: mfvsrd r3, v2
 ; CHECK: rldicl r3, r3, 32, 56
 ; CHECK-LE-LABEL: @getuc3
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 40, 56
 }
 
@@ -398,7 +398,7 @@
 ; CHECK: mfvsrd r3, v2
 ; CHECK: rldicl r3, r3, 40, 56
 ; CHECK-LE-LABEL: @getuc4
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 32, 56
 }
 
@@ -411,7 +411,7 @@
 ; CHECK: mfvsrd r3, v2
 ; CHECK: rldicl r3, r3, 48, 56
 ; CHECK-LE-LABEL: @getuc5
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 24, 56
 }
 
@@ -424,7 +424,7 @@
 ; CHECK: mfvsrd r3, v2
 ; CHECK: rldicl r3, r3, 56, 56
 ; CHECK-LE-LABEL: @getuc6
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 16, 56
 }
 
@@ -437,7 +437,7 @@
 ; CHECK: mfvsrd r3, v2
 ; CHECK: clrldi   r3, r3, 56
 ; CHECK-LE-LABEL: @getuc7
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 8, 56
 }
 
@@ -447,7 +447,7 @@
   %vecext = extractelement <16 x i8> %vuc, i32 8
   ret i8 %vecext
 ; CHECK-LABEL: @getuc8
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 8, 56
 ; CHECK-LE-LABEL: @getuc8
 ; CHECK-LE: mfvsrd r3, v2
@@ -460,7 +460,7 @@
   %vecext = extractelement <16 x i8> %vuc, i32 9
   ret i8 %vecext
 ; CHECK-LABEL: @getuc9
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 16, 56
 ; CHECK-LE-LABEL: @getuc9
 ; CHECK-LE: mfvsrd r3, v2
@@ -473,7 +473,7 @@
   %vecext = extractelement <16 x i8> %vuc, i32 10
   ret i8 %vecext
 ; CHECK-LABEL: @getuc10
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 24, 56
 ; CHECK-LE-LABEL: @getuc10
 ; CHECK-LE: mfvsrd r3, v2
@@ -486,7 +486,7 @@
   %vecext = extractelement <16 x i8> %vuc, i32 11
   ret i8 %vecext
 ; CHECK-LABEL: @getuc11
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 32, 56
 ; CHECK-LE-LABEL: @getuc11
 ; CHECK-LE: mfvsrd r3, v2
@@ -499,7 +499,7 @@
   %vecext = extractelement <16 x i8> %vuc, i32 12
   ret i8 %vecext
 ; CHECK-LABEL: @getuc12
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 40, 56
 ; CHECK-LE-LABEL: @getuc12
 ; CHECK-LE: mfvsrd r3, v2
@@ -512,7 +512,7 @@
   %vecext = extractelement <16 x i8> %vuc, i32 13
   ret i8 %vecext
 ; CHECK-LABEL: @getuc13
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 48, 56
 ; CHECK-LE-LABEL: @getuc13
 ; CHECK-LE: mfvsrd r3, v2
@@ -525,7 +525,7 @@
   %vecext = extractelement <16 x i8> %vuc, i32 14
   ret i8 %vecext
 ; CHECK-LABEL: @getuc14
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 56, 56
 ; CHECK-LE-LABEL: @getuc14
 ; CHECK-LE: mfvsrd r3, v2
@@ -538,7 +538,7 @@
   %vecext = extractelement <16 x i8> %vuc, i32 15
   ret i8 %vecext
 ; CHECK-LABEL: @getuc15
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: clrldi   r3, r3, 56
 ; CHECK-LE-LABEL: @getuc15
 ; CHECK-LE: mfvsrd r3, v2
@@ -611,7 +611,7 @@
 ; CHECK: rldicl r3, r3, 16, 48
 ; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss0
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: clrldi r3, r3, 48
 ; CHECK-LE: extsh r3, r3
 }
@@ -626,7 +626,7 @@
 ; CHECK: rldicl r3, r3, 32, 48
 ; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss1
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 48, 48
 ; CHECK-LE: extsh r3, r3
 }
@@ -641,7 +641,7 @@
 ; CHECK: rldicl r3, r3, 48, 48
 ; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss2
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 32, 48
 ; CHECK-LE: extsh r3, r3
 }
@@ -656,7 +656,7 @@
 ; CHECK: clrldi r3, r3, 48
 ; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss3
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 16, 48
 ; CHECK-LE: extsh r3, r3
 }
@@ -667,7 +667,7 @@
   %vecext = extractelement <8 x i16> %vss, i32 4
   ret i16 %vecext
 ; CHECK-LABEL: @getss4
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 16, 48
 ; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss4
@@ -682,7 +682,7 @@
   %vecext = extractelement <8 x i16> %vss, i32 5
   ret i16 %vecext
 ; CHECK-LABEL: @getss5
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 32, 48
 ; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss5
@@ -697,7 +697,7 @@
   %vecext = extractelement <8 x i16> %vss, i32 6
   ret i16 %vecext
 ; CHECK-LABEL: @getss6
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 48, 48
 ; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss6
@@ -712,7 +712,7 @@
   %vecext = extractelement <8 x i16> %vss, i32 7
   ret i16 %vecext
 ; CHECK-LABEL: @getss7
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: clrldi  r3, r3, 48
 ; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss7
@@ -730,7 +730,7 @@
 ; CHECK: mfvsrd r3, v2
 ; CHECK: rldicl r3, r3, 16, 48
 ; CHECK-LE-LABEL: @getus0
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: clrldi r3, r3, 48
 }
 
@@ -743,7 +743,7 @@
 ; CHECK: mfvsrd r3, v2
 ; CHECK: rldicl r3, r3, 32, 48
 ; CHECK-LE-LABEL: @getus1
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 48, 48
 }
 
@@ -756,7 +756,7 @@
 ; CHECK: mfvsrd r3, v2
 ; CHECK: rldicl r3, r3, 48, 48
 ; CHECK-LE-LABEL: @getus2
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 32, 48
 }
 
@@ -769,7 +769,7 @@
 ; CHECK: mfvsrd r3, v2
 ; CHECK: clrldi   r3, r3, 48
 ; CHECK-LE-LABEL: @getus3
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: rldicl r3, r3, 16, 48
 }
 
@@ -779,7 +779,7 @@
   %vecext = extractelement <8 x i16> %vus, i32 4
   ret i16 %vecext
 ; CHECK-LABEL: @getus4
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 16, 48
 ; CHECK-LE-LABEL: @getus4
 ; CHECK-LE: mfvsrd r3, v2
@@ -792,7 +792,7 @@
   %vecext = extractelement <8 x i16> %vus, i32 5
   ret i16 %vecext
 ; CHECK-LABEL: @getus5
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 32, 48
 ; CHECK-LE-LABEL: @getus5
 ; CHECK-LE: mfvsrd r3, v2
@@ -805,7 +805,7 @@
   %vecext = extractelement <8 x i16> %vus, i32 6
   ret i16 %vecext
 ; CHECK-LABEL: @getus6
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: rldicl r3, r3, 48, 48
 ; CHECK-LE-LABEL: @getus6
 ; CHECK-LE: mfvsrd r3, v2
@@ -818,7 +818,7 @@
   %vecext = extractelement <8 x i16> %vus, i32 7
   ret i16 %vecext
 ; CHECK-LABEL: @getus7
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK: clrldi   r3, r3, 48
 ; CHECK-LE-LABEL: @getus7
 ; CHECK-LE: mfvsrd r3, v2
@@ -892,11 +892,11 @@
   ret i32 %vecext
 ; CHECK-LABEL: @getsi0
 ; CHECK: xxsldwi vs0, v2, v2, 3
-; CHECK: mfvsrwz r3, f0
+; CHECK: mffprwz r3, f0
 ; CHECK: extsw r3, r3
 ; CHECK-LE-LABEL: @getsi0
 ; CHECK-LE: xxswapd vs0, v2
-; CHECK-LE: mfvsrwz r3, f0
+; CHECK-LE: mffprwz r3, f0
 ; CHECK-LE: extsw r3, r3
 }
 
@@ -910,7 +910,7 @@
 ; CHECK: extsw r3, r3
 ; CHECK-LE-LABEL: @getsi1
 ; CHECK-LE: xxsldwi vs0, v2, v2, 1
-; CHECK-LE: mfvsrwz r3, f0
+; CHECK-LE: mffprwz r3, f0
 ; CHECK-LE: extsw r3, r3
 }
 
@@ -921,7 +921,7 @@
   ret i32 %vecext
 ; CHECK-LABEL: @getsi2
 ; CHECK: xxsldwi vs0, v2, v2, 1
-; CHECK: mfvsrwz r3, f0
+; CHECK: mffprwz r3, f0
 ; CHECK: extsw r3, r3
 ; CHECK-LE-LABEL: @getsi2
 ; CHECK-LE: mfvsrwz r3, v2
@@ -935,11 +935,11 @@
   ret i32 %vecext
 ; CHECK-LABEL: @getsi3
 ; CHECK: xxswapd vs0, v2
-; CHECK: mfvsrwz r3, f0
+; CHECK: mffprwz r3, f0
 ; CHECK: extsw r3, r3
 ; CHECK-LE-LABEL: @getsi3
 ; CHECK-LE: xxsldwi vs0, v2, v2, 3
-; CHECK-LE: mfvsrwz r3, f0
+; CHECK-LE: mffprwz r3, f0
 ; CHECK-LE: extsw r3, r3
 }
 
@@ -950,10 +950,10 @@
   ret i32 %vecext
 ; CHECK-LABEL: @getui0
 ; CHECK: xxsldwi vs0, v2, v2, 3
-; CHECK: mfvsrwz r3, f0
+; CHECK: mffprwz r3, f0
 ; CHECK-LE-LABEL: @getui0
 ; CHECK-LE: xxswapd vs0, v2
-; CHECK-LE: mfvsrwz r3, f0
+; CHECK-LE: mffprwz r3, f0
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -965,7 +965,7 @@
 ; CHECK: mfvsrwz r3, v2
 ; CHECK-LE-LABEL: @getui1
 ; CHECK-LE: xxsldwi vs0, v2, v2, 1
-; CHECK-LE: mfvsrwz r3, f0
+; CHECK-LE: mffprwz r3, f0
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -975,7 +975,7 @@
   ret i32 %vecext
 ; CHECK-LABEL: @getui2
 ; CHECK: xxsldwi vs0, v2, v2, 1
-; CHECK: mfvsrwz r3, f0
+; CHECK: mffprwz r3, f0
 ; CHECK-LE-LABEL: @getui2
 ; CHECK-LE: mfvsrwz r3, v2
 }
@@ -987,10 +987,10 @@
   ret i32 %vecext
 ; CHECK-LABEL: @getui3
 ; CHECK: xxswapd vs0, v2
-; CHECK: mfvsrwz r3, f0
+; CHECK: mffprwz r3, f0
 ; CHECK-LE-LABEL: @getui3
 ; CHECK-LE: xxsldwi vs0, v2, v2, 3
-; CHECK-LE: mfvsrwz r3, f0
+; CHECK-LE: mffprwz r3, f0
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -1022,7 +1022,7 @@
 ; CHECK: mfvsrd r3, v2
 ; CHECK-LE-LABEL: @getsl0
 ; CHECK-LE: xxswapd vs0, v2
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -1032,7 +1032,7 @@
   ret i64 %vecext
 ; CHECK-LABEL: @getsl1
 ; CHECK: xxswapd vs0, v2
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK-LE-LABEL: @getsl1
 ; CHECK-LE: mfvsrd r3, v2
 }
@@ -1046,7 +1046,7 @@
 ; CHECK: mfvsrd r3, v2
 ; CHECK-LE-LABEL: @getul0
 ; CHECK-LE: xxswapd  vs0, v2
-; CHECK-LE: mfvsrd r3, f0
+; CHECK-LE: mffprd r3, f0
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -1056,7 +1056,7 @@
   ret i64 %vecext
 ; CHECK-LABEL: @getul1
 ; CHECK: xxswapd vs0, v2
-; CHECK: mfvsrd r3, f0
+; CHECK: mffprd r3, f0
 ; CHECK-LE-LABEL: @getul1
 ; CHECK-LE: mfvsrd r3, v2
 }
diff --git a/llvm/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll b/llvm/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
--- a/llvm/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
+++ b/llvm/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
@@ -561,10 +561,10 @@
 define <4 x i32> @_Z10testInsEltILj0EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
 entry:
 ; CHECK-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_
-; CHECK: mtvsrwz 0, 5
+; CHECK: mtfprwz 0, 5
 ; CHECK: xxinsertw 34, 0, 12
 ; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_
-; CHECK-BE: mtvsrwz 0, 5
+; CHECK-BE: mtfprwz 0, 5
 ; CHECK-BE: xxinsertw 34, 0, 0
   %vecins = insertelement <4 x i32> %a, i32 %b, i32 0
   ret <4 x i32> %vecins
@@ -573,10 +573,10 @@
 define <4 x i32> @_Z10testInsEltILj1EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
 entry:
 ; CHECK-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_
-; CHECK: mtvsrwz 0, 5
+; CHECK: mtfprwz 0, 5
 ; CHECK: xxinsertw 34, 0, 8
 ; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_
-; CHECK-BE: mtvsrwz 0, 5
+; CHECK-BE: mtfprwz 0, 5
 ; CHECK-BE: xxinsertw 34, 0, 4
   %vecins = insertelement <4 x i32> %a, i32 %b, i32 1
   ret <4 x i32> %vecins
@@ -585,10 +585,10 @@
 define <4 x i32> @_Z10testInsEltILj2EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
 entry:
 ; CHECK-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_
-; CHECK: mtvsrwz 0, 5
+; CHECK: mtfprwz 0, 5
 ; CHECK: xxinsertw 34, 0, 4
 ; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_
-; CHECK-BE: mtvsrwz 0, 5
+; CHECK-BE: mtfprwz 0, 5
 ; CHECK-BE: xxinsertw 34, 0, 8
   %vecins = insertelement <4 x i32> %a, i32 %b, i32 2
   ret <4 x i32> %vecins
@@ -597,10 +597,10 @@
 define <4 x i32> @_Z10testInsEltILj3EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
 entry:
 ; CHECK-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_
-; CHECK: mtvsrwz 0, 5
+; CHECK: mtfprwz 0, 5
 ; CHECK: xxinsertw 34, 0, 0
 ; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_
-; CHECK-BE: mtvsrwz 0, 5
+; CHECK-BE: mtfprwz 0, 5
 ; CHECK-BE: xxinsertw 34, 0, 12
   %vecins = insertelement <4 x i32> %a, i32 %b, i32 3
   ret <4 x i32> %vecins
diff --git a/llvm/test/CodeGen/PowerPC/popcnt-zext.ll b/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
--- a/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
+++ b/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
@@ -12,7 +12,7 @@
 ; SLOW-LABEL: zpop_i8_i16:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 24
-; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
+; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    subf 3, 3, 5
@@ -48,7 +48,7 @@
 ; SLOW-LABEL: popz_i8_i16:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 24
-; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
+; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    subf 3, 3, 5
@@ -77,14 +77,14 @@
 define i32 @zpop_i8_i32(i8 %x) {
 ; FAST-LABEL: zpop_i8_i32:
 ; FAST:       # %bb.0:
-; FAST-NEXT:    rlwinm 3, 3, 0, 24, 31
+; FAST-NEXT:    clrlwi 3, 3, 24
 ; FAST-NEXT:    popcntw 3, 3
 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: zpop_i8_i32:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 24
-; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
+; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    subf 3, 3, 5
@@ -120,7 +120,7 @@
 ; SLOW-LABEL: popz_i8_32:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 24
-; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
+; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    subf 3, 3, 5
@@ -149,14 +149,14 @@
 define i32 @zpop_i16_i32(i16 %x) {
 ; FAST-LABEL: zpop_i16_i32:
 ; FAST:       # %bb.0:
-; FAST-NEXT:    rlwinm 3, 3, 0, 16, 31
+; FAST-NEXT:    clrlwi 3, 3, 16
 ; FAST-NEXT:    popcntw 3, 3
 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: zpop_i16_i32:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 16
-; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
+; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
 ; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    subf 3, 3, 5
@@ -192,7 +192,7 @@
 ; SLOW-LABEL: popz_i16_32:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 16
-; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
+; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
 ; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    subf 3, 3, 5
@@ -305,7 +305,7 @@
 ; SLOW-LABEL: popa_i16_i64:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 16
-; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
+; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
 ; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    subf 3, 3, 5
diff --git a/llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll b/llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll
--- a/llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll
@@ -14,7 +14,7 @@
 
 ; CHECK-LABEL: @crbitsoff
 ; CHECK-NO-ISEL-LABEL: @crbitsoff
-; CHECK-DAG: cmplwi {{[0-9]+}}, 3, 0
+; CHECK-DAG: cmplwi 3, 0
 ; CHECK-DAG: li [[REG2:[0-9]+]], 1
 ; CHECK-DAG: cntlzw [[REG3:[0-9]+]],
 ; CHECK: isel [[REG4:[0-9]+]], 0, [[REG2]]
diff --git a/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll b/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
--- a/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
@@ -14,7 +14,7 @@
 ;
 ; Compare the arguments and return
 ; No prologue needed.
-; ENABLE: cmpw 0, 3, 4
+; ENABLE: cmpw 3, 4
 ; ENABLE-NEXT: bgelr 0
 ;
 ; Prologue code.
@@ -24,7 +24,7 @@
 ;
 ; Compare the arguments and jump to exit.
 ; After the prologue is set.
-; DISABLE: cmpw 0, 3, 4
+; DISABLE: cmpw 3, 4
 ; DISABLE-NEXT: bge 0, .[[EXIT_LABEL:LBB[0-9_]+]]
 ;
 ; Store %a on the stack
@@ -75,14 +75,14 @@
 ; CHECK-LABEL: freqSaveAndRestoreOutsideLoop:
 ;
 ; Shrink-wrapping allows to skip the prologue in the else case.
-; ENABLE: cmplwi 0, 3, 0
+; ENABLE: cmplwi 3, 0
 ; ENABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
 ;
 ; Prologue code.
 ; Make sure we save the link register
 ; CHECK: mflr {{[0-9]+}}
 ;
-; DISABLE: cmplwi 0, 3, 0
+; DISABLE: cmplwi 3, 0
 ; DISABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
 ;
 ; Loop preheader
@@ -202,7 +202,7 @@
 ; restore outside.
 ; CHECK-LABEL: loopInfoSaveOutsideLoop:
 ;
-; ENABLE: cmplwi 0, 3, 0
+; ENABLE: cmplwi 3, 0
 ; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
 ;
 ; Prologue code.
@@ -211,7 +211,7 @@
 ;
 ; DISABLE: std
 ; DISABLE-NEXT: std
-; DISABLE: cmplwi 0, 3, 0
+; DISABLE: cmplwi 3, 0
 ; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
 ;
 ; Loop preheader
@@ -284,7 +284,7 @@
 ; save outside.
 ; CHECK-LABEL: loopInfoRestoreOutsideLoop:
 ;
-; ENABLE: cmplwi 0, 3, 0
+; ENABLE: cmplwi 3, 0
 ; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
 ;
 ; Prologue code.
@@ -293,7 +293,7 @@
 ;
 ; DISABLE: std
 ; DISABLE-NEXT: std
-; DISABLE: cmplwi 0, 3, 0
+; DISABLE: cmplwi 3, 0
 ; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
 ;
 ; CHECK: bl somethingElse
@@ -373,7 +373,7 @@
 ; Check that we handle inline asm correctly.
 ; CHECK-LABEL: inlineAsm:
 ;
-; ENABLE: cmplwi 0, 3, 0
+; ENABLE: cmplwi 3, 0
 ; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
 ;
 ; Prologue code.
@@ -381,7 +381,7 @@
 ; ENABLE-DAG: li [[IV:[0-9]+]], 10
 ; ENABLE-DAG: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
 ;
-; DISABLE: cmplwi 0, 3, 0
+; DISABLE: cmplwi 3, 0
 ; DISABLE-NEXT: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
 ; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
 ; DISABLE: li [[IV:[0-9]+]], 10
@@ -438,13 +438,13 @@
 ; Check that we handle calls to variadic functions correctly.
 ; CHECK-LABEL: callVariadicFunc:
 ;
-; ENABLE: cmplwi 0, 3, 0
+; ENABLE: cmplwi 3, 0
 ; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
 ;
 ; Prologue code.
 ; CHECK: mflr {{[0-9]+}}
 ; 
-; DISABLE: cmplwi 0, 3, 0
+; DISABLE: cmplwi 3, 0
 ; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
 ;
 ; Setup of the varags.
@@ -497,7 +497,7 @@
 ; CHECK-LABEL: noreturn:
 ; DISABLE: mflr {{[0-9]+}}
 ;
-; CHECK: cmplwi 0, 3, 0
+; CHECK: cmplwi 3, 0
 ; CHECK-NEXT: bne{{[-]?}} 0, .[[ABORT:LBB[0-9_]+]]
 ;
 ; CHECK: li 3, 42
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll b/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
--- a/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
@@ -123,7 +123,7 @@
 ; CHECK-NOT: li
 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
 ; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
 ; CHECK-NOT: adde
 ; CHECK-NOT: xori
 ; CHECK-NOT: isel
@@ -133,7 +133,7 @@
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8: isel
@@ -153,7 +153,7 @@
 ; CHECK-NOT: li
 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
 ; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
 ; CHECK-NOT: adde
 ; CHECK-NOT: xori
 ; CHECK-NOT: isel
@@ -163,7 +163,7 @@
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8: isel
@@ -183,7 +183,7 @@
 ; CHECK-NOT: li
 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
 ; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
 ; CHECK-NOT: adde
 ; CHECK-NOT: xori
 ; CHECK-NOT: isel
@@ -193,7 +193,7 @@
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8: isel
@@ -213,7 +213,7 @@
 ; CHECK-NOT: li
 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
 ; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
 ; CHECK-NOT: adde
 ; CHECK-NOT: xori
 ; CHECK-NOT: isel
@@ -223,7 +223,7 @@
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8: isel
@@ -347,7 +347,7 @@
 ; CHECK-NOT: li
 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
 ; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
 ; CHECK-NOT: adde
 ; CHECK-NOT: xori
 ; CHECK-NOT: neg
@@ -358,7 +358,7 @@
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8-DAG: neg
@@ -379,7 +379,7 @@
 ; CHECK-NOT: li
 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
 ; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
 ; CHECK-NOT: adde
 ; CHECK-NOT: xori
 ; CHECK-NOT: neg
@@ -390,7 +390,7 @@
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8-DAG: neg
@@ -411,7 +411,7 @@
 ; CHECK-NOT: li
 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
 ; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
 ; CHECK-NOT: adde
 ; CHECK-NOT: xori
 ; CHECK-NOT: neg
@@ -422,7 +422,7 @@
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8-DAG: neg
@@ -443,7 +443,7 @@
 ; CHECK-NOT: li
 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
 ; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
 ; CHECK-NOT: adde
 ; CHECK-NOT: xori
 ; CHECK-NOT: neg
@@ -454,7 +454,7 @@
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8-DAG: neg
@@ -769,14 +769,14 @@
 ; CHECK-NOT: li
 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
 ; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
 ; CHECK-NOT: adde
 ; CHECK-NOT: xori
 ; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb29
 ; CHECK-PWR8-DAG: cmpd
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
@@ -1013,13 +1013,13 @@
 ; CHECK-NOT: li
 ; CHECK: cmpld {{c?r?(0, )?}}r3, r4
 ; CHECK-NEXT: setb r3, cr0
-; CHECK-NOT: subfc
+; CHECK-NOT: subc
 ; CHECK-NOT: subfe
 ; CHECK-NOT: neg
 ; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbud1
-; CHECK-PWR8-DAG: subfc
+; CHECK-PWR8-DAG: subc
 ; CHECK-PWR8-DAG: subfe
 ; CHECK-PWR8-DAG: cmpld
 ; CHECK-PWR8-DAG: neg
@@ -1138,8 +1138,8 @@
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
 ; CHECK-LABEL: setbuh:
-; CHECK-DAG: rlwinm [[RA:r[0-9]+]], r3, 0, 16, 31
-; CHECK-DAG: rlwinm [[RB:r[0-9]+]], r4, 0, 16, 31
+; CHECK-DAG: clrlwi [[RA:r[0-9]+]], r3, 16
+; CHECK-DAG: clrlwi [[RB:r[0-9]+]], r4, 16
 ; CHECK-NOT: li
 ; CHECK-NOT: xor
 ; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]]
@@ -1151,8 +1151,8 @@
 ; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbuh
-; CHECK-PWR8: rlwinm
-; CHECK-PWR8: rlwinm
+; CHECK-PWR8: clrlwi
+; CHECK-PWR8: clrlwi
 ; CHECK-PWR8-DAG: cmplw
 ; CHECK-PWR8-DAG: cntlzw
 ; CHECK-PWR8: srwi
@@ -1170,8 +1170,8 @@
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
 ; CHECK-LABEL: setbuc:
-; CHECK-DAG: rlwinm [[RA:r[0-9]+]], r3, 0, 24, 31
-; CHECK-DAG: rlwinm [[RB:r[0-9]+]], r4, 0, 24, 31
+; CHECK-DAG: clrlwi [[RA:r[0-9]+]], r3, 24
+; CHECK-DAG: clrlwi [[RB:r[0-9]+]], r4, 24
 ; CHECK-NOT: li
 ; CHECK-NOT: clrldi
 ; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]]
@@ -1181,8 +1181,8 @@
 ; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbuc
-; CHECK-PWR8: rlwinm
-; CHECK-PWR8: rlwinm
+; CHECK-PWR8: clrlwi
+; CHECK-PWR8: clrlwi
 ; CHECK-PWR8-DAG: clrldi
 ; CHECK-PWR8-DAG: clrldi
 ; CHECK-PWR8-DAG: cmplw
diff --git a/llvm/test/CodeGen/PowerPC/pr25080.ll b/llvm/test/CodeGen/PowerPC/pr25080.ll
--- a/llvm/test/CodeGen/PowerPC/pr25080.ll
+++ b/llvm/test/CodeGen/PowerPC/pr25080.ll
@@ -18,30 +18,30 @@
 ; LE-NEXT:    xxsldwi 1, 34, 34, 1
 ; LE-NEXT:    mfvsrwz 4, 35
 ; LE-NEXT:    xxsldwi 4, 34, 34, 3
-; LE-NEXT:    mtvsrd 2, 3
-; LE-NEXT:    mfvsrwz 3, 0
+; LE-NEXT:    mtfprd 2, 3
+; LE-NEXT:    mffprwz 3, 0
 ; LE-NEXT:    xxswapd 0, 35
-; LE-NEXT:    mtvsrd 3, 4
+; LE-NEXT:    mtfprd 3, 4
 ; LE-NEXT:    xxsldwi 5, 35, 35, 1
-; LE-NEXT:    mfvsrwz 4, 1
+; LE-NEXT:    mffprwz 4, 1
 ; LE-NEXT:    xxsldwi 7, 35, 35, 3
-; LE-NEXT:    mtvsrd 1, 3
+; LE-NEXT:    mtfprd 1, 3
 ; LE-NEXT:    xxswapd 33, 3
-; LE-NEXT:    mfvsrwz 3, 4
-; LE-NEXT:    mtvsrd 4, 4
+; LE-NEXT:    mffprwz 3, 4
+; LE-NEXT:    mtfprd 4, 4
 ; LE-NEXT:    xxswapd 34, 1
-; LE-NEXT:    mfvsrwz 4, 0
-; LE-NEXT:    mtvsrd 0, 3
+; LE-NEXT:    mffprwz 4, 0
+; LE-NEXT:    mtfprd 0, 3
 ; LE-NEXT:    xxswapd 35, 4
-; LE-NEXT:    mfvsrwz 3, 5
-; LE-NEXT:    mtvsrd 6, 4
+; LE-NEXT:    mffprwz 3, 5
+; LE-NEXT:    mtfprd 6, 4
 ; LE-NEXT:    xxswapd 36, 0
-; LE-NEXT:    mtvsrd 1, 3
-; LE-NEXT:    mfvsrwz 3, 7
+; LE-NEXT:    mtfprd 1, 3
+; LE-NEXT:    mffprwz 3, 7
 ; LE-NEXT:    xxswapd 37, 6
 ; LE-NEXT:    vmrglh 2, 3, 2
 ; LE-NEXT:    xxswapd 35, 2
-; LE-NEXT:    mtvsrd 2, 3
+; LE-NEXT:    mtfprd 2, 3
 ; LE-NEXT:    xxswapd 32, 1
 ; LE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
 ; LE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
@@ -73,29 +73,29 @@
 ; BE-NEXT:    mfvsrwz 3, 35
 ; BE-NEXT:    xxsldwi 1, 35, 35, 1
 ; BE-NEXT:    sldi 3, 3, 48
-; BE-NEXT:    mfvsrwz 4, 0
+; BE-NEXT:    mffprwz 4, 0
 ; BE-NEXT:    xxsldwi 0, 35, 35, 3
 ; BE-NEXT:    mtvsrd 36, 3
-; BE-NEXT:    mfvsrwz 3, 1
+; BE-NEXT:    mffprwz 3, 1
 ; BE-NEXT:    sldi 4, 4, 48
 ; BE-NEXT:    xxswapd 1, 34
 ; BE-NEXT:    mtvsrd 35, 4
 ; BE-NEXT:    mfvsrwz 4, 34
 ; BE-NEXT:    sldi 3, 3, 48
 ; BE-NEXT:    mtvsrd 37, 3
-; BE-NEXT:    mfvsrwz 3, 0
+; BE-NEXT:    mffprwz 3, 0
 ; BE-NEXT:    sldi 4, 4, 48
 ; BE-NEXT:    xxsldwi 0, 34, 34, 1
 ; BE-NEXT:    vmrghh 3, 5, 3
 ; BE-NEXT:    mtvsrd 37, 4
 ; BE-NEXT:    sldi 3, 3, 48
-; BE-NEXT:    mfvsrwz 4, 1
+; BE-NEXT:    mffprwz 4, 1
 ; BE-NEXT:    xxsldwi 1, 34, 34, 3
 ; BE-NEXT:    mtvsrd 34, 3
-; BE-NEXT:    mfvsrwz 3, 0
+; BE-NEXT:    mffprwz 3, 0
 ; BE-NEXT:    sldi 4, 4, 48
 ; BE-NEXT:    mtvsrd 32, 4
-; BE-NEXT:    mfvsrwz 4, 1
+; BE-NEXT:    mffprwz 4, 1
 ; BE-NEXT:    sldi 3, 3, 48
 ; BE-NEXT:    mtvsrd 33, 3
 ; BE-NEXT:    sldi 3, 4, 48
diff --git a/llvm/test/CodeGen/PowerPC/pr33093.ll b/llvm/test/CodeGen/PowerPC/pr33093.ll
--- a/llvm/test/CodeGen/PowerPC/pr33093.ll
+++ b/llvm/test/CodeGen/PowerPC/pr33093.ll
@@ -115,8 +115,8 @@
 ; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    or 3, 3, 5
 ; CHECK-NEXT:    rldicl 4, 3, 32, 32
-; CHECK-NEXT:    rlwinm 5, 3, 24, 0, 31
-; CHECK-NEXT:    rlwinm 6, 4, 24, 0, 31
+; CHECK-NEXT:    rotlwi 5, 3, 24
+; CHECK-NEXT:    rotlwi 6, 4, 24
 ; CHECK-NEXT:    rlwimi 5, 3, 8, 8, 15
 ; CHECK-NEXT:    rlwimi 5, 3, 8, 24, 31
 ; CHECK-NEXT:    rlwimi 6, 4, 8, 8, 15
diff --git a/llvm/test/CodeGen/PowerPC/pr35688.ll b/llvm/test/CodeGen/PowerPC/pr35688.ll
--- a/llvm/test/CodeGen/PowerPC/pr35688.ll
+++ b/llvm/test/CodeGen/PowerPC/pr35688.ll
@@ -13,7 +13,7 @@
 ; CHECK:    subfze 6, 4
 ; CHECK:    sradi 7, 6, 63
 ; CHECK:    srad 6, 6, 3
-; CHECK:    subfc 5, 5, 7
+; CHECK:    subc 5, 7, 5
 ; CHECK:    subfe 5, 4, 6
 ; CHECK:    sradi 5, 5, 63
 
@@ -25,7 +25,7 @@
 ; MSSA:     subfic 5, 3, 0
 ; MSSA:     subfze 5, 4
 ; MSSA:     sradi 5, 5, 63
-; MSSA:     subfc 3, 3, 5
+; MSSA:     subc 3, 5, 3
 ; MSSA:     subfe 3, 4, 5
 ; MSSA:     sradi 3, 3, 63
 ; MSSA:     std 3, 0(3)
diff --git a/llvm/test/CodeGen/PowerPC/pr38087.ll b/llvm/test/CodeGen/PowerPC/pr38087.ll
--- a/llvm/test/CodeGen/PowerPC/pr38087.ll
+++ b/llvm/test/CodeGen/PowerPC/pr38087.ll
@@ -12,7 +12,7 @@
 ; CHECK-LABEL: draw_llvm_vs_variant0:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfd f0, 0(r3)
-; CHECK-NEXT:    xxpermdi v3, f0, f0, 2
+; CHECK-NEXT:    xxswapd v3, f0
 ; CHECK-NEXT:    vmrglh v3, v3, v3
 ; CHECK-NEXT:    vextsh2w v3, v3
 ; CHECK-NEXT:    xvcvsxwsp vs0, v3
diff --git a/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll b/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
--- a/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
+++ b/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
@@ -18,7 +18,7 @@
 ; CHECK-NEXT:    addis r5, r2, .LCPI0_1@toc@ha
 ; CHECK-NEXT:    addi r5, r5, .LCPI0_1@toc@l
 ; CHECK-NEXT:    lxvx v4, 0, r5
-; CHECK-NEXT:    xxpermdi v5, f0, f0, 2
+; CHECK-NEXT:    xxswapd v5, f0
 ; CHECK-NEXT:    xxlxor v3, v3, v3
 ; CHECK-NEXT:    li r5, 4
 ; CHECK-NEXT:    vperm v0, v3, v5, v2
@@ -32,7 +32,7 @@
 ; CHECK-NEXT:  .LBB0_1: # %for.cond1.preheader
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lfd f0, 0(r3)
-; CHECK-NEXT:    xxpermdi v1, f0, f0, 2
+; CHECK-NEXT:    xxswapd v1, f0
 ; CHECK-NEXT:    lfdx f0, r3, r4
 ; CHECK-NEXT:    vperm v6, v1, v3, v4
 ; CHECK-NEXT:    vperm v1, v3, v1, v2
@@ -46,7 +46,7 @@
 ; CHECK-NEXT:    vadduwm v1, v1, v6
 ; CHECK-NEXT:    xxspltw v6, v1, 2
 ; CHECK-NEXT:    vadduwm v1, v1, v6
-; CHECK-NEXT:    xxpermdi v6, f0, f0, 2
+; CHECK-NEXT:    xxswapd v6, f0
 ; CHECK-NEXT:    vextuwrx r3, r5, v1
 ; CHECK-NEXT:    vperm v7, v6, v3, v4
 ; CHECK-NEXT:    vperm v6, v3, v6, v2
@@ -186,12 +186,12 @@
 ; CHECK-NEXT:    addi r3, r3, .LCPI1_0@toc@l
 ; CHECK-NEXT:    lxvx v4, 0, r3
 ; CHECK-NEXT:    addis r3, r2, .LCPI1_1@toc@ha
-; CHECK-NEXT:    xxpermdi v2, f0, f0, 2
+; CHECK-NEXT:    xxswapd v2, f0
 ; CHECK-NEXT:    lfd f0, 0(r4)
 ; CHECK-NEXT:    addi r3, r3, .LCPI1_1@toc@l
 ; CHECK-NEXT:    xxlxor v3, v3, v3
 ; CHECK-NEXT:    lxvx v0, 0, r3
-; CHECK-NEXT:    xxpermdi v1, f0, f0, 2
+; CHECK-NEXT:    xxswapd v1, f0
 ; CHECK-NEXT:    vperm v5, v2, v3, v4
 ; CHECK-NEXT:    vperm v2, v3, v2, v0
 ; CHECK-NEXT:    vperm v0, v3, v1, v0
@@ -291,11 +291,11 @@
 ; CHECK-NEXT:    addi r3, r3, .LCPI2_0@toc@l
 ; CHECK-NEXT:    lxvx v4, 0, r3
 ; CHECK-NEXT:    li r3, 4
-; CHECK-NEXT:    xxpermdi v2, f0, f0, 2
+; CHECK-NEXT:    xxswapd v2, f0
 ; CHECK-NEXT:    lfiwzx f0, r5, r3
 ; CHECK-NEXT:    xxlxor v3, v3, v3
 ; CHECK-NEXT:    vperm v2, v2, v3, v4
-; CHECK-NEXT:    xxpermdi v5, f0, f0, 2
+; CHECK-NEXT:    xxswapd v5, f0
 ; CHECK-NEXT:    vperm v3, v5, v3, v4
 ; CHECK-NEXT:    vspltisw v4, 8
 ; CHECK-NEXT:    vnegw v3, v3
@@ -361,7 +361,7 @@
 ; CHECK-NEXT:    lxsihzx v2, r6, r7
 ; CHECK-NEXT:    lxsihzx v4, r3, r4
 ; CHECK-NEXT:    li r6, 0
-; CHECK-NEXT:    mtvsrd f0, r6
+; CHECK-NEXT:    mtfprd f0, r6
 ; CHECK-NEXT:    vsplth v4, v4, 3
 ; CHECK-NEXT:    xxswapd v3, vs0
 ; CHECK-NEXT:    vsplth v2, v2, 3
@@ -377,7 +377,7 @@
 ; CHECK-NEXT:    xxspltw v3, v2, 2
 ; CHECK-NEXT:    vadduwm v2, v2, v3
 ; CHECK-NEXT:    vextuwrx r3, r3, v2
-; CHECK-NEXT:    cmpw cr0, r3, r5
+; CHECK-NEXT:    cmpw r3, r5
 ; CHECK-NEXT:    bgelr+ cr0
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ;
@@ -405,7 +405,7 @@
 ; P9BE-NEXT:    xxspltw v3, v2, 1
 ; P9BE-NEXT:    vadduwm v2, v2, v3
 ; P9BE-NEXT:    vextuwlx r3, r3, v2
-; P9BE-NEXT:    cmpw cr0, r3, r5
+; P9BE-NEXT:    cmpw r3, r5
 ; P9BE-NEXT:    bgelr+ cr0
 ; P9BE-NEXT:  # %bb.1: # %if.then
 entry:
@@ -446,7 +446,7 @@
 ; CHECK-NEXT:    add r6, r3, r4
 ; CHECK-NEXT:    lxsibzx v2, r3, r4
 ; CHECK-NEXT:    li r3, 0
-; CHECK-NEXT:    mtvsrd f0, r3
+; CHECK-NEXT:    mtfprd f0, r3
 ; CHECK-NEXT:    li r3, 8
 ; CHECK-NEXT:    lxsibzx v5, r6, r3
 ; CHECK-NEXT:    xxswapd v3, vs0
@@ -467,7 +467,7 @@
 ; CHECK-NEXT:    xxspltw v3, v2, 2
 ; CHECK-NEXT:    vadduwm v2, v2, v3
 ; CHECK-NEXT:    vextuwrx r3, r3, v2
-; CHECK-NEXT:    cmpw cr0, r3, r5
+; CHECK-NEXT:    cmpw r3, r5
 ; CHECK-NEXT:    bgelr+ cr0
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ;
@@ -496,7 +496,7 @@
 ; P9BE-NEXT:    xxspltw v3, v2, 1
 ; P9BE-NEXT:    vadduwm v2, v2, v3
 ; P9BE-NEXT:    vextuwlx r3, r3, v2
-; P9BE-NEXT:    cmpw cr0, r3, r5
+; P9BE-NEXT:    cmpw r3, r5
 ; P9BE-NEXT:    bgelr+ cr0
 ; P9BE-NEXT:  # %bb.1: # %if.then
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/qpx-load-splat.ll b/llvm/test/CodeGen/PowerPC/qpx-load-splat.ll
--- a/llvm/test/CodeGen/PowerPC/qpx-load-splat.ll
+++ b/llvm/test/CodeGen/PowerPC/qpx-load-splat.ll
@@ -53,7 +53,7 @@
 ; CHECK-LABEL: foof:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfiwzx f0, 0, r3
-; CHECK-NEXT:    xxpermdi vs0, f0, f0, 2
+; CHECK-NEXT:    xxswapd vs0, f0
 ; CHECK-NEXT:    xxspltw v2, vs0, 3
 ; CHECK-NEXT:    blr
 entry:
@@ -68,7 +68,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sldi r4, r4, 2
 ; CHECK-NEXT:    lfiwzx f0, r3, r4
-; CHECK-NEXT:    xxpermdi vs0, f0, f0, 2
+; CHECK-NEXT:    xxswapd vs0, f0
 ; CHECK-NEXT:    xxspltw v2, vs0, 3
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/qpx-s-sel.ll b/llvm/test/CodeGen/PowerPC/qpx-s-sel.ll
--- a/llvm/test/CodeGen/PowerPC/qpx-s-sel.ll
+++ b/llvm/test/CodeGen/PowerPC/qpx-s-sel.ll
@@ -56,7 +56,7 @@
 ; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]],
 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]]
-; CHECK: qvflogical 1, 1, [[REG4]], 1
+; CHECK: qvfand 1, 1, [[REG4]]
 ; CHECK: blr
 }
 
diff --git a/llvm/test/CodeGen/PowerPC/qpx-sel.ll b/llvm/test/CodeGen/PowerPC/qpx-sel.ll
--- a/llvm/test/CodeGen/PowerPC/qpx-sel.ll
+++ b/llvm/test/CodeGen/PowerPC/qpx-sel.ll
@@ -60,7 +60,7 @@
 ; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]],
 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]]
-; CHECK: qvflogical 1, 1, [[REG4]], 1
+; CHECK: qvfand 1, 1, [[REG4]]
 ; CHECK: blr
 }
 
diff --git a/llvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll b/llvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll
--- a/llvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll
+++ b/llvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll
@@ -29,7 +29,7 @@
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    blr
 ; CHECK-P9-NEXT:  .LBB0_4: # %lor.lhs.false
-; CHECK-P9-NEXT:    cmplwi cr0, r4, 0
+; CHECK-P9-NEXT:    cmplwi r4, 0
 ; CHECK-P9-NEXT:    bne cr0, .LBB0_2
 ; CHECK-P9-NEXT:  .LBB0_5: # %cleanup16
 ; CHECK-P9-NEXT:    mr r3, r5
diff --git a/llvm/test/CodeGen/PowerPC/sat-add.ll b/llvm/test/CodeGen/PowerPC/sat-add.ll
--- a/llvm/test/CodeGen/PowerPC/sat-add.ll
+++ b/llvm/test/CodeGen/PowerPC/sat-add.ll
@@ -24,7 +24,7 @@
 define i8 @unsigned_sat_constant_i8_using_cmp_sum(i8 %x) {
 ; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_sum:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 3, 3, 0, 24, 31
+; CHECK-NEXT:    clrlwi 3, 3, 24
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    andi. 4, 3, 256
 ; CHECK-NEXT:    li 4, -1
@@ -69,7 +69,7 @@
 define i16 @unsigned_sat_constant_i16_using_cmp_sum(i16 %x) {
 ; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_sum:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 3, 3, 0, 16, 31
+; CHECK-NEXT:    clrlwi 3, 3, 16
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    andis. 4, 3, 1
 ; CHECK-NEXT:    li 4, -1
@@ -115,7 +115,7 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi 5, 3, 42
 ; CHECK-NEXT:    li 4, -1
-; CHECK-NEXT:    cmplw 0, 5, 3
+; CHECK-NEXT:    cmplw 5, 3
 ; CHECK-NEXT:    isel 3, 4, 5, 0
 ; CHECK-NEXT:    blr
   %a = add i32 %x, 42
@@ -129,7 +129,7 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, -43
 ; CHECK-NEXT:    addi 5, 3, 42
-; CHECK-NEXT:    cmplw 0, 3, 4
+; CHECK-NEXT:    cmplw 3, 4
 ; CHECK-NEXT:    li 3, -1
 ; CHECK-NEXT:    isel 3, 3, 5, 1
 ; CHECK-NEXT:    blr
@@ -202,8 +202,8 @@
 define i8 @unsigned_sat_variable_i8_using_cmp_sum(i8 %x, i8 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_sum:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 4, 4, 0, 24, 31
-; CHECK-NEXT:    rlwinm 3, 3, 0, 24, 31
+; CHECK-NEXT:    clrlwi 4, 4, 24
+; CHECK-NEXT:    clrlwi 3, 3, 24
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    andi. 4, 3, 256
 ; CHECK-NEXT:    li 4, -1
@@ -253,8 +253,8 @@
 define i16 @unsigned_sat_variable_i16_using_cmp_sum(i16 %x, i16 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_sum:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 4, 4, 0, 16, 31
-; CHECK-NEXT:    rlwinm 3, 3, 0, 16, 31
+; CHECK-NEXT:    clrlwi 4, 4, 16
+; CHECK-NEXT:    clrlwi 3, 3, 16
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    andis. 4, 3, 1
 ; CHECK-NEXT:    li 4, -1
@@ -304,7 +304,7 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    add 4, 3, 4
 ; CHECK-NEXT:    li 5, -1
-; CHECK-NEXT:    cmplw 0, 4, 3
+; CHECK-NEXT:    cmplw 4, 3
 ; CHECK-NEXT:    isel 3, 5, 4, 0
 ; CHECK-NEXT:    blr
   %a = add i32 %x, %y
diff --git a/llvm/test/CodeGen/PowerPC/scalar_vector_test_1.ll b/llvm/test/CodeGen/PowerPC/scalar_vector_test_1.ll
--- a/llvm/test/CodeGen/PowerPC/scalar_vector_test_1.ll
+++ b/llvm/test/CodeGen/PowerPC/scalar_vector_test_1.ll
@@ -13,7 +13,7 @@
 ; P9LE-LABEL: s2v_test1:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfd f0, 0(r3)
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
@@ -33,7 +33,7 @@
 ; P9LE-LABEL: s2v_test2:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfd f0, 8(r3)
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
@@ -55,7 +55,7 @@
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r7, 3
 ; P9LE-NEXT:    lfdx f0, r3, r4
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
@@ -78,7 +78,7 @@
 ; P9LE-LABEL: s2v_test4:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfd f0, 8(r3)
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
@@ -99,7 +99,7 @@
 ; P9LE-LABEL: s2v_test5:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfd f0, 0(r5)
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
@@ -119,7 +119,7 @@
 ; P9LE-LABEL: s2v_test_f1:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfd f0, 0(r3)
-; P9LE-NEXT:    xxpermdi vs0, f0, f0, 2
+; P9LE-NEXT:    xxswapd vs0, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, vs0, 1
 ; P9LE-NEXT:    blr
 
@@ -152,7 +152,7 @@
 ; P9LE-LABEL: s2v_test_f2:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfd f0, 8(r3)
-; P9LE-NEXT:    xxpermdi vs0, f0, f0, 2
+; P9LE-NEXT:    xxswapd vs0, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, vs0, 1
 ; P9LE-NEXT:    blr
 
@@ -187,7 +187,7 @@
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r7, 3
 ; P9LE-NEXT:    lfdx f0, r3, r4
-; P9LE-NEXT:    xxpermdi vs0, f0, f0, 2
+; P9LE-NEXT:    xxswapd vs0, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, vs0, 1
 ; P9LE-NEXT:    blr
 
@@ -225,7 +225,7 @@
 ; P9LE-LABEL: s2v_test_f4:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfd f0, 8(r3)
-; P9LE-NEXT:    xxpermdi vs0, f0, f0, 2
+; P9LE-NEXT:    xxswapd vs0, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, vs0, 1
 ; P9LE-NEXT:    blr
 
@@ -259,7 +259,7 @@
 ; P9LE-LABEL: s2v_test_f5:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfd f0, 0(r5)
-; P9LE-NEXT:    xxpermdi vs0, f0, f0, 2
+; P9LE-NEXT:    xxswapd vs0, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, vs0, 1
 ; P9LE-NEXT:    blr
 
diff --git a/llvm/test/CodeGen/PowerPC/scalar_vector_test_2.ll b/llvm/test/CodeGen/PowerPC/scalar_vector_test_2.ll
--- a/llvm/test/CodeGen/PowerPC/scalar_vector_test_2.ll
+++ b/llvm/test/CodeGen/PowerPC/scalar_vector_test_2.ll
@@ -13,8 +13,8 @@
 ; P9LE:       # %bb.0:
 ; P9LE-NEXT:    lfiwzx f0, 0, r3
 ; P9LE-NEXT:    lfiwzx f1, 0, r4
-; P9LE-NEXT:    xxpermdi vs0, f0, f0, 2
-; P9LE-NEXT:    xxpermdi vs1, f1, f1, 2
+; P9LE-NEXT:    xxswapd vs0, f0
+; P9LE-NEXT:    xxswapd vs1, f1
 ; P9LE-NEXT:    xvaddsp vs0, vs0, vs1
 ; P9LE-NEXT:    xxsldwi vs0, vs0, vs0, 2
 ; P9LE-NEXT:    stfiwx f0, 0, r5
@@ -35,8 +35,8 @@
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
 ; P8LE-NEXT:    lfiwzx f1, 0, r4
-; P8LE-NEXT:    xxpermdi vs0, f0, f0, 2
-; P8LE-NEXT:    xxpermdi vs1, f1, f1, 2
+; P8LE-NEXT:    xxswapd vs0, f0
+; P8LE-NEXT:    xxswapd vs1, f1
 ; P8LE-NEXT:    xvaddsp vs0, vs0, vs1
 ; P8LE-NEXT:    xxsldwi vs0, vs0, vs0, 2
 ; P8LE-NEXT:    stfiwx f0, 0, r5
@@ -67,8 +67,8 @@
 ; P9LE:       # %bb.0:
 ; P9LE-NEXT:    lfiwzx f0, 0, r3
 ; P9LE-NEXT:    lfiwzx f1, 0, r4
-; P9LE-NEXT:    xxpermdi vs0, f0, f0, 2
-; P9LE-NEXT:    xxpermdi vs1, f1, f1, 2
+; P9LE-NEXT:    xxswapd vs0, f0
+; P9LE-NEXT:    xxswapd vs1, f1
 ; P9LE-NEXT:    xvsubsp vs0, vs0, vs1
 ; P9LE-NEXT:    xxsldwi vs0, vs0, vs0, 2
 ; P9LE-NEXT:    mr r3, r5
@@ -92,8 +92,8 @@
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
 ; P8LE-NEXT:    lfiwzx f1, 0, r4
 ; P8LE-NEXT:    mr r3, r5
-; P8LE-NEXT:    xxpermdi vs0, f0, f0, 2
-; P8LE-NEXT:    xxpermdi vs1, f1, f1, 2
+; P8LE-NEXT:    xxswapd vs0, f0
+; P8LE-NEXT:    xxswapd vs1, f1
 ; P8LE-NEXT:    xvsubsp vs0, vs0, vs1
 ; P8LE-NEXT:    xxsldwi vs0, vs0, vs0, 2
 ; P8LE-NEXT:    stfiwx f0, 0, r5
diff --git a/llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll b/llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll
--- a/llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll
+++ b/llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll
@@ -12,7 +12,7 @@
 ; P9LE-LABEL: s2v_test1:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfiwax f0, 0, r3
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
@@ -25,7 +25,7 @@
 ; P8LE-LABEL: s2v_test1:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwax f0, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P8LE-NEXT:    blr
 
@@ -47,7 +47,7 @@
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    addi r3, r3, 4
 ; P9LE-NEXT:    lfiwax f0, 0, r3
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
@@ -62,7 +62,7 @@
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addi r3, r3, 4
 ; P8LE-NEXT:    lfiwax f0, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P8LE-NEXT:    blr
 
@@ -86,7 +86,7 @@
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r7, 2
 ; P9LE-NEXT:    lfiwax f0, r3, r4
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
@@ -101,7 +101,7 @@
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    sldi r4, r7, 2
 ; P8LE-NEXT:    lfiwax f0, r3, r4
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P8LE-NEXT:    blr
 
@@ -126,7 +126,7 @@
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    addi r3, r3, 4
 ; P9LE-NEXT:    lfiwax f0, 0, r3
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
@@ -141,7 +141,7 @@
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addi r3, r3, 4
 ; P8LE-NEXT:    lfiwax f0, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P8LE-NEXT:    blr
 
@@ -164,7 +164,7 @@
 ; P9LE-LABEL: s2v_test5:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfiwax f0, 0, r5
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P9LE-NEXT:    blr
 
@@ -177,7 +177,7 @@
 ; P8LE-LABEL: s2v_test5:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwax f0, 0, r5
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    xxpermdi v2, v2, v3, 1
 ; P8LE-NEXT:    blr
 
@@ -198,7 +198,7 @@
 ; P9LE-LABEL: s2v_test6:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfiwax f0, 0, r3
-; P9LE-NEXT:    xxpermdi v2, f0, f0, 2
+; P9LE-NEXT:    xxswapd v2, f0
 ; P9LE-NEXT:    xxspltd v2, v2, 1
 ; P9LE-NEXT:    blr
 
@@ -211,7 +211,7 @@
 ; P8LE-LABEL: s2v_test6:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwax f0, 0, r3
-; P8LE-NEXT:    xxpermdi v2, f0, f0, 2
+; P8LE-NEXT:    xxswapd v2, f0
 ; P8LE-NEXT:    xxspltd v2, v2, 1
 ; P8LE-NEXT:    blr
 
@@ -233,7 +233,7 @@
 ; P9LE-LABEL: s2v_test7:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfiwax f0, 0, r3
-; P9LE-NEXT:    xxpermdi v2, f0, f0, 2
+; P9LE-NEXT:    xxswapd v2, f0
 ; P9LE-NEXT:    xxspltd v2, v2, 1
 ; P9LE-NEXT:    blr
 
@@ -246,7 +246,7 @@
 ; P8LE-LABEL: s2v_test7:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwax f0, 0, r3
-; P8LE-NEXT:    xxpermdi v2, f0, f0, 2
+; P8LE-NEXT:    xxswapd v2, f0
 ; P8LE-NEXT:    xxspltd v2, v2, 1
 ; P8LE-NEXT:    blr
 
diff --git a/llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll b/llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
--- a/llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
+++ b/llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
@@ -15,7 +15,7 @@
 ; P8LE-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
 ; P8LE-NEXT:    addi r3, r4, .LCPI0_0@toc@l
 ; P8LE-NEXT:    lvx v4, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    vperm v2, v3, v2, v4
 ; P8LE-NEXT:    blr
 
@@ -41,7 +41,7 @@
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
 ; P8LE-NEXT:    addi r3, r4, .LCPI1_0@toc@l
 ; P8LE-NEXT:    lvx v4, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    vperm v2, v3, v2, v4
 ; P8LE-NEXT:    blr
 
@@ -69,7 +69,7 @@
 ; P8LE-NEXT:    lfiwzx f0, r3, r5
 ; P8LE-NEXT:    addi r3, r4, .LCPI2_0@toc@l
 ; P8LE-NEXT:    lvx v4, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    vperm v2, v3, v2, v4
 ; P8LE-NEXT:    blr
 
@@ -98,7 +98,7 @@
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
 ; P8LE-NEXT:    addi r3, r4, .LCPI3_0@toc@l
 ; P8LE-NEXT:    lvx v4, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    vperm v2, v3, v2, v4
 ; P8LE-NEXT:    blr
 
@@ -125,7 +125,7 @@
 ; P8LE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; P8LE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
 ; P8LE-NEXT:    lvx v4, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    vperm v2, v3, v2, v4
 ; P8LE-NEXT:    blr
 
@@ -150,7 +150,7 @@
 ; P8LE-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
 ; P8LE-NEXT:    addi r3, r4, .LCPI5_0@toc@l
 ; P8LE-NEXT:    lvx v4, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    vperm v2, v3, v2, v4
 ; P8LE-NEXT:    blr
 
@@ -174,7 +174,7 @@
 ; P9LE-NEXT:    addi r3, r3, 4
 ; P9LE-DAG:     xxspltw v2, v2, 2
 ; P9LE-DAG:     lfiwzx f0, 0, r3
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    blr
 
@@ -192,7 +192,7 @@
 ; P8LE-NEXT:    addi r3, r3, 4
 ; P8LE-NEXT:    xxspltw v2, v2, 2
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    vmrglw v2, v2, v3
 ; P8LE-NEXT:    blr
 
@@ -218,7 +218,7 @@
 ; P9LE-NEXT:    sldi r4, r7, 2
 ; P9LE-NEXT:    lfiwzx f0, r3, r4
 ; P9LE-DAG:     xxspltw v2, v2, 2
-; P9LE-DAG:     xxpermdi v3, f0, f0, 2
+; P9LE-DAG:     xxswapd v3, f0
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    blr
 
@@ -236,7 +236,7 @@
 ; P8LE-NEXT:    sldi r4, r7, 2
 ; P8LE-NEXT:    xxspltw v2, v2, 2
 ; P8LE-NEXT:    lfiwzx f0, r3, r4
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    vmrglw v2, v2, v3
 ; P8LE-NEXT:    blr
 
@@ -263,7 +263,7 @@
 ; P9LE-NEXT:    addi r3, r3, 4
 ; P9LE-NEXT:    lfiwzx f0, 0, r3
 ; P9LE-DAG:    xxspltw v2, v2, 2
-; P9LE-DAG:    xxpermdi v3, f0, f0, 2
+; P9LE-DAG:    xxswapd v3, f0
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    blr
 
@@ -281,7 +281,7 @@
 ; P8LE-NEXT:    addi r3, r3, 4
 ; P8LE-NEXT:    xxspltw v2, v2, 2
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    vmrglw v2, v2, v3
 ; P8LE-NEXT:    blr
 
@@ -306,7 +306,7 @@
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfiwzx f0, 0, r5
 ; P9LE-NEXT:    xxspltw v2, v2, 2
-; P9LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P9LE-NEXT:    xxswapd v3, f0
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    blr
 
@@ -322,7 +322,7 @@
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwzx f0, 0, r5
 ; P8LE-NEXT:    xxspltw v2, v2, 2
-; P8LE-NEXT:    xxpermdi v3, f0, f0, 2
+; P8LE-NEXT:    xxswapd v3, f0
 ; P8LE-NEXT:    vmrglw v2, v2, v3
 ; P8LE-NEXT:    blr
 
diff --git a/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll b/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
--- a/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
+++ b/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
@@ -18,7 +18,7 @@
 
 ; CHECK-LABEL: @testi32slt
 ; CHECK-NO-ISEL-LABEL: @testi32slt
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
@@ -40,7 +40,7 @@
   ret i32 %cond
 
 ; CHECK-NO-ISEL-LABEL: @testi32ult
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
@@ -63,7 +63,7 @@
 
 ; CHECK-LABEL: @testi32sle
 ; CHECK-NO-ISEL-LABEL: @testi32sle
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
@@ -86,7 +86,7 @@
 
 ; CHECK-LABEL: @testi32ule
 ; CHECK-NO-ISEL-LABEL: @testi32ule
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
@@ -109,7 +109,7 @@
 
 ; CHECK-LABEL: @testi32eq
 ; CHECK-NO-ISEL-LABEL: @testi32eq
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
@@ -132,7 +132,7 @@
 
 ; CHECK-LABEL: @testi32sge
 ; CHECK-NO-ISEL-LABEL: @testi32sge
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
@@ -155,7 +155,7 @@
 
 ; CHECK-LABEL: @testi32uge
 ; CHECK-NO-ISEL-LABEL: @testi32uge
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
@@ -178,7 +178,7 @@
 
 ; CHECK-LABEL: @testi32sgt
 ; CHECK-NO-ISEL-LABEL: @testi32sgt
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
@@ -201,7 +201,7 @@
 
 ; CHECK-LABEL: @testi32ugt
 ; CHECK-NO-ISEL-LABEL: @testi32ugt
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
@@ -224,7 +224,7 @@
 
 ; CHECK-LABEL: @testi32ne
 ; CHECK-NO-ISEL-LABEL: @testi32ne
-; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
diff --git a/llvm/test/CodeGen/PowerPC/select_const.ll b/llvm/test/CodeGen/PowerPC/select_const.ll
--- a/llvm/test/CodeGen/PowerPC/select_const.ll
+++ b/llvm/test/CodeGen/PowerPC/select_const.ll
@@ -614,7 +614,7 @@
 define i8 @shl_constant_sel_constants(i1 %cond) {
 ; ALL-LABEL: shl_constant_sel_constants:
 ; ALL:       # %bb.0:
-; ALL-NEXT:    rlwinm 3, 3, 0, 31, 31
+; ALL-NEXT:    clrlwi 3, 3, 31
 ; ALL-NEXT:    li 4, 1
 ; ALL-NEXT:    subfic 3, 3, 3
 ; ALL-NEXT:    slw 3, 4, 3
@@ -651,7 +651,7 @@
 define i8 @lshr_constant_sel_constants(i1 %cond) {
 ; ALL-LABEL: lshr_constant_sel_constants:
 ; ALL:       # %bb.0:
-; ALL-NEXT:    rlwinm 3, 3, 0, 31, 31
+; ALL-NEXT:    clrlwi 3, 3, 31
 ; ALL-NEXT:    li 4, 64
 ; ALL-NEXT:    subfic 3, 3, 3
 ; ALL-NEXT:    srw 3, 4, 3
@@ -676,7 +676,7 @@
 define i8 @ashr_constant_sel_constants(i1 %cond) {
 ; ALL-LABEL: ashr_constant_sel_constants:
 ; ALL:       # %bb.0:
-; ALL-NEXT:    rlwinm 3, 3, 0, 31, 31
+; ALL-NEXT:    clrlwi 3, 3, 31
 ; ALL-NEXT:    li 4, -128
 ; ALL-NEXT:    subfic 3, 3, 3
 ; ALL-NEXT:    sraw 3, 4, 3
diff --git a/llvm/test/CodeGen/PowerPC/setcc-logic.ll b/llvm/test/CodeGen/PowerPC/setcc-logic.ll
--- a/llvm/test/CodeGen/PowerPC/setcc-logic.ll
+++ b/llvm/test/CodeGen/PowerPC/setcc-logic.ll
@@ -138,7 +138,7 @@
 ; CHECK-LABEL: all_sign_bits_clear_branch:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or 3, 3, 4
-; CHECK-NEXT:    cmpwi 0, 3, 0
+; CHECK-NEXT:    cmpwi 3, 0
 ; CHECK-NEXT:    blt 0, .LBB9_2
 ; CHECK-NEXT:  # %bb.1: # %bb1
 ; CHECK-NEXT:    li 3, 4
@@ -163,7 +163,7 @@
 ; CHECK-LABEL: all_bits_set_branch:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    and 3, 3, 4
-; CHECK-NEXT:    cmpwi 0, 3, -1
+; CHECK-NEXT:    cmpwi 3, -1
 ; CHECK-NEXT:    bne 0, .LBB10_2
 ; CHECK-NEXT:  # %bb.1: # %bb1
 ; CHECK-NEXT:    li 3, 4
@@ -188,7 +188,7 @@
 ; CHECK-LABEL: all_sign_bits_set_branch:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    and 3, 3, 4
-; CHECK-NEXT:    cmpwi 0, 3, -1
+; CHECK-NEXT:    cmpwi 3, -1
 ; CHECK-NEXT:    bgt 0, .LBB11_2
 ; CHECK-NEXT:  # %bb.1: # %bb1
 ; CHECK-NEXT:    li 3, 4
@@ -238,7 +238,7 @@
 ; CHECK-LABEL: any_sign_bits_set_branch:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or 3, 3, 4
-; CHECK-NEXT:    cmpwi 0, 3, -1
+; CHECK-NEXT:    cmpwi 3, -1
 ; CHECK-NEXT:    bgt 0, .LBB13_2
 ; CHECK-NEXT:  # %bb.1: # %bb1
 ; CHECK-NEXT:    li 3, 4
@@ -263,7 +263,7 @@
 ; CHECK-LABEL: any_bits_clear_branch:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    and 3, 3, 4
-; CHECK-NEXT:    cmpwi 0, 3, -1
+; CHECK-NEXT:    cmpwi 3, -1
 ; CHECK-NEXT:    beq 0, .LBB14_2
 ; CHECK-NEXT:  # %bb.1: # %bb1
 ; CHECK-NEXT:    li 3, 4
@@ -288,7 +288,7 @@
 ; CHECK-LABEL: any_sign_bits_clear_branch:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    and 3, 3, 4
-; CHECK-NEXT:    cmpwi 0, 3, 0
+; CHECK-NEXT:    cmpwi 3, 0
 ; CHECK-NEXT:    blt 0, .LBB15_2
 ; CHECK-NEXT:  # %bb.1: # %bb1
 ; CHECK-NEXT:    li 3, 4
diff --git a/llvm/test/CodeGen/PowerPC/shift_mask.ll b/llvm/test/CodeGen/PowerPC/shift_mask.ll
--- a/llvm/test/CodeGen/PowerPC/shift_mask.ll
+++ b/llvm/test/CodeGen/PowerPC/shift_mask.ll
@@ -5,7 +5,7 @@
 define i8 @test000(i8 %a, i8 %b) {
 ; CHECK-LABEL: test000:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 4, 4, 0, 29, 31
+; CHECK-NEXT:    clrlwi 4, 4, 29
 ; CHECK-NEXT:    slw 3, 3, 4
 ; CHECK-NEXT:    blr
   %rem = and i8 %b, 7
@@ -16,7 +16,7 @@
 define i16 @test001(i16 %a, i16 %b) {
 ; CHECK-LABEL: test001:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 31
+; CHECK-NEXT:    clrlwi 4, 4, 28
 ; CHECK-NEXT:    slw 3, 3, 4
 ; CHECK-NEXT:    blr
   %rem = and i16 %b, 15
@@ -27,7 +27,7 @@
 define i32 @test002(i32 %a, i32 %b) {
 ; CHECK-LABEL: test002:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 4, 4, 0, 27, 31
+; CHECK-NEXT:    clrlwi 4, 4, 27
 ; CHECK-NEXT:    slw 3, 3, 4
 ; CHECK-NEXT:    blr
   %rem = and i32 %b, 31
@@ -38,7 +38,7 @@
 define i64 @test003(i64 %a, i64 %b) {
 ; CHECK-LABEL: test003:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 4, 4, 0, 26, 31
+; CHECK-NEXT:    clrlwi 4, 4, 26
 ; CHECK-NEXT:    sld 3, 3, 4
 ; CHECK-NEXT:    blr
   %rem = and i64 %b, 63
@@ -89,8 +89,8 @@
 define i8 @test100(i8 %a, i8 %b) {
 ; CHECK-LABEL: test100:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 3, 3, 0, 24, 31
-; CHECK-NEXT:    rlwinm 4, 4, 0, 29, 31
+; CHECK-NEXT:    clrlwi 3, 3, 24
+; CHECK-NEXT:    clrlwi 4, 4, 29
 ; CHECK-NEXT:    srw 3, 3, 4
 ; CHECK-NEXT:    blr
   %rem = and i8 %b, 7
@@ -101,8 +101,8 @@
 define i16 @test101(i16 %a, i16 %b) {
 ; CHECK-LABEL: test101:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 3, 3, 0, 16, 31
-; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 31
+; CHECK-NEXT:    clrlwi 3, 3, 16
+; CHECK-NEXT:    clrlwi 4, 4, 28
 ; CHECK-NEXT:    srw 3, 3, 4
 ; CHECK-NEXT:    blr
   %rem = and i16 %b, 15
@@ -113,7 +113,7 @@
 define i32 @test102(i32 %a, i32 %b) {
 ; CHECK-LABEL: test102:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 4, 4, 0, 27, 31
+; CHECK-NEXT:    clrlwi 4, 4, 27
 ; CHECK-NEXT:    srw 3, 3, 4
 ; CHECK-NEXT:    blr
   %rem = and i32 %b, 31
@@ -124,7 +124,7 @@
 define i64 @test103(i64 %a, i64 %b) {
 ; CHECK-LABEL: test103:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 4, 4, 0, 26, 31
+; CHECK-NEXT:    clrlwi 4, 4, 26
 ; CHECK-NEXT:    srd 3, 3, 4
 ; CHECK-NEXT:    blr
   %rem = and i64 %b, 63
@@ -176,7 +176,7 @@
 ; CHECK-LABEL: test200:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    extsb 3, 3
-; CHECK-NEXT:    rlwinm 4, 4, 0, 29, 31
+; CHECK-NEXT:    clrlwi 4, 4, 29
 ; CHECK-NEXT:    sraw 3, 3, 4
 ; CHECK-NEXT:    blr
   %rem = and i8 %b, 7
@@ -188,7 +188,7 @@
 ; CHECK-LABEL: test201:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    extsh 3, 3
-; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 31
+; CHECK-NEXT:    clrlwi 4, 4, 28
 ; CHECK-NEXT:    sraw 3, 3, 4
 ; CHECK-NEXT:    blr
   %rem = and i16 %b, 15
@@ -199,7 +199,7 @@
 define i32 @test202(i32 %a, i32 %b) {
 ; CHECK-LABEL: test202:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 4, 4, 0, 27, 31
+; CHECK-NEXT:    clrlwi 4, 4, 27
 ; CHECK-NEXT:    sraw 3, 3, 4
 ; CHECK-NEXT:    blr
   %rem = and i32 %b, 31
@@ -210,7 +210,7 @@
 define i64 @test203(i64 %a, i64 %b) {
 ; CHECK-LABEL: test203:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 4, 4, 0, 26, 31
+; CHECK-NEXT:    clrlwi 4, 4, 26
 ; CHECK-NEXT:    srad 3, 3, 4
 ; CHECK-NEXT:    blr
   %rem = and i64 %b, 63
diff --git a/llvm/test/CodeGen/PowerPC/signbit-shift.ll b/llvm/test/CodeGen/PowerPC/signbit-shift.ll
--- a/llvm/test/CodeGen/PowerPC/signbit-shift.ll
+++ b/llvm/test/CodeGen/PowerPC/signbit-shift.ll
@@ -46,7 +46,7 @@
 ; CHECK-LABEL: sel_ifpos_tval_bigger:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, 41
-; CHECK-NEXT:    cmpwi 0, 3, -1
+; CHECK-NEXT:    cmpwi 3, -1
 ; CHECK-NEXT:    li 3, 42
 ; CHECK-NEXT:    isel 3, 3, 4, 1
 ; CHECK-NEXT:    blr
@@ -98,7 +98,7 @@
 ; CHECK-LABEL: sel_ifpos_fval_bigger:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, 42
-; CHECK-NEXT:    cmpwi 0, 3, -1
+; CHECK-NEXT:    cmpwi 3, -1
 ; CHECK-NEXT:    li 3, 41
 ; CHECK-NEXT:    isel 3, 3, 4, 1
 ; CHECK-NEXT:    blr
@@ -135,7 +135,7 @@
 ; CHECK-LABEL: sel_ifneg_tval_bigger:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, 41
-; CHECK-NEXT:    cmpwi 0, 3, 0
+; CHECK-NEXT:    cmpwi 3, 0
 ; CHECK-NEXT:    li 3, 42
 ; CHECK-NEXT:    isel 3, 3, 4, 0
 ; CHECK-NEXT:    blr
@@ -170,7 +170,7 @@
 ; CHECK-LABEL: sel_ifneg_fval_bigger:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, 42
-; CHECK-NEXT:    cmpwi 0, 3, 0
+; CHECK-NEXT:    cmpwi 3, 0
 ; CHECK-NEXT:    li 3, 41
 ; CHECK-NEXT:    isel 3, 3, 4, 0
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll b/llvm/test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll
--- a/llvm/test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll
+++ b/llvm/test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll
@@ -4,7 +4,7 @@
 define void @test(i32 zeroext %parts) {
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmplwi 0, 3, 1
+; CHECK-NEXT:    cmplwi 3, 1
 ; CHECK-NEXT:    bnelr+ 0
 ; CHECK-NEXT:  # %bb.1: # %test2.exit.us.unr-lcssa
 ; CHECK-NEXT:    ld 3, 0(3)
diff --git a/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll b/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
--- a/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
+++ b/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
@@ -13,7 +13,7 @@
 ; CHECK-NEXT:    lwz 3, 0(3)
 ; CHECK-NEXT:    addi 3, 3, -1
 ; CHECK-NEXT:    clrldi 4, 3, 32
-; CHECK-NEXT:    cmplwi 0, 3, 1
+; CHECK-NEXT:    cmplwi 3, 1
 ; CHECK-NEXT:    li 3, 1
 ; CHECK-NEXT:    isel 3, 4, 3, 1
 ; CHECK-NEXT:    li 4, 2
diff --git a/llvm/test/CodeGen/PowerPC/spill_p9_setb.ll b/llvm/test/CodeGen/PowerPC/spill_p9_setb.ll
--- a/llvm/test/CodeGen/PowerPC/spill_p9_setb.ll
+++ b/llvm/test/CodeGen/PowerPC/spill_p9_setb.ll
@@ -17,7 +17,7 @@
 define void @p9_setb_spill() {
 ; CHECK-P9-LABEL: p9_setb_spill:
 ; CHECK-P9:       # %bb.1: # %if.then
-; CHECK-P9-DAG:    crnor 4*cr[[CREG:.*]]+lt, eq, eq
+; CHECK-P9-DAG:    crnot 4*cr[[CREG:.*]]+lt, eq
 ; CHECK-P9-DAG:    setb [[REG1:.*]], cr[[CREG]]
 ; CHECK-P9-DAG:    stw [[REG1]]
 ; CHECK-P9:        blr
@@ -25,7 +25,7 @@
 ;
 ; CHECK-P8-LABEL: p9_setb_spill:
 ; CHECK-P8:       # %bb.1: # %if.then
-; CHECK-P8-DAG:    crnor 4*cr[[CREG2:.*]]+lt, eq, eq
+; CHECK-P8-DAG:    crnot 4*cr[[CREG2:.*]]+lt, eq
 ; CHECK-P8-DAG:    mfocrf [[REG2:.*]],
 ; CHECK-P8-DAG:    rlwinm [[REG2]], [[REG2]]
 ; CHECK-P8-DAG:    stw [[REG2]]
diff --git a/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll b/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
--- a/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
@@ -26,7 +26,7 @@
 ; P9LE-NEXT:    lis r5, 31710
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
@@ -42,7 +42,7 @@
 ; P9LE-NEXT:    mulli r4, r4, -124
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
@@ -57,7 +57,7 @@
 ; P9LE-NEXT:    mulli r4, r4, 98
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
@@ -72,7 +72,7 @@
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    vmrglh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v2, v3
@@ -157,7 +157,7 @@
 ; P8LE-NEXT:    ori r4, r4, 33437
 ; P8LE-NEXT:    ori r9, r9, 63249
 ; P8LE-NEXT:    ori r11, r11, 37253
-; P8LE-NEXT:    mfvsrd r5, f0
+; P8LE-NEXT:    mffprd r5, f0
 ; P8LE-NEXT:    rldicl r3, r5, 32, 48
 ; P8LE-NEXT:    rldicl r6, r5, 16, 48
 ; P8LE-NEXT:    clrldi r7, r5, 48
@@ -201,13 +201,13 @@
 ; P8LE-NEXT:    mulli r8, r8, -124
 ; P8LE-NEXT:    subf r3, r4, r3
 ; P8LE-NEXT:    subf r4, r9, r6
-; P8LE-NEXT:    mtvsrd f0, r3
+; P8LE-NEXT:    mtfprd f0, r3
 ; P8LE-NEXT:    subf r3, r10, r7
-; P8LE-NEXT:    mtvsrd f1, r4
+; P8LE-NEXT:    mtfprd f1, r4
 ; P8LE-NEXT:    subf r4, r8, r5
-; P8LE-NEXT:    mtvsrd f2, r3
+; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    mtvsrd f3, r4
+; P8LE-NEXT:    mtfprd f3, r4
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    xxswapd v4, vs2
 ; P8LE-NEXT:    xxswapd v5, vs3
@@ -302,7 +302,7 @@
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
@@ -316,7 +316,7 @@
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
@@ -330,7 +330,7 @@
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
@@ -345,7 +345,7 @@
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    vmrglh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v2, v3
@@ -422,7 +422,7 @@
 ; P8LE-NEXT:    lis r4, -21386
 ; P8LE-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; P8LE-NEXT:    ori r4, r4, 37253
-; P8LE-NEXT:    mfvsrd r5, f0
+; P8LE-NEXT:    mffprd r5, f0
 ; P8LE-NEXT:    clrldi r3, r5, 48
 ; P8LE-NEXT:    rldicl r7, r5, 32, 48
 ; P8LE-NEXT:    extsh r8, r3
@@ -466,13 +466,13 @@
 ; P8LE-NEXT:    mulli r4, r4, 95
 ; P8LE-NEXT:    subf r3, r8, r3
 ; P8LE-NEXT:    subf r6, r9, r6
-; P8LE-NEXT:    mtvsrd f0, r3
+; P8LE-NEXT:    mtfprd f0, r3
 ; P8LE-NEXT:    subf r3, r10, r7
 ; P8LE-NEXT:    subf r4, r4, r5
-; P8LE-NEXT:    mtvsrd f1, r6
-; P8LE-NEXT:    mtvsrd f2, r3
+; P8LE-NEXT:    mtfprd f1, r6
+; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    mtvsrd f3, r4
+; P8LE-NEXT:    mtfprd f3, r4
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    xxswapd v4, vs2
 ; P8LE-NEXT:    xxswapd v5, vs3
@@ -565,7 +565,7 @@
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    mulli r6, r4, 95
 ; P9LE-NEXT:    subf r3, r6, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r6, r3
@@ -579,7 +579,7 @@
 ; P9LE-NEXT:    mulli r7, r6, 95
 ; P9LE-NEXT:    subf r3, r7, r3
 ; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r7, r3
@@ -593,7 +593,7 @@
 ; P9LE-NEXT:    mulli r8, r7, 95
 ; P9LE-NEXT:    subf r3, r8, r3
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r8, r3
@@ -608,18 +608,18 @@
 ; P9LE-NEXT:    subf r3, r8, r3
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
-; P9LE-NEXT:    mtvsrd f0, r4
+; P9LE-NEXT:    mtfprd f0, r4
 ; P9LE-NEXT:    vmrglh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r6
+; P9LE-NEXT:    mtfprd f0, r6
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r7
+; P9LE-NEXT:    mtfprd f0, r7
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r5
+; P9LE-NEXT:    mtfprd f0, r5
 ; P9LE-NEXT:    xxswapd v5, vs0
 ; P9LE-NEXT:    vmrglh v4, v5, v4
 ; P9LE-NEXT:    vmrglw v3, v4, v3
@@ -709,7 +709,7 @@
 ; P8LE-NEXT:    lis r5, -21386
 ; P8LE-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; P8LE-NEXT:    ori r5, r5, 37253
-; P8LE-NEXT:    mfvsrd r6, f0
+; P8LE-NEXT:    mffprd r6, f0
 ; P8LE-NEXT:    clrldi r3, r6, 48
 ; P8LE-NEXT:    rldicl r4, r6, 48, 48
 ; P8LE-NEXT:    rldicl r7, r6, 32, 48
@@ -745,28 +745,28 @@
 ; P8LE-NEXT:    add r9, r0, r9
 ; P8LE-NEXT:    mulli r0, r8, 95
 ; P8LE-NEXT:    add r10, r12, r10
-; P8LE-NEXT:    mtvsrd f0, r8
+; P8LE-NEXT:    mtfprd f0, r8
 ; P8LE-NEXT:    srwi r8, r5, 31
 ; P8LE-NEXT:    srawi r5, r5, 6
 ; P8LE-NEXT:    mulli r11, r9, 95
-; P8LE-NEXT:    mtvsrd f1, r9
+; P8LE-NEXT:    mtfprd f1, r9
 ; P8LE-NEXT:    mulli r9, r10, 95
 ; P8LE-NEXT:    add r5, r5, r8
 ; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    mtvsrd f2, r10
-; P8LE-NEXT:    mtvsrd f3, r5
+; P8LE-NEXT:    mtfprd f2, r10
+; P8LE-NEXT:    mtfprd f3, r5
 ; P8LE-NEXT:    mulli r5, r5, 95
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    subf r3, r0, r3
 ; P8LE-NEXT:    xxswapd v1, vs2
-; P8LE-NEXT:    mtvsrd f0, r3
+; P8LE-NEXT:    mtfprd f0, r3
 ; P8LE-NEXT:    subf r4, r11, r4
 ; P8LE-NEXT:    xxswapd v6, vs3
 ; P8LE-NEXT:    subf r3, r9, r7
-; P8LE-NEXT:    mtvsrd f1, r4
-; P8LE-NEXT:    mtvsrd f4, r3
+; P8LE-NEXT:    mtfprd f1, r4
+; P8LE-NEXT:    mtfprd f4, r3
 ; P8LE-NEXT:    subf r3, r5, r6
-; P8LE-NEXT:    mtvsrd f5, r3
+; P8LE-NEXT:    mtfprd f5, r3
 ; P8LE-NEXT:    xxswapd v4, vs1
 ; P8LE-NEXT:    vmrglh v2, v3, v2
 ; P8LE-NEXT:    xxswapd v3, vs0
@@ -870,7 +870,7 @@
 ; P9LE-NEXT:    addze r4, r4
 ; P9LE-NEXT:    slwi r4, r4, 6
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
@@ -879,7 +879,7 @@
 ; P9LE-NEXT:    slwi r4, r4, 5
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
@@ -896,7 +896,7 @@
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
@@ -905,7 +905,7 @@
 ; P9LE-NEXT:    slwi r4, r4, 3
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    vmrglh v2, v4, v2
 ; P9LE-NEXT:    vmrglw v2, v2, v3
@@ -966,7 +966,7 @@
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, -21386
 ; P8LE-NEXT:    ori r3, r3, 37253
-; P8LE-NEXT:    mfvsrd r4, f0
+; P8LE-NEXT:    mffprd r4, f0
 ; P8LE-NEXT:    rldicl r5, r4, 16, 48
 ; P8LE-NEXT:    clrldi r7, r4, 48
 ; P8LE-NEXT:    extsh r6, r5
@@ -982,7 +982,7 @@
 ; P8LE-NEXT:    slwi r8, r8, 6
 ; P8LE-NEXT:    subf r7, r8, r7
 ; P8LE-NEXT:    rldicl r3, r3, 32, 32
-; P8LE-NEXT:    mtvsrd f0, r7
+; P8LE-NEXT:    mtfprd f0, r7
 ; P8LE-NEXT:    add r3, r3, r6
 ; P8LE-NEXT:    addze r6, r10
 ; P8LE-NEXT:    srwi r10, r3, 31
@@ -994,14 +994,14 @@
 ; P8LE-NEXT:    subf r6, r6, r9
 ; P8LE-NEXT:    mulli r3, r3, 95
 ; P8LE-NEXT:    srawi r8, r10, 3
-; P8LE-NEXT:    mtvsrd f1, r6
+; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    addze r7, r8
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    subf r3, r3, r5
 ; P8LE-NEXT:    slwi r5, r7, 3
 ; P8LE-NEXT:    subf r4, r5, r4
-; P8LE-NEXT:    mtvsrd f2, r3
-; P8LE-NEXT:    mtvsrd f3, r4
+; P8LE-NEXT:    mtfprd f2, r3
+; P8LE-NEXT:    mtfprd f3, r4
 ; P8LE-NEXT:    xxswapd v4, vs2
 ; P8LE-NEXT:    vmrglh v2, v3, v2
 ; P8LE-NEXT:    xxswapd v5, vs3
@@ -1079,7 +1079,7 @@
 ; P9LE-NEXT:    lis r5, -19946
 ; P9LE-NEXT:    mulli r4, r4, 654
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
@@ -1095,7 +1095,7 @@
 ; P9LE-NEXT:    mulli r4, r4, 23
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
@@ -1110,7 +1110,7 @@
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    vmrglh v3, v3, v4
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    vmrglh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v2, v3
@@ -1182,7 +1182,7 @@
 ; P8LE-NEXT:    xxlxor v5, v5, v5
 ; P8LE-NEXT:    ori r3, r3, 47143
 ; P8LE-NEXT:    ori r8, r8, 17097
-; P8LE-NEXT:    mfvsrd r4, f0
+; P8LE-NEXT:    mffprd r4, f0
 ; P8LE-NEXT:    rldicl r5, r4, 16, 48
 ; P8LE-NEXT:    rldicl r6, r4, 32, 48
 ; P8LE-NEXT:    rldicl r4, r4, 48, 48
@@ -1214,11 +1214,11 @@
 ; P8LE-NEXT:    mulli r8, r8, 23
 ; P8LE-NEXT:    mulli r7, r7, 654
 ; P8LE-NEXT:    subf r3, r3, r5
-; P8LE-NEXT:    mtvsrd f0, r3
+; P8LE-NEXT:    mtfprd f0, r3
 ; P8LE-NEXT:    subf r3, r8, r6
 ; P8LE-NEXT:    subf r4, r7, r4
-; P8LE-NEXT:    mtvsrd f1, r3
-; P8LE-NEXT:    mtvsrd f2, r4
+; P8LE-NEXT:    mtfprd f1, r3
+; P8LE-NEXT:    mtfprd f2, r4
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    xxswapd v4, vs2
@@ -1304,7 +1304,7 @@
 ; P9LE-NEXT:    lis r5, 24749
 ; P9LE-NEXT:    mulli r4, r4, 23
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
@@ -1318,7 +1318,7 @@
 ; P9LE-NEXT:    mulli r4, r4, 5423
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
@@ -1327,7 +1327,7 @@
 ; P9LE-NEXT:    slwi r4, r4, 15
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxlxor v4, v4, v4
@@ -1393,7 +1393,7 @@
 ; P8LE-NEXT:    xxlxor v5, v5, v5
 ; P8LE-NEXT:    ori r6, r6, 47143
 ; P8LE-NEXT:    ori r7, r7, 17097
-; P8LE-NEXT:    mfvsrd r3, f0
+; P8LE-NEXT:    mffprd r3, f0
 ; P8LE-NEXT:    rldicl r4, r3, 16, 48
 ; P8LE-NEXT:    rldicl r5, r3, 32, 48
 ; P8LE-NEXT:    extsh r8, r4
@@ -1418,13 +1418,13 @@
 ; P8LE-NEXT:    srawi r8, r8, 15
 ; P8LE-NEXT:    subf r4, r6, r4
 ; P8LE-NEXT:    addze r6, r8
-; P8LE-NEXT:    mtvsrd f0, r4
+; P8LE-NEXT:    mtfprd f0, r4
 ; P8LE-NEXT:    slwi r4, r6, 15
 ; P8LE-NEXT:    subf r5, r7, r5
 ; P8LE-NEXT:    subf r3, r4, r3
-; P8LE-NEXT:    mtvsrd f1, r5
+; P8LE-NEXT:    mtfprd f1, r5
 ; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    mtvsrd f2, r3
+; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    xxswapd v4, vs2
 ; P8LE-NEXT:    vmrglh v2, v2, v3
@@ -1588,7 +1588,7 @@
 ; P8LE-NEXT:    sldi r5, r5, 32
 ; P8LE-NEXT:    oris r3, r3, 58853
 ; P8LE-NEXT:    oris r4, r4, 22795
-; P8LE-NEXT:    mfvsrd r8, f0
+; P8LE-NEXT:    mffprd r8, f0
 ; P8LE-NEXT:    oris r5, r5, 1603
 ; P8LE-NEXT:    ori r3, r3, 6055
 ; P8LE-NEXT:    ori r4, r4, 8549
@@ -1610,13 +1610,13 @@
 ; P8LE-NEXT:    add r4, r4, r9
 ; P8LE-NEXT:    mulli r4, r4, 23
 ; P8LE-NEXT:    sub r3, r6, r3
-; P8LE-NEXT:    mtvsrd f0, r3
+; P8LE-NEXT:    mtfprd f0, r3
 ; P8LE-NEXT:    sub r5, r7, r5
-; P8LE-NEXT:    mtvsrd f1, r5
+; P8LE-NEXT:    mtfprd f1, r5
 ; P8LE-NEXT:    sub r3, r8, r4
 ; P8LE-NEXT:    li r4, 0
-; P8LE-NEXT:    mtvsrd f2, r3
-; P8LE-NEXT:    mtvsrd f3, r4
+; P8LE-NEXT:    mtfprd f2, r3
+; P8LE-NEXT:    mtfprd f3, r4
 ; P8LE-NEXT:    xxmrghd v3, vs0, vs2
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs3
 ; P8LE-NEXT:    blr
@@ -1637,11 +1637,11 @@
 ; P8BE-NEXT:    oris r4, r4, 22795
 ; P8BE-NEXT:    sldi r5, r5, 32
 ; P8BE-NEXT:    oris r3, r3, 58853
-; P8BE-NEXT:    mfvsrd r7, f0
+; P8BE-NEXT:    mffprd r7, f0
 ; P8BE-NEXT:    ori r4, r4, 8549
 ; P8BE-NEXT:    ori r3, r3, 6055
 ; P8BE-NEXT:    oris r5, r5, 1603
-; P8BE-NEXT:    mfvsrd r8, f1
+; P8BE-NEXT:    mffprd r8, f1
 ; P8BE-NEXT:    mulhd r4, r6, r4
 ; P8BE-NEXT:    mulhd r3, r7, r3
 ; P8BE-NEXT:    ori r5, r5, 21445
@@ -1661,12 +1661,12 @@
 ; P8BE-NEXT:    mulli r5, r5, 654
 ; P8BE-NEXT:    sub r3, r7, r3
 ; P8BE-NEXT:    sub r4, r6, r4
-; P8BE-NEXT:    mtvsrd f0, r3
+; P8BE-NEXT:    mtfprd f0, r3
 ; P8BE-NEXT:    sub r3, r8, r5
-; P8BE-NEXT:    mtvsrd f1, r4
+; P8BE-NEXT:    mtfprd f1, r4
 ; P8BE-NEXT:    li r4, 0
-; P8BE-NEXT:    mtvsrd f2, r3
-; P8BE-NEXT:    mtvsrd f3, r4
+; P8BE-NEXT:    mtfprd f2, r3
+; P8BE-NEXT:    mtfprd f3, r4
 ; P8BE-NEXT:    xxmrghd v3, vs1, vs0
 ; P8BE-NEXT:    xxmrghd v2, vs3, vs2
 ; P8BE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/stack-realign.ll b/llvm/test/CodeGen/PowerPC/stack-realign.ll
--- a/llvm/test/CodeGen/PowerPC/stack-realign.ll
+++ b/llvm/test/CodeGen/PowerPC/stack-realign.ll
@@ -129,7 +129,7 @@
 ; CHECK-DAG: std 30, -16(1)
 ; CHECK-DAG: mr 30, 1
 ; CHECK-DAG: std 0, 16(1)
-; CHECK-DAG: subfc 0, [[REG3]], [[REG2]]
+; CHECK-DAG: subc 0, [[REG2]], [[REG3]]
 ; CHECK: stdux 1, 1, 0
 
 ; CHECK: .cfi_def_cfa_register r30
diff --git a/llvm/test/CodeGen/PowerPC/swaps-le-6.ll b/llvm/test/CodeGen/PowerPC/swaps-le-6.ll
--- a/llvm/test/CodeGen/PowerPC/swaps-le-6.ll
+++ b/llvm/test/CodeGen/PowerPC/swaps-le-6.ll
@@ -52,7 +52,7 @@
 ; CHECK-P9:     lfd f1, 0(r3)
 ; CHECK-P9:     addis r3, r2, .LC2@toc@ha
 ; CHECK-P9:     ld r3, .LC2@toc@l(r3)
-; CHECK-P9:     xxpermdi vs1, f1, f1, 2
+; CHECK-P9:     xxswapd vs1, f1
 ; CHECK-P9:     xxpermdi vs0, vs0, vs1, 1
 ; CHECK-P9:     stxvx vs0, 0, r3
 ; CHECK-P9:     blr
@@ -97,7 +97,7 @@
 ; CHECK-P9:     lfd f1, 0(r3)
 ; CHECK-P9:     addis r3, r2, .LC2@toc@ha
 ; CHECK-P9:     ld r3, .LC2@toc@l(r3)
-; CHECK-P9:     xxpermdi vs1, f1, f1, 2
+; CHECK-P9:     xxswapd vs1, f1
 ; CHECK-P9:     xxmrgld vs0, vs1, vs0
 ; CHECK-P9:     stxvx vs0, 0, r3
 ; CHECK-P9:     blr
diff --git a/llvm/test/CodeGen/PowerPC/testBitReverse.ll b/llvm/test/CodeGen/PowerPC/testBitReverse.ll
--- a/llvm/test/CodeGen/PowerPC/testBitReverse.ll
+++ b/llvm/test/CodeGen/PowerPC/testBitReverse.ll
@@ -91,8 +91,8 @@
 ; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    or 3, 3, 5
 ; CHECK-NEXT:    rldicl 4, 3, 32, 32
-; CHECK-NEXT:    rlwinm 5, 3, 24, 0, 31
-; CHECK-NEXT:    rlwinm 6, 4, 24, 0, 31
+; CHECK-NEXT:    rotlwi 5, 3, 24
+; CHECK-NEXT:    rotlwi 6, 4, 24
 ; CHECK-NEXT:    rlwimi 5, 3, 8, 8, 15
 ; CHECK-NEXT:    rlwimi 5, 3, 8, 24, 31
 ; CHECK-NEXT:    rlwimi 6, 4, 8, 8, 15
diff --git a/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll b/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll
@@ -72,8 +72,8 @@
 define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: testCompare2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    rlwinm r3, r3, 0, 31, 31
-; CHECK-NEXT:    rlwinm r4, r4, 0, 31, 31
+; CHECK-NEXT:    clrlwi r3, r3, 31
+; CHECK-NEXT:    clrlwi r4, r4, 31
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    clrldi r4, r4, 32
 ; CHECK-NEXT:    sub r3, r4, r3
diff --git a/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll b/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll
@@ -9,8 +9,8 @@
 define signext i32 @test(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    rlwinm r3, r3, 0, 31, 31
-; CHECK-NEXT:    rlwinm r4, r4, 0, 31, 31
+; CHECK-NEXT:    clrlwi r3, r3, 31
+; CHECK-NEXT:    clrlwi r4, r4, 31
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    clrldi r4, r4, 32
 ; CHECK-NEXT:    sub r3, r4, r3
diff --git a/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll b/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll
@@ -72,8 +72,8 @@
 define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: testCompare2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    rlwinm r3, r3, 0, 31, 31
-; CHECK-NEXT:    rlwinm r4, r4, 0, 31, 31
+; CHECK-NEXT:    clrlwi r3, r3, 31
+; CHECK-NEXT:    clrlwi r4, r4, 31
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    clrldi r4, r4, 32
 ; CHECK-NEXT:    sub r3, r3, r4
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigesll.ll b/llvm/test/CodeGen/PowerPC/testComparesigesll.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesigesll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigesll.ll
@@ -19,7 +19,7 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r5, r3, 63
 ; CHECK-BE-NEXT:    rldicl r6, r4, 1, 63
-; CHECK-BE-NEXT:    subfc r3, r4, r3
+; CHECK-BE-NEXT:    subc r3, r3, r4
 ; CHECK-BE-NEXT:    adde r3, r5, r6
 ; CHECK-BE-NEXT:    blr
 ;
@@ -27,7 +27,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r5, r3, 63
 ; CHECK-LE-NEXT:    rldicl r6, r4, 1, 63
-; CHECK-LE-NEXT:    subfc r3, r4, r3
+; CHECK-LE-NEXT:    subc r3, r3, r4
 ; CHECK-LE-NEXT:    adde r3, r5, r6
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -49,7 +49,7 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r5, r3, 63
 ; CHECK-BE-NEXT:    rldicl r6, r4, 1, 63
-; CHECK-BE-NEXT:    subfc r3, r4, r3
+; CHECK-BE-NEXT:    subc r3, r3, r4
 ; CHECK-BE-NEXT:    adde r3, r5, r6
 ; CHECK-BE-NEXT:    neg r3, r3
 ; CHECK-BE-NEXT:    blr
@@ -58,7 +58,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r5, r3, 63
 ; CHECK-LE-NEXT:    rldicl r6, r4, 1, 63
-; CHECK-LE-NEXT:    subfc r3, r4, r3
+; CHECK-LE-NEXT:    subc r3, r3, r4
 ; CHECK-LE-NEXT:    adde r3, r5, r6
 ; CHECK-LE-NEXT:    neg r3, r3
 ; CHECK-LE-NEXT:    blr
@@ -129,7 +129,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sradi r6, r3, 63
 ; CHECK-BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    subfc r3, r4, r3
+; CHECK-BE-NEXT:    subc r3, r3, r4
 ; CHECK-BE-NEXT:    rldicl r3, r4, 1, 63
 ; CHECK-BE-NEXT:    adde r3, r6, r3
 ; CHECK-BE-NEXT:    std r3, 0(r5)
@@ -139,7 +139,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r6, r3, 63
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    subfc r3, r4, r3
+; CHECK-LE-NEXT:    subc r3, r3, r4
 ; CHECK-LE-NEXT:    rldicl r3, r4, 1, 63
 ; CHECK-LE-NEXT:    adde r3, r6, r3
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
@@ -166,7 +166,7 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r6, r3, 63
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    subfc r3, r4, r3
+; CHECK-BE-NEXT:    subc r3, r3, r4
 ; CHECK-BE-NEXT:    rldicl r3, r4, 1, 63
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    adde r3, r6, r3
@@ -178,7 +178,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r6, r3, 63
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    subfc r3, r4, r3
+; CHECK-LE-NEXT:    subc r3, r3, r4
 ; CHECK-LE-NEXT:    rldicl r3, r4, 1, 63
 ; CHECK-LE-NEXT:    adde r3, r6, r3
 ; CHECK-LE-NEXT:    neg r3, r3
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeull.ll b/llvm/test/CodeGen/PowerPC/testComparesigeull.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesigeull.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigeull.ll
@@ -14,7 +14,7 @@
 define signext i32 @test_igeull(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igeull:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    subc r3, r3, r4
 ; CHECK-NEXT:    subfe r3, r4, r4
 ; CHECK-NEXT:    addi r3, r3, 1
 ; CHECK-NEXT:    blr
@@ -28,7 +28,7 @@
 define signext i32 @test_igeull_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igeull_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    subc r3, r3, r4
 ; CHECK-NEXT:    subfe r3, r4, r4
 ; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    blr
@@ -67,7 +67,7 @@
 ; BE-LABEL: test_igeull_store:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subfc r3, r4, r3
+; BE-NEXT:    subc r3, r3, r4
 ; BE-NEXT:    ld r3, .LC0@toc@l(r5)
 ; BE-NEXT:    subfe r4, r4, r4
 ; BE-NEXT:    addi r4, r4, 1
@@ -76,7 +76,7 @@
 ;
 ; LE-LABEL: test_igeull_store:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    subfc r3, r4, r3
+; LE-NEXT:    subc r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    subfe r3, r4, r4
 ; LE-NEXT:    addi r3, r3, 1
@@ -94,7 +94,7 @@
 ; BE-LABEL: test_igeull_sext_store:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subfc r3, r4, r3
+; BE-NEXT:    subc r3, r3, r4
 ; BE-NEXT:    ld r3, .LC0@toc@l(r5)
 ; BE-NEXT:    subfe r4, r4, r4
 ; BE-NEXT:    not r4, r4
@@ -103,7 +103,7 @@
 ;
 ; LE-LABEL: test_igeull_sext_store:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    subfc r3, r4, r3
+; LE-NEXT:    subc r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    subfe r3, r4, r4
 ; LE-NEXT:    not r3, r3
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll b/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll
@@ -14,7 +14,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r4, 63
 ; CHECK-NEXT:    rldicl r6, r3, 1, 63
-; CHECK-NEXT:    subfc r3, r3, r4
+; CHECK-NEXT:    subc r3, r4, r3
 ; CHECK-NEXT:    adde r3, r6, r5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
@@ -30,7 +30,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r4, 63
 ; CHECK-NEXT:    rldicl r6, r3, 1, 63
-; CHECK-NEXT:    subfc r3, r3, r4
+; CHECK-NEXT:    subc r3, r4, r3
 ; CHECK-NEXT:    adde r3, r6, r5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    neg r3, r3
@@ -76,7 +76,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r6, r4, 63
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    subc r4, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-NEXT:    adde r3, r3, r6
@@ -97,7 +97,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r6, r4, 63
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    subc r4, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    adde r3, r3, r6
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
diff --git a/llvm/test/CodeGen/PowerPC/testComparesilesll.ll b/llvm/test/CodeGen/PowerPC/testComparesilesll.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesilesll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesilesll.ll
@@ -19,7 +19,7 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r5, r4, 63
 ; CHECK-BE-NEXT:    rldicl r6, r3, 1, 63
-; CHECK-BE-NEXT:    subfc r3, r3, r4
+; CHECK-BE-NEXT:    subc r3, r4, r3
 ; CHECK-BE-NEXT:    adde r3, r5, r6
 ; CHECK-BE-NEXT:    blr
 ;
@@ -27,7 +27,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r5, r4, 63
 ; CHECK-LE-NEXT:    rldicl r6, r3, 1, 63
-; CHECK-LE-NEXT:    subfc r3, r3, r4
+; CHECK-LE-NEXT:    subc r3, r4, r3
 ; CHECK-LE-NEXT:    adde r3, r5, r6
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -49,7 +49,7 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r5, r4, 63
 ; CHECK-BE-NEXT:    rldicl r6, r3, 1, 63
-; CHECK-BE-NEXT:    subfc r3, r3, r4
+; CHECK-BE-NEXT:    subc r3, r4, r3
 ; CHECK-BE-NEXT:    adde r3, r5, r6
 ; CHECK-BE-NEXT:    neg r3, r3
 ; CHECK-BE-NEXT:    blr
@@ -58,7 +58,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r5, r4, 63
 ; CHECK-LE-NEXT:    rldicl r6, r3, 1, 63
-; CHECK-LE-NEXT:    subfc r3, r3, r4
+; CHECK-LE-NEXT:    subc r3, r4, r3
 ; CHECK-LE-NEXT:    adde r3, r5, r6
 ; CHECK-LE-NEXT:    neg r3, r3
 ; CHECK-LE-NEXT:    blr
@@ -135,7 +135,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sradi r6, r4, 63
 ; CHECK-BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    subfc r4, r3, r4
+; CHECK-BE-NEXT:    subc r4, r4, r3
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    adde r3, r6, r3
 ; CHECK-BE-NEXT:    std r3, 0(r5)
@@ -145,7 +145,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r6, r4, 63
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    subfc r4, r3, r4
+; CHECK-LE-NEXT:    subc r4, r4, r3
 ; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-LE-NEXT:    adde r3, r6, r3
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
@@ -172,7 +172,7 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r6, r4, 63
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    subfc r4, r3, r4
+; CHECK-BE-NEXT:    subc r4, r4, r3
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    adde r3, r6, r3
@@ -184,7 +184,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r6, r4, 63
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    subfc r4, r3, r4
+; CHECK-LE-NEXT:    subc r4, r4, r3
 ; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-LE-NEXT:    adde r3, r6, r3
 ; CHECK-LE-NEXT:    neg r3, r3
diff --git a/llvm/test/CodeGen/PowerPC/testComparesileull.ll b/llvm/test/CodeGen/PowerPC/testComparesileull.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesileull.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesileull.ll
@@ -14,7 +14,7 @@
 define signext i32 @test_ileull(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ileull:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    subc r4, r4, r3
 ; CHECK-NEXT:    subfe r3, r3, r3
 ; CHECK-NEXT:    addi r3, r3, 1
 ; CHECK-NEXT:    blr
@@ -28,7 +28,7 @@
 define signext i32 @test_ileull_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ileull_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    subc r4, r4, r3
 ; CHECK-NEXT:    subfe r3, r3, r3
 ; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    blr
@@ -69,7 +69,7 @@
 ; BE-LABEL: test_ileull_store:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subfc r4, r3, r4
+; BE-NEXT:    subc r4, r4, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    subfe r3, r3, r3
 ; BE-NEXT:    addi r3, r3, 1
@@ -78,7 +78,7 @@
 ;
 ; LE-LABEL: test_ileull_store:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    subfc r4, r3, r4
+; LE-NEXT:    subc r4, r4, r3
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    subfe r3, r3, r3
 ; LE-NEXT:    addi r3, r3, 1
@@ -96,7 +96,7 @@
 ; BE-LABEL: test_ileull_sext_store:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subfc r4, r3, r4
+; BE-NEXT:    subc r4, r4, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    subfe r3, r3, r3
 ; BE-NEXT:    not r3, r3
@@ -105,7 +105,7 @@
 ;
 ; LE-LABEL: test_ileull_sext_store:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    subfc r4, r3, r4
+; LE-NEXT:    subc r4, r4, r3
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    subfe r3, r3, r3
 ; LE-NEXT:    not r3, r3
diff --git a/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll b/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll
@@ -16,7 +16,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r3, 63
 ; CHECK-NEXT:    rldicl r6, r4, 1, 63
-; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    subc r3, r3, r4
 ; CHECK-NEXT:    adde r3, r6, r5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
@@ -32,7 +32,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r3, 63
 ; CHECK-NEXT:    rldicl r6, r4, 1, 63
-; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    subc r3, r3, r4
 ; CHECK-NEXT:    adde r3, r6, r5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    neg r3, r3
@@ -61,7 +61,7 @@
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    sradi r6, r3, 63
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subfc r3, r4, r3
+; BE-NEXT:    subc r3, r3, r4
 ; BE-NEXT:    rldicl r3, r4, 1, 63
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    adde r3, r3, r6
@@ -73,7 +73,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sradi r6, r3, 63
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    subfc r3, r4, r3
+; LE-NEXT:    subc r3, r3, r4
 ; LE-NEXT:    rldicl r3, r4, 1, 63
 ; LE-NEXT:    adde r3, r3, r6
 ; LE-NEXT:    xori r3, r3, 1
@@ -93,7 +93,7 @@
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    sradi r6, r3, 63
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subfc r3, r4, r3
+; BE-NEXT:    subc r3, r3, r4
 ; BE-NEXT:    rldicl r3, r4, 1, 63
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    adde r3, r3, r6
@@ -106,7 +106,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sradi r6, r3, 63
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    subfc r3, r4, r3
+; LE-NEXT:    subc r3, r3, r4
 ; LE-NEXT:    rldicl r3, r4, 1, 63
 ; LE-NEXT:    adde r3, r3, r6
 ; LE-NEXT:    xori r3, r3, 1
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll b/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll
@@ -19,7 +19,7 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r5, r3, 63
 ; CHECK-BE-NEXT:    rldicl r6, r4, 1, 63
-; CHECK-BE-NEXT:    subfc r3, r4, r3
+; CHECK-BE-NEXT:    subc r3, r3, r4
 ; CHECK-BE-NEXT:    adde r3, r5, r6
 ; CHECK-BE-NEXT:    blr
 ;
@@ -27,7 +27,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r5, r3, 63
 ; CHECK-LE-NEXT:    rldicl r6, r4, 1, 63
-; CHECK-LE-NEXT:    subfc r3, r4, r3
+; CHECK-LE-NEXT:    subc r3, r3, r4
 ; CHECK-LE-NEXT:    adde r3, r5, r6
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -49,7 +49,7 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r5, r3, 63
 ; CHECK-BE-NEXT:    rldicl r6, r4, 1, 63
-; CHECK-BE-NEXT:    subfc r3, r4, r3
+; CHECK-BE-NEXT:    subc r3, r3, r4
 ; CHECK-BE-NEXT:    adde r3, r5, r6
 ; CHECK-BE-NEXT:    neg r3, r3
 ; CHECK-BE-NEXT:    blr
@@ -58,7 +58,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r5, r3, 63
 ; CHECK-LE-NEXT:    rldicl r6, r4, 1, 63
-; CHECK-LE-NEXT:    subfc r3, r4, r3
+; CHECK-LE-NEXT:    subc r3, r3, r4
 ; CHECK-LE-NEXT:    adde r3, r5, r6
 ; CHECK-LE-NEXT:    neg r3, r3
 ; CHECK-LE-NEXT:    blr
@@ -129,7 +129,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sradi r6, r3, 63
 ; CHECK-BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    subfc r3, r4, r3
+; CHECK-BE-NEXT:    subc r3, r3, r4
 ; CHECK-BE-NEXT:    rldicl r3, r4, 1, 63
 ; CHECK-BE-NEXT:    adde r3, r6, r3
 ; CHECK-BE-NEXT:    std r3, 0(r5)
@@ -139,7 +139,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r6, r3, 63
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    subfc r3, r4, r3
+; CHECK-LE-NEXT:    subc r3, r3, r4
 ; CHECK-LE-NEXT:    rldicl r3, r4, 1, 63
 ; CHECK-LE-NEXT:    adde r3, r6, r3
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
@@ -166,7 +166,7 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r6, r3, 63
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    subfc r3, r4, r3
+; CHECK-BE-NEXT:    subc r3, r3, r4
 ; CHECK-BE-NEXT:    rldicl r3, r4, 1, 63
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    adde r3, r6, r3
@@ -178,7 +178,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r6, r3, 63
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    subfc r3, r4, r3
+; CHECK-LE-NEXT:    subc r3, r3, r4
 ; CHECK-LE-NEXT:    rldicl r3, r4, 1, 63
 ; CHECK-LE-NEXT:    adde r3, r6, r3
 ; CHECK-LE-NEXT:    neg r3, r3
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeull.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeull.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllgeull.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgeull.ll
@@ -14,7 +14,7 @@
 define i64 @test_llgeull(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llgeull:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    subc r3, r3, r4
 ; CHECK-NEXT:    subfe r3, r4, r4
 ; CHECK-NEXT:    addi r3, r3, 1
 ; CHECK-NEXT:    blr
@@ -28,7 +28,7 @@
 define i64 @test_llgeull_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llgeull_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    subc r3, r3, r4
 ; CHECK-NEXT:    subfe r3, r4, r4
 ; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    blr
@@ -67,7 +67,7 @@
 ; BE-LABEL: test_llgeull_store:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subfc r3, r4, r3
+; BE-NEXT:    subc r3, r3, r4
 ; BE-NEXT:    ld r3, .LC0@toc@l(r5)
 ; BE-NEXT:    subfe r4, r4, r4
 ; BE-NEXT:    addi r4, r4, 1
@@ -76,7 +76,7 @@
 ;
 ; LE-LABEL: test_llgeull_store:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    subfc r3, r4, r3
+; LE-NEXT:    subc r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    subfe r3, r4, r4
 ; LE-NEXT:    addi r3, r3, 1
@@ -94,7 +94,7 @@
 ; BE-LABEL: test_llgeull_sext_store:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subfc r3, r4, r3
+; BE-NEXT:    subc r3, r3, r4
 ; BE-NEXT:    ld r3, .LC0@toc@l(r5)
 ; BE-NEXT:    subfe r4, r4, r4
 ; BE-NEXT:    not r4, r4
@@ -103,7 +103,7 @@
 ;
 ; LE-LABEL: test_llgeull_sext_store:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    subfc r3, r4, r3
+; LE-NEXT:    subc r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    subfe r3, r4, r4
 ; LE-NEXT:    not r3, r3
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll b/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll
@@ -14,7 +14,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r4, 63
 ; CHECK-NEXT:    rldicl r6, r3, 1, 63
-; CHECK-NEXT:    subfc r3, r3, r4
+; CHECK-NEXT:    subc r3, r4, r3
 ; CHECK-NEXT:    adde r3, r6, r5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
@@ -30,7 +30,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r4, 63
 ; CHECK-NEXT:    rldicl r6, r3, 1, 63
-; CHECK-NEXT:    subfc r3, r3, r4
+; CHECK-NEXT:    subc r3, r4, r3
 ; CHECK-NEXT:    adde r3, r6, r5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    neg r3, r3
@@ -76,7 +76,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r6, r4, 63
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    subc r4, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-NEXT:    adde r3, r3, r6
@@ -97,7 +97,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r6, r4, 63
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    subc r4, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    adde r3, r3, r6
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
diff --git a/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll b/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll
--- a/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll
@@ -20,7 +20,7 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r5, r4, 63
 ; CHECK-BE-NEXT:    rldicl r6, r3, 1, 63
-; CHECK-BE-NEXT:    subfc r3, r3, r4
+; CHECK-BE-NEXT:    subc r3, r4, r3
 ; CHECK-BE-NEXT:    adde r3, r5, r6
 ; CHECK-BE-NEXT:    blr
 ;
@@ -28,7 +28,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r5, r4, 63
 ; CHECK-LE-NEXT:    rldicl r6, r3, 1, 63
-; CHECK-LE-NEXT:    subfc r3, r3, r4
+; CHECK-LE-NEXT:    subc r3, r4, r3
 ; CHECK-LE-NEXT:    adde r3, r5, r6
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -51,7 +51,7 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r5, r4, 63
 ; CHECK-BE-NEXT:    rldicl r6, r3, 1, 63
-; CHECK-BE-NEXT:    subfc r3, r3, r4
+; CHECK-BE-NEXT:    subc r3, r4, r3
 ; CHECK-BE-NEXT:    adde r3, r5, r6
 ; CHECK-BE-NEXT:    neg r3, r3
 ; CHECK-BE-NEXT:    blr
@@ -60,7 +60,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r5, r4, 63
 ; CHECK-LE-NEXT:    rldicl r6, r3, 1, 63
-; CHECK-LE-NEXT:    subfc r3, r3, r4
+; CHECK-LE-NEXT:    subc r3, r4, r3
 ; CHECK-LE-NEXT:    adde r3, r5, r6
 ; CHECK-LE-NEXT:    neg r3, r3
 ; CHECK-LE-NEXT:    blr
@@ -140,7 +140,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sradi r6, r4, 63
 ; CHECK-BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    subfc r4, r3, r4
+; CHECK-BE-NEXT:    subc r4, r4, r3
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    adde r3, r6, r3
 ; CHECK-BE-NEXT:    std r3, 0(r5)
@@ -150,7 +150,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r6, r4, 63
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    subfc r4, r3, r4
+; CHECK-LE-NEXT:    subc r4, r4, r3
 ; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-LE-NEXT:    adde r3, r6, r3
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
@@ -178,7 +178,7 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r6, r4, 63
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    subfc r4, r3, r4
+; CHECK-BE-NEXT:    subc r4, r4, r3
 ; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    adde r3, r6, r3
@@ -190,7 +190,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r6, r4, 63
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    subfc r4, r3, r4
+; CHECK-LE-NEXT:    subc r4, r4, r3
 ; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-LE-NEXT:    adde r3, r6, r3
 ; CHECK-LE-NEXT:    neg r3, r3
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleull.ll b/llvm/test/CodeGen/PowerPC/testComparesllleull.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllleull.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllleull.ll
@@ -14,7 +14,7 @@
 define i64 @test_llleull(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llleull:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    subc r4, r4, r3
 ; CHECK-NEXT:    subfe r3, r3, r3
 ; CHECK-NEXT:    addi r3, r3, 1
 ; CHECK-NEXT:    blr
@@ -28,7 +28,7 @@
 define i64 @test_llleull_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llleull_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    subc r4, r4, r3
 ; CHECK-NEXT:    subfe r3, r3, r3
 ; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    blr
@@ -69,7 +69,7 @@
 ; BE-LABEL: test_llleull_store:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subfc r4, r3, r4
+; BE-NEXT:    subc r4, r4, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    subfe r3, r3, r3
 ; BE-NEXT:    addi r3, r3, 1
@@ -78,7 +78,7 @@
 ;
 ; LE-LABEL: test_llleull_store:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    subfc r4, r3, r4
+; LE-NEXT:    subc r4, r4, r3
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    subfe r3, r3, r3
 ; LE-NEXT:    addi r3, r3, 1
@@ -96,7 +96,7 @@
 ; BE-LABEL: test_llleull_sext_store:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subfc r4, r3, r4
+; BE-NEXT:    subc r4, r4, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    subfe r3, r3, r3
 ; BE-NEXT:    not r3, r3
@@ -105,7 +105,7 @@
 ;
 ; LE-LABEL: test_llleull_sext_store:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    subfc r4, r3, r4
+; LE-NEXT:    subc r4, r4, r3
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    subfe r3, r3, r3
 ; LE-NEXT:    not r3, r3
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll b/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll
@@ -16,7 +16,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r3, 63
 ; CHECK-NEXT:    rldicl r6, r4, 1, 63
-; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    subc r3, r3, r4
 ; CHECK-NEXT:    adde r3, r6, r5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
@@ -32,7 +32,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r3, 63
 ; CHECK-NEXT:    rldicl r6, r4, 1, 63
-; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    subc r3, r3, r4
 ; CHECK-NEXT:    adde r3, r6, r5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    neg r3, r3
@@ -61,7 +61,7 @@
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    sradi r6, r3, 63
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subfc r3, r4, r3
+; BE-NEXT:    subc r3, r3, r4
 ; BE-NEXT:    rldicl r3, r4, 1, 63
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    adde r3, r3, r6
@@ -73,7 +73,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sradi r6, r3, 63
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    subfc r3, r4, r3
+; LE-NEXT:    subc r3, r3, r4
 ; LE-NEXT:    rldicl r3, r4, 1, 63
 ; LE-NEXT:    adde r3, r3, r6
 ; LE-NEXT:    xori r3, r3, 1
@@ -93,7 +93,7 @@
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    sradi r6, r3, 63
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
-; BE-NEXT:    subfc r3, r4, r3
+; BE-NEXT:    subc r3, r3, r4
 ; BE-NEXT:    rldicl r3, r4, 1, 63
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    adde r3, r3, r6
@@ -106,7 +106,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sradi r6, r3, 63
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    subfc r3, r4, r3
+; LE-NEXT:    subc r3, r3, r4
 ; LE-NEXT:    rldicl r3, r4, 1, 63
 ; LE-NEXT:    adde r3, r3, r6
 ; LE-NEXT:    xori r3, r3, 1
diff --git a/llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll b/llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll
--- a/llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll
+++ b/llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll
@@ -22,7 +22,7 @@
 ; CHECK-NEXT:    cmpwi r29, 1
 ; CHECK-NEXT:    bc 12, lt, .LBB0_3
 ; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    cmpwi cr0, r4, 11
+; CHECK-NEXT:    cmpwi r4, 11
 ; CHECK-NEXT:    bc 12, lt, .LBB0_3
 ; CHECK-NEXT:    .p2align 5
 ; CHECK-NEXT:  .LBB0_2: # %for.body.us
diff --git a/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll b/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll
--- a/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll
+++ b/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll
@@ -5,7 +5,7 @@
 ; CHECK-LABEL: trunc_srl_load:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz 4, 2(0)
-; CHECK-NEXT:    cmplw 0, 4, 3
+; CHECK-NEXT:    cmplw 4, 3
 ; CHECK-NEXT:    ble 0, .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %exit
 ; CHECK-NEXT:  .LBB0_2: # %cond.false
diff --git a/llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll b/llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
--- a/llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
+++ b/llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
@@ -16,11 +16,11 @@
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    xscvuxddp f0, f0
 ; P9BE-NEXT:    xscvuxddp f1, f1
@@ -31,11 +31,11 @@
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    li r3, 0
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r3, r3, 16
 ; P9LE-NEXT:    mtfprwz f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r3, r3, 16
 ; P9LE-NEXT:    mtfprwz f1, r3
 ; P9LE-NEXT:    xscvuxddp f0, f0
 ; P9LE-NEXT:    xscvuxddp f1, f1
@@ -47,8 +47,8 @@
 ; P8BE-NEXT:    mfvsrd r3, v2
 ; P8BE-NEXT:    rldicl r4, r3, 16, 48
 ; P8BE-NEXT:    rldicl r3, r3, 32, 48
-; P8BE-NEXT:    rlwinm r4, r4, 0, 16, 31
-; P8BE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; P8BE-NEXT:    clrlwi r4, r4, 16
+; P8BE-NEXT:    clrlwi r3, r3, 16
 ; P8BE-NEXT:    mtfprwz f0, r4
 ; P8BE-NEXT:    mtfprwz f1, r3
 ; P8BE-NEXT:    xscvuxddp f0, f0
@@ -59,11 +59,11 @@
 ; P8LE-LABEL: test1:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    xxswapd vs0, v2
-; P8LE-NEXT:    mfvsrd r3, f0
+; P8LE-NEXT:    mffprd r3, f0
 ; P8LE-NEXT:    clrldi r4, r3, 48
 ; P8LE-NEXT:    rldicl r3, r3, 48, 48
-; P8LE-NEXT:    rlwinm r4, r4, 0, 16, 31
-; P8LE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; P8LE-NEXT:    clrlwi r4, r4, 16
+; P8LE-NEXT:    clrlwi r3, r3, 16
 ; P8LE-NEXT:    mtfprwz f0, r4
 ; P8LE-NEXT:    mtfprwz f1, r3
 ; P8LE-NEXT:    xscvuxddp f0, f0
@@ -104,7 +104,7 @@
 ; P8BE-NEXT:    xxsldwi vs0, v2, v2, 3
 ; P8BE-NEXT:    mfvsrwz r4, v3
 ; P8BE-NEXT:    mtfprwz f1, r4
-; P8BE-NEXT:    mfvsrwz r3, f0
+; P8BE-NEXT:    mffprwz r3, f0
 ; P8BE-NEXT:    xscvuxddp f1, f1
 ; P8BE-NEXT:    mtfprwz f0, r3
 ; P8BE-NEXT:    xscvuxddp f0, f0
@@ -115,8 +115,8 @@
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    xxsldwi vs1, v3, v3, 1
-; P8LE-NEXT:    mfvsrwz r3, f0
-; P8LE-NEXT:    mfvsrwz r4, f1
+; P8LE-NEXT:    mffprwz r3, f0
+; P8LE-NEXT:    mffprwz r4, f1
 ; P8LE-NEXT:    mtfprwz f0, r3
 ; P8LE-NEXT:    mtfprwz f1, r4
 ; P8LE-NEXT:    xscvuxddp f0, f0
diff --git a/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll b/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
--- a/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
+++ b/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
@@ -22,7 +22,7 @@
 ; P9LE-NEXT:    rldicl r4, r4, 27, 37
 ; P9LE-NEXT:    mulli r4, r4, 98
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
@@ -33,7 +33,7 @@
 ; P9LE-NEXT:    mulli r4, r4, 1003
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r4, r3, 30, 18, 31
@@ -42,10 +42,10 @@
 ; P9LE-NEXT:    mulli r4, r4, 124
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 0
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    lis r6, 22765
 ; P9LE-NEXT:    ori r6, r6, 8969
 ; P9LE-NEXT:    vmrglh v3, v4, v3
@@ -59,7 +59,7 @@
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    vmrglh v2, v4, v2
 ; P9LE-NEXT:    vmrglw v2, v3, v2
@@ -69,7 +69,7 @@
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    lis r5, 16727
 ; P9BE-NEXT:    ori r5, r5, 2287
 ; P9BE-NEXT:    clrldi r4, r3, 32
@@ -83,7 +83,7 @@
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r5
 ; P9BE-NEXT:    lis r5, 8456
@@ -108,7 +108,7 @@
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r5
 ; P9BE-NEXT:    rldicl r4, r4, 32, 32
@@ -131,10 +131,10 @@
 ; P8LE-NEXT:    lis r8, 21399
 ; P8LE-NEXT:    ori r3, r3, 8969
 ; P8LE-NEXT:    ori r8, r8, 33437
-; P8LE-NEXT:    mfvsrd r4, f0
+; P8LE-NEXT:    mffprd r4, f0
 ; P8LE-NEXT:    clrldi r5, r4, 48
 ; P8LE-NEXT:    rldicl r9, r4, 32, 48
-; P8LE-NEXT:    rlwinm r6, r5, 0, 16, 31
+; P8LE-NEXT:    clrlwi r6, r5, 16
 ; P8LE-NEXT:    rldicl r10, r4, 16, 48
 ; P8LE-NEXT:    rlwinm r11, r9, 0, 16, 31
 ; P8LE-NEXT:    clrldi r7, r6, 32
@@ -163,13 +163,13 @@
 ; P8LE-NEXT:    mulli r8, r8, 124
 ; P8LE-NEXT:    subf r7, r7, r9
 ; P8LE-NEXT:    subf r6, r6, r10
-; P8LE-NEXT:    mtvsrd f0, r7
+; P8LE-NEXT:    mtfprd f0, r7
 ; P8LE-NEXT:    subf r3, r3, r5
 ; P8LE-NEXT:    subf r4, r8, r4
-; P8LE-NEXT:    mtvsrd f1, r6
-; P8LE-NEXT:    mtvsrd f2, r3
+; P8LE-NEXT:    mtfprd f1, r6
+; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    mtvsrd f3, r4
+; P8LE-NEXT:    mtfprd f3, r4
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    xxswapd v4, vs2
 ; P8LE-NEXT:    xxswapd v5, vs3
@@ -187,11 +187,11 @@
 ; P8BE-NEXT:    ori r9, r9, 2287
 ; P8BE-NEXT:    rldicl r5, r4, 16, 48
 ; P8BE-NEXT:    clrldi r6, r4, 48
-; P8BE-NEXT:    rlwinm r5, r5, 0, 16, 31
+; P8BE-NEXT:    clrlwi r5, r5, 16
 ; P8BE-NEXT:    rldicl r7, r4, 48, 48
-; P8BE-NEXT:    rlwinm r6, r6, 0, 16, 31
+; P8BE-NEXT:    clrlwi r6, r6, 16
 ; P8BE-NEXT:    clrldi r8, r5, 32
-; P8BE-NEXT:    rlwinm r7, r7, 0, 16, 31
+; P8BE-NEXT:    clrlwi r7, r7, 16
 ; P8BE-NEXT:    mulld r3, r8, r3
 ; P8BE-NEXT:    lis r8, 21399
 ; P8BE-NEXT:    clrldi r10, r6, 32
@@ -204,7 +204,7 @@
 ; P8BE-NEXT:    ori r10, r10, 16913
 ; P8BE-NEXT:    rlwinm r11, r4, 30, 18, 31
 ; P8BE-NEXT:    rldicl r3, r3, 32, 32
-; P8BE-NEXT:    rlwinm r4, r4, 0, 16, 31
+; P8BE-NEXT:    clrlwi r4, r4, 16
 ; P8BE-NEXT:    mulld r10, r11, r10
 ; P8BE-NEXT:    subf r11, r3, r5
 ; P8BE-NEXT:    srwi r11, r11, 1
@@ -242,7 +242,7 @@
 ; P9LE:       # %bb.0:
 ; P9LE-NEXT:    li r3, 0
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    lis r6, 22765
 ; P9LE-NEXT:    ori r6, r6, 8969
 ; P9LE-NEXT:    clrldi r5, r4, 32
@@ -254,10 +254,10 @@
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    clrldi r5, r4, 32
 ; P9LE-NEXT:    mulld r5, r5, r6
 ; P9LE-NEXT:    rldicl r5, r5, 32, 32
@@ -268,10 +268,10 @@
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    clrldi r5, r4, 32
 ; P9LE-NEXT:    mulld r5, r5, r6
 ; P9LE-NEXT:    rldicl r5, r5, 32, 32
@@ -282,10 +282,10 @@
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    clrldi r5, r4, 32
 ; P9LE-NEXT:    mulld r5, r5, r6
 ; P9LE-NEXT:    rldicl r5, r5, 32, 32
@@ -297,7 +297,7 @@
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    vmrglh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v2, v3
@@ -307,7 +307,7 @@
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    lis r5, 22765
 ; P9BE-NEXT:    ori r5, r5, 8969
 ; P9BE-NEXT:    clrldi r4, r3, 32
@@ -323,7 +323,7 @@
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r5
 ; P9BE-NEXT:    rldicl r4, r4, 32, 32
@@ -337,7 +337,7 @@
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r5
 ; P9BE-NEXT:    rldicl r4, r4, 32, 32
@@ -352,7 +352,7 @@
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r5
 ; P9BE-NEXT:    rldicl r4, r4, 32, 32
@@ -375,16 +375,16 @@
 ; P8LE-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; P8LE-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; P8LE-NEXT:    ori r4, r4, 8969
-; P8LE-NEXT:    mfvsrd r5, f0
+; P8LE-NEXT:    mffprd r5, f0
 ; P8LE-NEXT:    clrldi r3, r5, 48
 ; P8LE-NEXT:    rldicl r6, r5, 48, 48
-; P8LE-NEXT:    rlwinm r8, r3, 0, 16, 31
+; P8LE-NEXT:    clrlwi r8, r3, 16
 ; P8LE-NEXT:    rldicl r7, r5, 32, 48
-; P8LE-NEXT:    rlwinm r9, r6, 0, 16, 31
+; P8LE-NEXT:    clrlwi r9, r6, 16
 ; P8LE-NEXT:    rldicl r5, r5, 16, 48
 ; P8LE-NEXT:    clrldi r11, r8, 32
-; P8LE-NEXT:    rlwinm r10, r7, 0, 16, 31
-; P8LE-NEXT:    rlwinm r12, r5, 0, 16, 31
+; P8LE-NEXT:    clrlwi r10, r7, 16
+; P8LE-NEXT:    clrlwi r12, r5, 16
 ; P8LE-NEXT:    mulld r11, r11, r4
 ; P8LE-NEXT:    clrldi r0, r9, 32
 ; P8LE-NEXT:    clrldi r30, r10, 32
@@ -420,13 +420,13 @@
 ; P8LE-NEXT:    mulli r4, r4, 95
 ; P8LE-NEXT:    subf r3, r8, r3
 ; P8LE-NEXT:    subf r6, r9, r6
-; P8LE-NEXT:    mtvsrd f0, r3
+; P8LE-NEXT:    mtfprd f0, r3
 ; P8LE-NEXT:    subf r3, r10, r7
 ; P8LE-NEXT:    subf r4, r4, r5
-; P8LE-NEXT:    mtvsrd f1, r6
-; P8LE-NEXT:    mtvsrd f2, r3
+; P8LE-NEXT:    mtfprd f1, r6
+; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    mtvsrd f3, r4
+; P8LE-NEXT:    mtfprd f3, r4
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    xxswapd v4, vs2
 ; P8LE-NEXT:    xxswapd v5, vs3
@@ -442,15 +442,15 @@
 ; P8BE-NEXT:    ori r3, r3, 8969
 ; P8BE-NEXT:    clrldi r5, r4, 48
 ; P8BE-NEXT:    rldicl r6, r4, 48, 48
-; P8BE-NEXT:    rlwinm r5, r5, 0, 16, 31
+; P8BE-NEXT:    clrlwi r5, r5, 16
 ; P8BE-NEXT:    rldicl r7, r4, 32, 48
-; P8BE-NEXT:    rlwinm r6, r6, 0, 16, 31
+; P8BE-NEXT:    clrlwi r6, r6, 16
 ; P8BE-NEXT:    clrldi r8, r5, 32
 ; P8BE-NEXT:    rldicl r4, r4, 16, 48
-; P8BE-NEXT:    rlwinm r7, r7, 0, 16, 31
+; P8BE-NEXT:    clrlwi r7, r7, 16
 ; P8BE-NEXT:    clrldi r9, r6, 32
 ; P8BE-NEXT:    mulld r8, r8, r3
-; P8BE-NEXT:    rlwinm r4, r4, 0, 16, 31
+; P8BE-NEXT:    clrlwi r4, r4, 16
 ; P8BE-NEXT:    clrldi r10, r7, 32
 ; P8BE-NEXT:    mulld r9, r9, r3
 ; P8BE-NEXT:    clrldi r11, r4, 32
@@ -507,7 +507,7 @@
 ; P9LE:       # %bb.0:
 ; P9LE-NEXT:    li r3, 0
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    lis r6, 22765
 ; P9LE-NEXT:    ori r6, r6, 8969
 ; P9LE-NEXT:    clrldi r5, r4, 32
@@ -519,10 +519,10 @@
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r5, r4, 95
 ; P9LE-NEXT:    subf r3, r5, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r5, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r5, r3, 16
 ; P9LE-NEXT:    clrldi r7, r5, 32
 ; P9LE-NEXT:    mulld r7, r7, r6
 ; P9LE-NEXT:    rldicl r7, r7, 32, 32
@@ -533,10 +533,10 @@
 ; P9LE-NEXT:    mulli r7, r5, 95
 ; P9LE-NEXT:    subf r3, r7, r3
 ; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r7, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r7, r3, 16
 ; P9LE-NEXT:    clrldi r8, r7, 32
 ; P9LE-NEXT:    mulld r8, r8, r6
 ; P9LE-NEXT:    rldicl r8, r8, 32, 32
@@ -547,10 +547,10 @@
 ; P9LE-NEXT:    mulli r8, r7, 95
 ; P9LE-NEXT:    subf r3, r8, r3
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r8, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r8, r3, 16
 ; P9LE-NEXT:    clrldi r9, r8, 32
 ; P9LE-NEXT:    mulld r6, r9, r6
 ; P9LE-NEXT:    rldicl r6, r6, 32, 32
@@ -562,18 +562,18 @@
 ; P9LE-NEXT:    subf r3, r8, r3
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
-; P9LE-NEXT:    mtvsrd f0, r4
+; P9LE-NEXT:    mtfprd f0, r4
 ; P9LE-NEXT:    vmrglh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r5
+; P9LE-NEXT:    mtfprd f0, r5
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r7
+; P9LE-NEXT:    mtfprd f0, r7
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r6
+; P9LE-NEXT:    mtfprd f0, r6
 ; P9LE-NEXT:    xxswapd v5, vs0
 ; P9LE-NEXT:    vmrglh v4, v5, v4
 ; P9LE-NEXT:    vmrglw v3, v4, v3
@@ -584,7 +584,7 @@
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r4, r3, 0, 16, 31
+; P9BE-NEXT:    clrlwi r4, r3, 16
 ; P9BE-NEXT:    lis r6, 22765
 ; P9BE-NEXT:    ori r6, r6, 8969
 ; P9BE-NEXT:    clrldi r5, r4, 32
@@ -600,7 +600,7 @@
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r5, r3, 0, 16, 31
+; P9BE-NEXT:    clrlwi r5, r3, 16
 ; P9BE-NEXT:    clrldi r7, r5, 32
 ; P9BE-NEXT:    mulld r7, r7, r6
 ; P9BE-NEXT:    rldicl r7, r7, 32, 32
@@ -614,7 +614,7 @@
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r7, r3, 0, 16, 31
+; P9BE-NEXT:    clrlwi r7, r3, 16
 ; P9BE-NEXT:    clrldi r8, r7, 32
 ; P9BE-NEXT:    mulld r8, r8, r6
 ; P9BE-NEXT:    rldicl r8, r8, 32, 32
@@ -629,7 +629,7 @@
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    clrldi r8, r3, 32
 ; P9BE-NEXT:    mulld r6, r8, r6
 ; P9BE-NEXT:    rldicl r6, r6, 32, 32
@@ -664,16 +664,16 @@
 ; P8LE-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; P8LE-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; P8LE-NEXT:    ori r5, r5, 8969
-; P8LE-NEXT:    mfvsrd r6, f0
+; P8LE-NEXT:    mffprd r6, f0
 ; P8LE-NEXT:    clrldi r3, r6, 48
 ; P8LE-NEXT:    rldicl r4, r6, 48, 48
 ; P8LE-NEXT:    rldicl r7, r6, 32, 48
-; P8LE-NEXT:    rlwinm r8, r3, 0, 16, 31
-; P8LE-NEXT:    rlwinm r9, r4, 0, 16, 31
+; P8LE-NEXT:    clrlwi r8, r3, 16
+; P8LE-NEXT:    clrlwi r9, r4, 16
 ; P8LE-NEXT:    rldicl r6, r6, 16, 48
-; P8LE-NEXT:    rlwinm r10, r7, 0, 16, 31
+; P8LE-NEXT:    clrlwi r10, r7, 16
 ; P8LE-NEXT:    clrldi r11, r8, 32
-; P8LE-NEXT:    rlwinm r12, r6, 0, 16, 31
+; P8LE-NEXT:    clrlwi r12, r6, 16
 ; P8LE-NEXT:    clrldi r0, r9, 32
 ; P8LE-NEXT:    clrldi r30, r10, 32
 ; P8LE-NEXT:    mulld r11, r11, r5
@@ -703,26 +703,26 @@
 ; P8LE-NEXT:    mulli r12, r8, 95
 ; P8LE-NEXT:    srwi r10, r10, 6
 ; P8LE-NEXT:    add r5, r11, r5
-; P8LE-NEXT:    mtvsrd f0, r8
+; P8LE-NEXT:    mtfprd f0, r8
 ; P8LE-NEXT:    mulli r8, r9, 95
-; P8LE-NEXT:    mtvsrd f1, r9
+; P8LE-NEXT:    mtfprd f1, r9
 ; P8LE-NEXT:    mulli r9, r10, 95
 ; P8LE-NEXT:    srwi r5, r5, 6
-; P8LE-NEXT:    mtvsrd f3, r5
+; P8LE-NEXT:    mtfprd f3, r5
 ; P8LE-NEXT:    mulli r5, r5, 95
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    mtvsrd f2, r10
+; P8LE-NEXT:    mtfprd f2, r10
 ; P8LE-NEXT:    subf r3, r12, r3
 ; P8LE-NEXT:    xxswapd v6, vs3
-; P8LE-NEXT:    mtvsrd f0, r3
+; P8LE-NEXT:    mtfprd f0, r3
 ; P8LE-NEXT:    subf r3, r9, r7
 ; P8LE-NEXT:    subf r4, r8, r4
 ; P8LE-NEXT:    xxswapd v1, vs2
-; P8LE-NEXT:    mtvsrd f4, r3
+; P8LE-NEXT:    mtfprd f4, r3
 ; P8LE-NEXT:    subf r3, r5, r6
-; P8LE-NEXT:    mtvsrd f1, r4
-; P8LE-NEXT:    mtvsrd f5, r3
+; P8LE-NEXT:    mtfprd f1, r4
+; P8LE-NEXT:    mtfprd f5, r3
 ; P8LE-NEXT:    xxswapd v5, vs4
 ; P8LE-NEXT:    vmrglh v2, v3, v2
 ; P8LE-NEXT:    xxswapd v3, vs0
@@ -744,13 +744,13 @@
 ; P8BE-NEXT:    ori r5, r5, 8969
 ; P8BE-NEXT:    clrldi r3, r6, 48
 ; P8BE-NEXT:    rldicl r4, r6, 48, 48
-; P8BE-NEXT:    rlwinm r8, r3, 0, 16, 31
+; P8BE-NEXT:    clrlwi r8, r3, 16
 ; P8BE-NEXT:    rldicl r7, r6, 32, 48
-; P8BE-NEXT:    rlwinm r9, r4, 0, 16, 31
+; P8BE-NEXT:    clrlwi r9, r4, 16
 ; P8BE-NEXT:    rldicl r6, r6, 16, 48
 ; P8BE-NEXT:    clrldi r11, r8, 32
-; P8BE-NEXT:    rlwinm r10, r7, 0, 16, 31
-; P8BE-NEXT:    rlwinm r6, r6, 0, 16, 31
+; P8BE-NEXT:    clrlwi r10, r7, 16
+; P8BE-NEXT:    clrlwi r6, r6, 16
 ; P8BE-NEXT:    clrldi r12, r9, 32
 ; P8BE-NEXT:    mulld r11, r11, r5
 ; P8BE-NEXT:    clrldi r0, r10, 32
@@ -823,16 +823,16 @@
 ; P9LE:       # %bb.0:
 ; P9LE-NEXT:    li r3, 0
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r3, r3, 0, 26, 31
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    clrlwi r3, r3, 26
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r3, r3, 0, 27, 31
+; P9LE-NEXT:    clrlwi r3, r3, 27
 ; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    lis r6, 22765
 ; P9LE-NEXT:    ori r6, r6, 8969
 ; P9LE-NEXT:    xxswapd v4, vs0
@@ -846,12 +846,12 @@
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r3, r3, 0, 29, 31
+; P9LE-NEXT:    clrlwi r3, r3, 29
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    vmrglh v2, v4, v2
 ; P9LE-NEXT:    vmrglw v2, v2, v3
@@ -861,17 +861,17 @@
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r3, r3, 0, 27, 31
+; P9BE-NEXT:    clrlwi r3, r3, 27
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r3, r3, 0, 26, 31
+; P9BE-NEXT:    clrlwi r3, r3, 26
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    lis r5, 22765
 ; P9BE-NEXT:    ori r5, r5, 8969
 ; P9BE-NEXT:    vmrghh v3, v4, v3
@@ -888,7 +888,7 @@
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r3, r3, 0, 29, 31
+; P9BE-NEXT:    clrlwi r3, r3, 29
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    vmrghh v2, v2, v4
@@ -900,14 +900,14 @@
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 22765
 ; P8LE-NEXT:    ori r3, r3, 8969
-; P8LE-NEXT:    mfvsrd r4, f0
+; P8LE-NEXT:    mffprd r4, f0
 ; P8LE-NEXT:    rldicl r5, r4, 16, 48
-; P8LE-NEXT:    rlwinm r6, r5, 0, 16, 31
+; P8LE-NEXT:    clrlwi r6, r5, 16
 ; P8LE-NEXT:    clrldi r7, r6, 32
 ; P8LE-NEXT:    mulld r3, r7, r3
 ; P8LE-NEXT:    rldicl r7, r4, 48, 48
-; P8LE-NEXT:    rlwinm r7, r7, 0, 27, 31
-; P8LE-NEXT:    mtvsrd f1, r7
+; P8LE-NEXT:    clrlwi r7, r7, 27
+; P8LE-NEXT:    mtfprd f1, r7
 ; P8LE-NEXT:    rldicl r3, r3, 32, 32
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    subf r6, r3, r6
@@ -916,15 +916,15 @@
 ; P8LE-NEXT:    clrldi r6, r4, 48
 ; P8LE-NEXT:    srwi r3, r3, 6
 ; P8LE-NEXT:    rldicl r4, r4, 32, 48
-; P8LE-NEXT:    rlwinm r6, r6, 0, 26, 31
+; P8LE-NEXT:    clrlwi r6, r6, 26
 ; P8LE-NEXT:    mulli r3, r3, 95
-; P8LE-NEXT:    rlwinm r4, r4, 0, 29, 31
-; P8LE-NEXT:    mtvsrd f0, r6
-; P8LE-NEXT:    mtvsrd f3, r4
+; P8LE-NEXT:    clrlwi r4, r4, 29
+; P8LE-NEXT:    mtfprd f0, r6
+; P8LE-NEXT:    mtfprd f3, r4
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    xxswapd v5, vs3
 ; P8LE-NEXT:    subf r3, r3, r5
-; P8LE-NEXT:    mtvsrd f2, r3
+; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    vmrglh v2, v3, v2
 ; P8LE-NEXT:    xxswapd v4, vs2
 ; P8LE-NEXT:    vmrglh v3, v4, v5
@@ -938,8 +938,8 @@
 ; P8BE-NEXT:    ori r3, r3, 8969
 ; P8BE-NEXT:    clrldi r5, r4, 48
 ; P8BE-NEXT:    rldicl r7, r4, 16, 48
-; P8BE-NEXT:    rlwinm r5, r5, 0, 16, 31
-; P8BE-NEXT:    rlwinm r7, r7, 0, 26, 31
+; P8BE-NEXT:    clrlwi r5, r5, 16
+; P8BE-NEXT:    clrlwi r7, r7, 26
 ; P8BE-NEXT:    clrldi r6, r5, 32
 ; P8BE-NEXT:    mulld r3, r6, r3
 ; P8BE-NEXT:    rldicl r3, r3, 32, 32
@@ -949,10 +949,10 @@
 ; P8BE-NEXT:    rldicl r6, r4, 32, 48
 ; P8BE-NEXT:    srwi r3, r3, 6
 ; P8BE-NEXT:    rldicl r4, r4, 48, 48
-; P8BE-NEXT:    rlwinm r6, r6, 0, 27, 31
+; P8BE-NEXT:    clrlwi r6, r6, 27
 ; P8BE-NEXT:    mulli r3, r3, 95
 ; P8BE-NEXT:    sldi r6, r6, 48
-; P8BE-NEXT:    rlwinm r4, r4, 0, 29, 31
+; P8BE-NEXT:    clrlwi r4, r4, 29
 ; P8BE-NEXT:    mtvsrd v2, r6
 ; P8BE-NEXT:    sldi r6, r7, 48
 ; P8BE-NEXT:    sldi r4, r4, 48
@@ -987,7 +987,7 @@
 ; P9LE-NEXT:    rldicl r4, r4, 28, 36
 ; P9LE-NEXT:    mulli r4, r4, 23
 ; P9LE-NEXT:    subf r3, r4, r3
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
@@ -996,7 +996,7 @@
 ; P9LE-NEXT:    mulli r4, r4, 5423
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    xxswapd v3, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r4, r3, 31, 17, 31
@@ -1005,7 +1005,7 @@
 ; P9LE-NEXT:    mulli r4, r4, 654
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    xxswapd v4, vs0
-; P9LE-NEXT:    mtvsrd f0, r3
+; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxlxor v4, v4, v4
@@ -1017,7 +1017,7 @@
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    lis r5, 24749
 ; P9BE-NEXT:    ori r5, r5, 47143
 ; P9BE-NEXT:    clrldi r4, r3, 32
@@ -1034,7 +1034,7 @@
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r6
 ; P9BE-NEXT:    rldicl r4, r4, 28, 36
@@ -1071,7 +1071,7 @@
 ; P8LE-NEXT:    oris r3, r3, 51306
 ; P8LE-NEXT:    ori r5, r5, 17097
 ; P8LE-NEXT:    ori r3, r3, 30865
-; P8LE-NEXT:    mfvsrd r4, f0
+; P8LE-NEXT:    mffprd r4, f0
 ; P8LE-NEXT:    rldicl r6, r4, 32, 48
 ; P8LE-NEXT:    rldicl r7, r4, 16, 48
 ; P8LE-NEXT:    rlwinm r9, r6, 0, 16, 31
@@ -1089,10 +1089,10 @@
 ; P8LE-NEXT:    mulli r3, r3, 654
 ; P8LE-NEXT:    subf r5, r5, r6
 ; P8LE-NEXT:    subf r6, r8, r7
-; P8LE-NEXT:    mtvsrd f0, r5
+; P8LE-NEXT:    mtfprd f0, r5
 ; P8LE-NEXT:    subf r3, r3, r4
-; P8LE-NEXT:    mtvsrd f1, r6
-; P8LE-NEXT:    mtvsrd f2, r3
+; P8LE-NEXT:    mtfprd f1, r6
+; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    xxswapd v4, vs2
@@ -1115,9 +1115,9 @@
 ; P8BE-NEXT:    ori r3, r3, 17097
 ; P8BE-NEXT:    rldicl r4, r4, 48, 48
 ; P8BE-NEXT:    rlwinm r9, r5, 31, 17, 31
-; P8BE-NEXT:    rlwinm r7, r7, 0, 16, 31
-; P8BE-NEXT:    rlwinm r5, r5, 0, 16, 31
-; P8BE-NEXT:    rlwinm r4, r4, 0, 16, 31
+; P8BE-NEXT:    clrlwi r7, r7, 16
+; P8BE-NEXT:    clrlwi r5, r5, 16
+; P8BE-NEXT:    clrlwi r4, r4, 16
 ; P8BE-NEXT:    mulld r6, r9, r6
 ; P8BE-NEXT:    clrldi r9, r7, 32
 ; P8BE-NEXT:    mulld r8, r9, r8
@@ -1255,7 +1255,7 @@
 ; P8LE-NEXT:    sldi r3, r3, 32
 ; P8LE-NEXT:    sldi r4, r4, 32
 ; P8LE-NEXT:    oris r3, r3, 45590
-; P8LE-NEXT:    mfvsrd r7, f0
+; P8LE-NEXT:    mffprd r7, f0
 ; P8LE-NEXT:    sldi r5, r5, 32
 ; P8LE-NEXT:    oris r4, r4, 52170
 ; P8LE-NEXT:    ori r3, r3, 17097
@@ -1277,12 +1277,12 @@
 ; P8LE-NEXT:    mulli r3, r3, 23
 ; P8LE-NEXT:    sub r4, r8, r4
 ; P8LE-NEXT:    sub r5, r6, r5
-; P8LE-NEXT:    mtvsrd f0, r4
+; P8LE-NEXT:    mtfprd f0, r4
 ; P8LE-NEXT:    sub r3, r7, r3
 ; P8LE-NEXT:    li r4, 0
-; P8LE-NEXT:    mtvsrd f1, r5
-; P8LE-NEXT:    mtvsrd f2, r3
-; P8LE-NEXT:    mtvsrd f3, r4
+; P8LE-NEXT:    mtfprd f1, r5
+; P8LE-NEXT:    mtfprd f2, r3
+; P8LE-NEXT:    mtfprd f3, r4
 ; P8LE-NEXT:    xxmrghd v3, vs0, vs2
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs3
 ; P8LE-NEXT:    blr
@@ -1302,10 +1302,10 @@
 ; P8BE-NEXT:    sldi r4, r4, 32
 ; P8BE-NEXT:    oris r3, r3, 45590
 ; P8BE-NEXT:    sldi r5, r5, 32
-; P8BE-NEXT:    mfvsrd r7, f0
+; P8BE-NEXT:    mffprd r7, f0
 ; P8BE-NEXT:    oris r4, r4, 52170
 ; P8BE-NEXT:    ori r3, r3, 17097
-; P8BE-NEXT:    mfvsrd r8, f1
+; P8BE-NEXT:    mffprd r8, f1
 ; P8BE-NEXT:    oris r5, r5, 1603
 ; P8BE-NEXT:    ori r4, r4, 12109
 ; P8BE-NEXT:    mulhdu r3, r6, r3
@@ -1323,13 +1323,13 @@
 ; P8BE-NEXT:    mulli r5, r5, 654
 ; P8BE-NEXT:    mulli r3, r3, 23
 ; P8BE-NEXT:    sub r4, r7, r4
-; P8BE-NEXT:    mtvsrd f0, r4
+; P8BE-NEXT:    mtfprd f0, r4
 ; P8BE-NEXT:    sub r4, r8, r5
 ; P8BE-NEXT:    sub r3, r6, r3
-; P8BE-NEXT:    mtvsrd f1, r4
+; P8BE-NEXT:    mtfprd f1, r4
 ; P8BE-NEXT:    li r4, 0
-; P8BE-NEXT:    mtvsrd f2, r3
-; P8BE-NEXT:    mtvsrd f3, r4
+; P8BE-NEXT:    mtfprd f2, r3
+; P8BE-NEXT:    mtfprd f3, r4
 ; P8BE-NEXT:    xxmrghd v3, vs2, vs0
 ; P8BE-NEXT:    xxmrghd v2, vs3, vs1
 ; P8BE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/vec-min-max.ll b/llvm/test/CodeGen/PowerPC/vec-min-max.ll
--- a/llvm/test/CodeGen/PowerPC/vec-min-max.ll
+++ b/llvm/test/CodeGen/PowerPC/vec-min-max.ll
@@ -246,9 +246,9 @@
 ; CHECK-NEXT:    xxswapd 1, 34
 ; CHECK-NEXT:    cmpld 4, 3
 ; CHECK-NEXT:    cmpd 1, 4, 3
-; CHECK-NEXT:    mfvsrd 3, 0
+; CHECK-NEXT:    mffprd 3, 0
 ; CHECK-NEXT:    crandc 20, 4, 2
-; CHECK-NEXT:    mfvsrd 4, 1
+; CHECK-NEXT:    mffprd 4, 1
 ; CHECK-NEXT:    cmpld 1, 4, 3
 ; CHECK-NEXT:    bc 12, 20, .LBB12_3
 ; CHECK-NEXT:  # %bb.1:
@@ -259,7 +259,7 @@
 ; CHECK-NEXT:  .LBB12_3:
 ; CHECK-NEXT:    xxswapd 0, 34
 ; CHECK-NEXT:    mfvsrd 4, 34
-; CHECK-NEXT:    mfvsrd 3, 0
+; CHECK-NEXT:    mffprd 3, 0
 ; CHECK-NEXT:    blr
 ;
 ; NOP8VEC-LABEL: invalidv1i128:
diff --git a/llvm/test/CodeGen/PowerPC/vec-trunc.ll b/llvm/test/CodeGen/PowerPC/vec-trunc.ll
--- a/llvm/test/CodeGen/PowerPC/vec-trunc.ll
+++ b/llvm/test/CodeGen/PowerPC/vec-trunc.ll
@@ -93,7 +93,7 @@
 ; CHECK-NEXT:    lvx v2, 0, r4
 ; CHECK-NEXT:    vpkuhum v2, v2, v2
 ; CHECK-NEXT:    xxswapd vs0, v2
-; CHECK-NEXT:    mfvsrd r4, f0
+; CHECK-NEXT:    mffprd r4, f0
 ; CHECK-NEXT:    clrldi r4, r4, 48
 ; CHECK-NEXT:    sth r4, 0(r3)
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll b/llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
--- a/llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
@@ -36,7 +36,7 @@
 define <2 x i64> @increment_by_val(<2 x i64> %x, i64 %val) nounwind {
 ; VSX-LABEL: increment_by_val:
 ; VSX:       # %bb.0:
-; VSX-NEXT:    mtvsrd 0, 5
+; VSX-NEXT:    mtfprd 0, 5
 ; VSX-NEXT:    xxspltd 35, 0, 0
 ; VSX-NEXT:    vaddudm 2, 2, 3
 ; VSX-NEXT:    blr
@@ -98,7 +98,7 @@
 define <2 x i64> @decrement_by_val(<2 x i64> %x, i64 %val) nounwind {
 ; VSX-LABEL: decrement_by_val:
 ; VSX:       # %bb.0:
-; VSX-NEXT:    mtvsrd 0, 5
+; VSX-NEXT:    mtfprd 0, 5
 ; VSX-NEXT:    xxspltd 35, 0, 0
 ; VSX-NEXT:    vsubudm 2, 2, 3
 ; VSX-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll b/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
--- a/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
@@ -45,8 +45,8 @@
 define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind {
 ; VSX-LABEL: increment_by_val:
 ; VSX:       # %bb.0:
-; VSX-NEXT:    mtvsrd 0, 6
-; VSX-NEXT:    mtvsrd 1, 5
+; VSX-NEXT:    mtfprd 0, 6
+; VSX-NEXT:    mtfprd 1, 5
 ; VSX-NEXT:    xxmrghd 35, 1, 0
 ; VSX-NEXT:    vadduqm 2, 2, 3
 ; VSX-NEXT:    blr
@@ -96,8 +96,8 @@
 define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind {
 ; VSX-LABEL: decrement_by_val:
 ; VSX:       # %bb.0:
-; VSX-NEXT:    mtvsrd 0, 6
-; VSX-NEXT:    mtvsrd 1, 5
+; VSX-NEXT:    mtfprd 0, 6
+; VSX-NEXT:    mtfprd 1, 5
 ; VSX-NEXT:    xxmrghd 35, 1, 0
 ; VSX-NEXT:    vsubuqm 2, 2, 3
 ; VSX-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll
--- a/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll
@@ -12,37 +12,37 @@
 define i32 @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-P8-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mffprwz r4, f0
+; CHECK-P8-NEXT:    mffprwz r3, f1
+; CHECK-P8-NEXT:    mtfprd f1, r4
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v3, vs1
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs1
 ; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
@@ -52,16 +52,16 @@
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrd f0, r3
+; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    li r3, 0
@@ -89,23 +89,23 @@
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mtvsrd f1, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    mffprwz r3, f1
+; CHECK-P8-NEXT:    mtfprd f1, r3
+; CHECK-P8-NEXT:    mffprwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r4, f2
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mffprwz r3, f3
+; CHECK-P8-NEXT:    mtfprd f2, r4
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    mtvsrd f3, r3
+; CHECK-P8-NEXT:    mtfprd f3, r3
 ; CHECK-P8-NEXT:    xxswapd v3, vs2
 ; CHECK-P8-NEXT:    xxswapd v5, vs3
 ; CHECK-P8-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P8-NEXT:    vmrglh v3, v4, v5
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt:
@@ -113,26 +113,26 @@
 ; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, v2
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 1
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    vmrglh v2, v4, v2
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v3
@@ -144,25 +144,25 @@
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xscvspdpn f0, v2
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    vmrghh v2, v4, v2
@@ -198,34 +198,34 @@
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    mfvsrwz r6, f1
-; CHECK-P8-NEXT:    mfvsrwz r5, f0
-; CHECK-P8-NEXT:    mtvsrd f1, r6
-; CHECK-P8-NEXT:    mtvsrd f0, r5
+; CHECK-P8-NEXT:    mffprwz r4, f4
+; CHECK-P8-NEXT:    mffprwz r6, f1
+; CHECK-P8-NEXT:    mffprwz r5, f0
+; CHECK-P8-NEXT:    mtfprd f1, r6
+; CHECK-P8-NEXT:    mtfprd f0, r5
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
 ; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 1
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    xscvspdpn f0, v2
-; CHECK-P8-NEXT:    mtvsrd f4, r4
+; CHECK-P8-NEXT:    mtfprd f4, r4
 ; CHECK-P8-NEXT:    xscvspdpn f1, vs1
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    mffprwz r4, f2
 ; CHECK-P8-NEXT:    xxswapd v1, vs4
 ; CHECK-P8-NEXT:    vmrglh v2, v4, v3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
+; CHECK-P8-NEXT:    mtfprd f2, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
+; CHECK-P8-NEXT:    mffprwz r4, f5
 ; CHECK-P8-NEXT:    xxswapd v5, vs2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
+; CHECK-P8-NEXT:    mffprwz r3, f0
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mffprwz r3, f1
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    mtvsrd f1, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f3, r4
+; CHECK-P8-NEXT:    mtfprd f1, r3
+; CHECK-P8-NEXT:    mffprwz r3, f3
+; CHECK-P8-NEXT:    mtfprd f3, r4
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v6, vs3
 ; CHECK-P8-NEXT:    xxswapd v0, vs0
 ; CHECK-P8-NEXT:    vmrglh v3, v3, v4
@@ -243,24 +243,24 @@
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    lxv vs0, 16(r3)
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs0, vs0, 3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
@@ -269,24 +269,24 @@
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    vmrglh v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxswapd v5, vs0
@@ -302,13 +302,13 @@
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
@@ -317,16 +317,16 @@
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    vmrghh v2, v3, v2
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
@@ -334,7 +334,7 @@
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
@@ -343,10 +343,10 @@
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    vmrghh v4, v4, v5
@@ -399,56 +399,56 @@
 ; CHECK-P8-NEXT:    xscvdpsxws f6, f6
 ; CHECK-P8-NEXT:    xscvspdpn f12, vs12
 ; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    mffprwz r4, f0
 ; CHECK-P8-NEXT:    xscvspdpn f11, vs11
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    xscvspdpn v2, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f8, f8
-; CHECK-P8-NEXT:    mtvsrd f0, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
+; CHECK-P8-NEXT:    mtfprd f0, r4
+; CHECK-P8-NEXT:    mffprwz r4, f4
 ; CHECK-P8-NEXT:    xscvdpsxws f7, f7
-; CHECK-P8-NEXT:    mfvsrwz r6, f2
+; CHECK-P8-NEXT:    mffprwz r6, f2
 ; CHECK-P8-NEXT:    xscvspdpn f13, vs13
 ; CHECK-P8-NEXT:    xscvspdpn v3, v3
 ; CHECK-P8-NEXT:    xscvdpsxws f10, f10
-; CHECK-P8-NEXT:    mtvsrd f4, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    mtfprd f4, r4
+; CHECK-P8-NEXT:    mffprwz r4, f1
 ; CHECK-P8-NEXT:    xscvdpsxws f9, f9
-; CHECK-P8-NEXT:    mtvsrd f2, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f6
+; CHECK-P8-NEXT:    mtfprd f2, r6
+; CHECK-P8-NEXT:    mffprwz r6, f6
 ; CHECK-P8-NEXT:    xscvdpsxws f12, f12
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
+; CHECK-P8-NEXT:    mtfprd f1, r4
+; CHECK-P8-NEXT:    mffprwz r4, f5
 ; CHECK-P8-NEXT:    xscvdpsxws f11, f11
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f6, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f3
+; CHECK-P8-NEXT:    mtfprd f6, r6
+; CHECK-P8-NEXT:    mffprwz r6, f3
 ; CHECK-P8-NEXT:    xscvdpsxws v2, v2
 ; CHECK-P8-NEXT:    xxswapd v9, vs6
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f8
-; CHECK-P8-NEXT:    mtvsrd f3, r6
+; CHECK-P8-NEXT:    mtfprd f5, r4
+; CHECK-P8-NEXT:    mffprwz r4, f8
+; CHECK-P8-NEXT:    mtfprd f3, r6
 ; CHECK-P8-NEXT:    xxswapd v0, vs5
-; CHECK-P8-NEXT:    mfvsrwz r6, f7
+; CHECK-P8-NEXT:    mffprwz r6, f7
 ; CHECK-P8-NEXT:    xscvdpsxws f13, f13
 ; CHECK-P8-NEXT:    xxswapd v5, vs3
 ; CHECK-P8-NEXT:    xscvdpsxws v3, v3
-; CHECK-P8-NEXT:    mtvsrd f8, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f10
-; CHECK-P8-NEXT:    mtvsrd f7, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f9
-; CHECK-P8-NEXT:    mtvsrd f10, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f12
-; CHECK-P8-NEXT:    mtvsrd f9, r6
+; CHECK-P8-NEXT:    mtfprd f8, r4
+; CHECK-P8-NEXT:    mffprwz r4, f10
+; CHECK-P8-NEXT:    mtfprd f7, r6
+; CHECK-P8-NEXT:    mffprwz r6, f9
+; CHECK-P8-NEXT:    mtfprd f10, r4
+; CHECK-P8-NEXT:    mffprwz r4, f12
+; CHECK-P8-NEXT:    mtfprd f9, r6
 ; CHECK-P8-NEXT:    xxswapd v6, vs10
-; CHECK-P8-NEXT:    mfvsrwz r6, f11
-; CHECK-P8-NEXT:    mtvsrd f12, r4
+; CHECK-P8-NEXT:    mffprwz r6, f11
+; CHECK-P8-NEXT:    mtfprd f12, r4
 ; CHECK-P8-NEXT:    xxswapd v1, vs9
 ; CHECK-P8-NEXT:    mfvsrwz r4, v2
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    mtvsrd f11, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f13
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mtfprd f11, r6
+; CHECK-P8-NEXT:    mffprwz r6, f13
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    xxswapd v7, vs11
 ; CHECK-P8-NEXT:    mfvsrwz r4, v3
 ; CHECK-P8-NEXT:    vmrglh v3, v5, v4
@@ -456,8 +456,8 @@
 ; CHECK-P8-NEXT:    vmrglh v2, v2, v0
 ; CHECK-P8-NEXT:    xxswapd v5, vs8
 ; CHECK-P8-NEXT:    xxswapd v0, vs2
-; CHECK-P8-NEXT:    mtvsrd f13, r6
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mtfprd f13, r6
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v8, vs0
 ; CHECK-P8-NEXT:    vmrglh v4, v5, v4
 ; CHECK-P8-NEXT:    vmrglh v5, v0, v1
@@ -502,14 +502,14 @@
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f4
 ; CHECK-P9-NEXT:    xscvdpsxws f6, f6
-; CHECK-P9-NEXT:    mfvsrwz r5, f5
+; CHECK-P9-NEXT:    mffprwz r5, f5
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f7, f7
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
-; CHECK-P9-NEXT:    mtvsrd f5, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f8
-; CHECK-P9-NEXT:    mtvsrd f8, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f2
+; CHECK-P9-NEXT:    mtfprd f5, r5
+; CHECK-P9-NEXT:    mffprwz r5, f8
+; CHECK-P9-NEXT:    mtfprd f8, r5
+; CHECK-P9-NEXT:    mffprwz r5, f2
 ; CHECK-P9-NEXT:    lxv vs0, 32(r4)
 ; CHECK-P9-NEXT:    xxsldwi vs9, vs0, vs0, 3
 ; CHECK-P9-NEXT:    xxswapd vs10, vs0
@@ -517,40 +517,40 @@
 ; CHECK-P9-NEXT:    xscvspdpn f10, vs10
 ; CHECK-P9-NEXT:    xscvdpsxws f9, f9
 ; CHECK-P9-NEXT:    xscvdpsxws f10, f10
-; CHECK-P9-NEXT:    mtvsrd f2, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f6
+; CHECK-P9-NEXT:    mtfprd f2, r5
+; CHECK-P9-NEXT:    mffprwz r5, f4
+; CHECK-P9-NEXT:    mtfprd f4, r5
+; CHECK-P9-NEXT:    mffprwz r5, f1
+; CHECK-P9-NEXT:    mtfprd f1, r5
+; CHECK-P9-NEXT:    mffprwz r5, f6
 ; CHECK-P9-NEXT:    xxswapd v2, vs2
 ; CHECK-P9-NEXT:    xxswapd v3, vs4
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mtvsrd f6, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f7
+; CHECK-P9-NEXT:    mtfprd f6, r5
+; CHECK-P9-NEXT:    mffprwz r5, f7
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    lxv vs1, 48(r4)
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P9-NEXT:    xxswapd v3, vs5
-; CHECK-P9-NEXT:    mtvsrd f7, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f3
+; CHECK-P9-NEXT:    mtfprd f7, r5
+; CHECK-P9-NEXT:    mffprwz r5, f3
 ; CHECK-P9-NEXT:    vmrglh v3, v3, v4
 ; CHECK-P9-NEXT:    xxswapd v4, vs6
 ; CHECK-P9-NEXT:    xxswapd v5, vs7
-; CHECK-P9-NEXT:    mtvsrd f3, r5
+; CHECK-P9-NEXT:    mtfprd f3, r5
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    xxswapd v0, vs3
 ; CHECK-P9-NEXT:    vmrglh v4, v5, v4
 ; CHECK-P9-NEXT:    xxswapd v5, vs8
 ; CHECK-P9-NEXT:    vmrglh v5, v5, v0
-; CHECK-P9-NEXT:    mfvsrwz r4, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r4
-; CHECK-P9-NEXT:    mfvsrwz r4, f0
+; CHECK-P9-NEXT:    mffprwz r4, f2
+; CHECK-P9-NEXT:    mtfprd f2, r4
+; CHECK-P9-NEXT:    mffprwz r4, f0
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    vmrglw v3, v5, v4
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xxmrgld vs2, v3, v2
@@ -558,36 +558,36 @@
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs1, vs1, 3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mffprwz r4, f0
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mffprwz r4, f0
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    vmrglh v2, v4, v2
 ; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mffprwz r4, f0
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs1, vs1, 1
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r5, f9
-; CHECK-P9-NEXT:    mtvsrd f9, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f10
-; CHECK-P9-NEXT:    mtvsrd f10, r5
+; CHECK-P9-NEXT:    mffprwz r5, f9
+; CHECK-P9-NEXT:    mtfprd f9, r5
+; CHECK-P9-NEXT:    mffprwz r5, f10
+; CHECK-P9-NEXT:    mtfprd f10, r5
 ; CHECK-P9-NEXT:    xxswapd v0, vs9
 ; CHECK-P9-NEXT:    xxswapd v1, vs10
 ; CHECK-P9-NEXT:    vmrglh v0, v1, v0
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v0
 ; CHECK-P9-NEXT:    stxv vs2, 0(r3)
-; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mffprwz r4, f0
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    xxswapd v5, vs0
 ; CHECK-P9-NEXT:    vmrglh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
@@ -604,14 +604,14 @@
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mfvsrwz r5, f2
+; CHECK-BE-NEXT:    mffprwz r5, f2
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    mtvsrd v2, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f3
+; CHECK-BE-NEXT:    mffprwz r5, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f4
 ; CHECK-BE-NEXT:    lxv vs0, 0(r4)
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs0, vs0, 3
@@ -619,22 +619,22 @@
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    mtvsrd v3, r5
 ; CHECK-BE-NEXT:    vmrghh v2, v3, v2
-; CHECK-BE-NEXT:    mfvsrwz r5, f3
+; CHECK-BE-NEXT:    mffprwz r5, f3
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    mtvsrd v3, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f1
+; CHECK-BE-NEXT:    mffprwz r5, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    mtvsrd v4, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f2
+; CHECK-BE-NEXT:    mffprwz r5, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    vmrghh v3, v3, v4
 ; CHECK-BE-NEXT:    mtvsrd v4, r5
 ; CHECK-BE-NEXT:    vmrghw v2, v3, v2
-; CHECK-BE-NEXT:    mfvsrwz r5, f1
+; CHECK-BE-NEXT:    mffprwz r5, f1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
@@ -643,11 +643,11 @@
 ; CHECK-BE-NEXT:    mtvsrd v5, r5
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    vmrghh v4, v5, v4
-; CHECK-BE-NEXT:    mfvsrwz r5, f1
+; CHECK-BE-NEXT:    mffprwz r5, f1
 ; CHECK-BE-NEXT:    lxv vs1, 48(r4)
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    mtvsrd v5, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f0
+; CHECK-BE-NEXT:    mffprwz r5, f0
 ; CHECK-BE-NEXT:    lxv vs0, 32(r4)
 ; CHECK-BE-NEXT:    xscvspdpn f5, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
@@ -663,26 +663,26 @@
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    vmrghw v3, v5, v4
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mfvsrwz r4, f5
+; CHECK-BE-NEXT:    mffprwz r4, f5
 ; CHECK-BE-NEXT:    xxmrghd vs4, v3, v2
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    mtvsrd v2, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f2
+; CHECK-BE-NEXT:    mffprwz r4, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    stxv vs4, 0(r3)
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    mtvsrd v3, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f3
+; CHECK-BE-NEXT:    mffprwz r4, f3
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    mtvsrd v4, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f1
+; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    vmrghh v3, v4, v3
 ; CHECK-BE-NEXT:    mtvsrd v4, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f1
+; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
@@ -690,7 +690,7 @@
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mtvsrd v3, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f1
+; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
@@ -699,10 +699,10 @@
 ; CHECK-BE-NEXT:    mtvsrd v4, r4
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mfvsrwz r4, f1
+; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    mtvsrd v4, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f0
+; CHECK-BE-NEXT:    mffprwz r4, f0
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    mtvsrd v5, r4
 ; CHECK-BE-NEXT:    vmrghh v4, v4, v5
@@ -720,37 +720,37 @@
 define i32 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-P8-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mffprwz r4, f0
+; CHECK-P8-NEXT:    mffprwz r3, f1
+; CHECK-P8-NEXT:    mtfprd f1, r4
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v3, vs1
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs1
 ; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
@@ -760,16 +760,16 @@
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrd f0, r3
+; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    li r3, 0
@@ -797,23 +797,23 @@
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mtvsrd f1, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    mffprwz r3, f1
+; CHECK-P8-NEXT:    mtfprd f1, r3
+; CHECK-P8-NEXT:    mffprwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r4, f2
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mffprwz r3, f3
+; CHECK-P8-NEXT:    mtfprd f2, r4
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    mtvsrd f3, r3
+; CHECK-P8-NEXT:    mtfprd f3, r3
 ; CHECK-P8-NEXT:    xxswapd v3, vs2
 ; CHECK-P8-NEXT:    xxswapd v5, vs3
 ; CHECK-P8-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P8-NEXT:    vmrglh v3, v4, v5
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt_signed:
@@ -821,26 +821,26 @@
 ; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, v2
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 1
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    vmrglh v2, v4, v2
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v3
@@ -852,25 +852,25 @@
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xscvspdpn f0, v2
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    vmrghh v2, v4, v2
@@ -906,34 +906,34 @@
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    mfvsrwz r6, f1
-; CHECK-P8-NEXT:    mfvsrwz r5, f0
-; CHECK-P8-NEXT:    mtvsrd f1, r6
-; CHECK-P8-NEXT:    mtvsrd f0, r5
+; CHECK-P8-NEXT:    mffprwz r4, f4
+; CHECK-P8-NEXT:    mffprwz r6, f1
+; CHECK-P8-NEXT:    mffprwz r5, f0
+; CHECK-P8-NEXT:    mtfprd f1, r6
+; CHECK-P8-NEXT:    mtfprd f0, r5
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
 ; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 1
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    xscvspdpn f0, v2
-; CHECK-P8-NEXT:    mtvsrd f4, r4
+; CHECK-P8-NEXT:    mtfprd f4, r4
 ; CHECK-P8-NEXT:    xscvspdpn f1, vs1
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    mffprwz r4, f2
 ; CHECK-P8-NEXT:    xxswapd v1, vs4
 ; CHECK-P8-NEXT:    vmrglh v2, v4, v3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
+; CHECK-P8-NEXT:    mtfprd f2, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
+; CHECK-P8-NEXT:    mffprwz r4, f5
 ; CHECK-P8-NEXT:    xxswapd v5, vs2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
+; CHECK-P8-NEXT:    mffprwz r3, f0
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mffprwz r3, f1
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    mtvsrd f1, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f3, r4
+; CHECK-P8-NEXT:    mtfprd f1, r3
+; CHECK-P8-NEXT:    mffprwz r3, f3
+; CHECK-P8-NEXT:    mtfprd f3, r4
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v6, vs3
 ; CHECK-P8-NEXT:    xxswapd v0, vs0
 ; CHECK-P8-NEXT:    vmrglh v3, v3, v4
@@ -951,24 +951,24 @@
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    lxv vs0, 16(r3)
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs0, vs0, 3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
@@ -977,24 +977,24 @@
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    vmrglh v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxswapd v5, vs0
@@ -1010,13 +1010,13 @@
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
@@ -1025,16 +1025,16 @@
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    vmrghh v2, v3, v2
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
@@ -1042,7 +1042,7 @@
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
@@ -1051,10 +1051,10 @@
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    vmrghh v4, v4, v5
@@ -1107,56 +1107,56 @@
 ; CHECK-P8-NEXT:    xscvdpsxws f6, f6
 ; CHECK-P8-NEXT:    xscvspdpn f12, vs12
 ; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    mffprwz r4, f0
 ; CHECK-P8-NEXT:    xscvspdpn f11, vs11
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    xscvspdpn v2, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f8, f8
-; CHECK-P8-NEXT:    mtvsrd f0, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
+; CHECK-P8-NEXT:    mtfprd f0, r4
+; CHECK-P8-NEXT:    mffprwz r4, f4
 ; CHECK-P8-NEXT:    xscvdpsxws f7, f7
-; CHECK-P8-NEXT:    mfvsrwz r6, f2
+; CHECK-P8-NEXT:    mffprwz r6, f2
 ; CHECK-P8-NEXT:    xscvspdpn f13, vs13
 ; CHECK-P8-NEXT:    xscvspdpn v3, v3
 ; CHECK-P8-NEXT:    xscvdpsxws f10, f10
-; CHECK-P8-NEXT:    mtvsrd f4, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    mtfprd f4, r4
+; CHECK-P8-NEXT:    mffprwz r4, f1
 ; CHECK-P8-NEXT:    xscvdpsxws f9, f9
-; CHECK-P8-NEXT:    mtvsrd f2, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f6
+; CHECK-P8-NEXT:    mtfprd f2, r6
+; CHECK-P8-NEXT:    mffprwz r6, f6
 ; CHECK-P8-NEXT:    xscvdpsxws f12, f12
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
+; CHECK-P8-NEXT:    mtfprd f1, r4
+; CHECK-P8-NEXT:    mffprwz r4, f5
 ; CHECK-P8-NEXT:    xscvdpsxws f11, f11
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f6, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f3
+; CHECK-P8-NEXT:    mtfprd f6, r6
+; CHECK-P8-NEXT:    mffprwz r6, f3
 ; CHECK-P8-NEXT:    xscvdpsxws v2, v2
 ; CHECK-P8-NEXT:    xxswapd v9, vs6
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f8
-; CHECK-P8-NEXT:    mtvsrd f3, r6
+; CHECK-P8-NEXT:    mtfprd f5, r4
+; CHECK-P8-NEXT:    mffprwz r4, f8
+; CHECK-P8-NEXT:    mtfprd f3, r6
 ; CHECK-P8-NEXT:    xxswapd v0, vs5
-; CHECK-P8-NEXT:    mfvsrwz r6, f7
+; CHECK-P8-NEXT:    mffprwz r6, f7
 ; CHECK-P8-NEXT:    xscvdpsxws f13, f13
 ; CHECK-P8-NEXT:    xxswapd v5, vs3
 ; CHECK-P8-NEXT:    xscvdpsxws v3, v3
-; CHECK-P8-NEXT:    mtvsrd f8, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f10
-; CHECK-P8-NEXT:    mtvsrd f7, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f9
-; CHECK-P8-NEXT:    mtvsrd f10, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f12
-; CHECK-P8-NEXT:    mtvsrd f9, r6
+; CHECK-P8-NEXT:    mtfprd f8, r4
+; CHECK-P8-NEXT:    mffprwz r4, f10
+; CHECK-P8-NEXT:    mtfprd f7, r6
+; CHECK-P8-NEXT:    mffprwz r6, f9
+; CHECK-P8-NEXT:    mtfprd f10, r4
+; CHECK-P8-NEXT:    mffprwz r4, f12
+; CHECK-P8-NEXT:    mtfprd f9, r6
 ; CHECK-P8-NEXT:    xxswapd v6, vs10
-; CHECK-P8-NEXT:    mfvsrwz r6, f11
-; CHECK-P8-NEXT:    mtvsrd f12, r4
+; CHECK-P8-NEXT:    mffprwz r6, f11
+; CHECK-P8-NEXT:    mtfprd f12, r4
 ; CHECK-P8-NEXT:    xxswapd v1, vs9
 ; CHECK-P8-NEXT:    mfvsrwz r4, v2
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    mtvsrd f11, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f13
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mtfprd f11, r6
+; CHECK-P8-NEXT:    mffprwz r6, f13
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    xxswapd v7, vs11
 ; CHECK-P8-NEXT:    mfvsrwz r4, v3
 ; CHECK-P8-NEXT:    vmrglh v3, v5, v4
@@ -1164,8 +1164,8 @@
 ; CHECK-P8-NEXT:    vmrglh v2, v2, v0
 ; CHECK-P8-NEXT:    xxswapd v5, vs8
 ; CHECK-P8-NEXT:    xxswapd v0, vs2
-; CHECK-P8-NEXT:    mtvsrd f13, r6
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mtfprd f13, r6
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v8, vs0
 ; CHECK-P8-NEXT:    vmrglh v4, v5, v4
 ; CHECK-P8-NEXT:    vmrglh v5, v0, v1
@@ -1210,14 +1210,14 @@
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f4
 ; CHECK-P9-NEXT:    xscvdpsxws f6, f6
-; CHECK-P9-NEXT:    mfvsrwz r5, f5
+; CHECK-P9-NEXT:    mffprwz r5, f5
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f7, f7
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
-; CHECK-P9-NEXT:    mtvsrd f5, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f8
-; CHECK-P9-NEXT:    mtvsrd f8, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f2
+; CHECK-P9-NEXT:    mtfprd f5, r5
+; CHECK-P9-NEXT:    mffprwz r5, f8
+; CHECK-P9-NEXT:    mtfprd f8, r5
+; CHECK-P9-NEXT:    mffprwz r5, f2
 ; CHECK-P9-NEXT:    lxv vs0, 32(r4)
 ; CHECK-P9-NEXT:    xxsldwi vs9, vs0, vs0, 3
 ; CHECK-P9-NEXT:    xxswapd vs10, vs0
@@ -1225,40 +1225,40 @@
 ; CHECK-P9-NEXT:    xscvspdpn f10, vs10
 ; CHECK-P9-NEXT:    xscvdpsxws f9, f9
 ; CHECK-P9-NEXT:    xscvdpsxws f10, f10
-; CHECK-P9-NEXT:    mtvsrd f2, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f6
+; CHECK-P9-NEXT:    mtfprd f2, r5
+; CHECK-P9-NEXT:    mffprwz r5, f4
+; CHECK-P9-NEXT:    mtfprd f4, r5
+; CHECK-P9-NEXT:    mffprwz r5, f1
+; CHECK-P9-NEXT:    mtfprd f1, r5
+; CHECK-P9-NEXT:    mffprwz r5, f6
 ; CHECK-P9-NEXT:    xxswapd v2, vs2
 ; CHECK-P9-NEXT:    xxswapd v3, vs4
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mtvsrd f6, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f7
+; CHECK-P9-NEXT:    mtfprd f6, r5
+; CHECK-P9-NEXT:    mffprwz r5, f7
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    lxv vs1, 48(r4)
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P9-NEXT:    xxswapd v3, vs5
-; CHECK-P9-NEXT:    mtvsrd f7, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f3
+; CHECK-P9-NEXT:    mtfprd f7, r5
+; CHECK-P9-NEXT:    mffprwz r5, f3
 ; CHECK-P9-NEXT:    vmrglh v3, v3, v4
 ; CHECK-P9-NEXT:    xxswapd v4, vs6
 ; CHECK-P9-NEXT:    xxswapd v5, vs7
-; CHECK-P9-NEXT:    mtvsrd f3, r5
+; CHECK-P9-NEXT:    mtfprd f3, r5
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    xxswapd v0, vs3
 ; CHECK-P9-NEXT:    vmrglh v4, v5, v4
 ; CHECK-P9-NEXT:    xxswapd v5, vs8
 ; CHECK-P9-NEXT:    vmrglh v5, v5, v0
-; CHECK-P9-NEXT:    mfvsrwz r4, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r4
-; CHECK-P9-NEXT:    mfvsrwz r4, f0
+; CHECK-P9-NEXT:    mffprwz r4, f2
+; CHECK-P9-NEXT:    mtfprd f2, r4
+; CHECK-P9-NEXT:    mffprwz r4, f0
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    vmrglw v3, v5, v4
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xxmrgld vs2, v3, v2
@@ -1266,36 +1266,36 @@
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs1, vs1, 3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mffprwz r4, f0
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mffprwz r4, f0
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    vmrglh v2, v4, v2
 ; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mffprwz r4, f0
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs1, vs1, 1
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r5, f9
-; CHECK-P9-NEXT:    mtvsrd f9, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f10
-; CHECK-P9-NEXT:    mtvsrd f10, r5
+; CHECK-P9-NEXT:    mffprwz r5, f9
+; CHECK-P9-NEXT:    mtfprd f9, r5
+; CHECK-P9-NEXT:    mffprwz r5, f10
+; CHECK-P9-NEXT:    mtfprd f10, r5
 ; CHECK-P9-NEXT:    xxswapd v0, vs9
 ; CHECK-P9-NEXT:    xxswapd v1, vs10
 ; CHECK-P9-NEXT:    vmrglh v0, v1, v0
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v0
 ; CHECK-P9-NEXT:    stxv vs2, 0(r3)
-; CHECK-P9-NEXT:    mfvsrwz r4, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mffprwz r4, f0
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    xxswapd v5, vs0
 ; CHECK-P9-NEXT:    vmrglh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
@@ -1312,14 +1312,14 @@
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mfvsrwz r5, f2
+; CHECK-BE-NEXT:    mffprwz r5, f2
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    mtvsrd v2, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f3
+; CHECK-BE-NEXT:    mffprwz r5, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f4
 ; CHECK-BE-NEXT:    lxv vs0, 0(r4)
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs0, vs0, 3
@@ -1327,22 +1327,22 @@
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    mtvsrd v3, r5
 ; CHECK-BE-NEXT:    vmrghh v2, v3, v2
-; CHECK-BE-NEXT:    mfvsrwz r5, f3
+; CHECK-BE-NEXT:    mffprwz r5, f3
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    mtvsrd v3, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f1
+; CHECK-BE-NEXT:    mffprwz r5, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    mtvsrd v4, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f2
+; CHECK-BE-NEXT:    mffprwz r5, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    vmrghh v3, v3, v4
 ; CHECK-BE-NEXT:    mtvsrd v4, r5
 ; CHECK-BE-NEXT:    vmrghw v2, v3, v2
-; CHECK-BE-NEXT:    mfvsrwz r5, f1
+; CHECK-BE-NEXT:    mffprwz r5, f1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
@@ -1351,11 +1351,11 @@
 ; CHECK-BE-NEXT:    mtvsrd v5, r5
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    vmrghh v4, v5, v4
-; CHECK-BE-NEXT:    mfvsrwz r5, f1
+; CHECK-BE-NEXT:    mffprwz r5, f1
 ; CHECK-BE-NEXT:    lxv vs1, 48(r4)
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    mtvsrd v5, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f0
+; CHECK-BE-NEXT:    mffprwz r5, f0
 ; CHECK-BE-NEXT:    lxv vs0, 32(r4)
 ; CHECK-BE-NEXT:    xscvspdpn f5, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
@@ -1371,26 +1371,26 @@
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    vmrghw v3, v5, v4
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mfvsrwz r4, f5
+; CHECK-BE-NEXT:    mffprwz r4, f5
 ; CHECK-BE-NEXT:    xxmrghd vs4, v3, v2
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    mtvsrd v2, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f2
+; CHECK-BE-NEXT:    mffprwz r4, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    stxv vs4, 0(r3)
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    mtvsrd v3, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f3
+; CHECK-BE-NEXT:    mffprwz r4, f3
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    mtvsrd v4, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f1
+; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    vmrghh v3, v4, v3
 ; CHECK-BE-NEXT:    mtvsrd v4, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f1
+; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
@@ -1398,7 +1398,7 @@
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mtvsrd v3, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f1
+; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
@@ -1407,10 +1407,10 @@
 ; CHECK-BE-NEXT:    mtvsrd v4, r4
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mfvsrwz r4, f1
+; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    mtvsrd v4, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f0
+; CHECK-BE-NEXT:    mffprwz r4, f0
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    mtvsrd v5, r4
 ; CHECK-BE-NEXT:    vmrghh v4, v4, v5
diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll
--- a/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll
@@ -12,7 +12,7 @@
 define <2 x i64> @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xxmrglw vs0, v2, v2
 ; CHECK-P8-NEXT:    xvcvspdp vs0, vs0
@@ -21,7 +21,7 @@
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    xxmrglw vs0, v2, v2
 ; CHECK-P9-NEXT:    xvcvspdp vs0, vs0
@@ -30,7 +30,7 @@
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrd f0, r3
+; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    xxmrghw vs0, vs0, vs0
 ; CHECK-BE-NEXT:    xvcvspdp vs0, vs0
 ; CHECK-BE-NEXT:    xvcvdpuxds v2, vs0
@@ -311,7 +311,7 @@
 define <2 x i64> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xxmrglw vs0, v2, v2
 ; CHECK-P8-NEXT:    xvcvspdp vs0, vs0
@@ -320,7 +320,7 @@
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    xxmrglw vs0, v2, v2
 ; CHECK-P9-NEXT:    xvcvspdp vs0, vs0
@@ -329,7 +329,7 @@
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrd f0, r3
+; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    xxmrghw vs0, vs0, vs0
 ; CHECK-BE-NEXT:    xvcvspdp vs0, vs0
 ; CHECK-BE-NEXT:    xvcvdpuxds v2, vs0
diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll
--- a/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll
@@ -12,22 +12,22 @@
 define i16 @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-P8-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mffprwz r4, f0
+; CHECK-P8-NEXT:    mffprwz r3, f1
+; CHECK-P8-NEXT:    mtfprd f1, r4
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v3, vs1
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    vmrglb v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    clrldi r3, r3, 48
 ; CHECK-P8-NEXT:    sth r3, -2(r1)
 ; CHECK-P8-NEXT:    lhz r3, -2(r1)
@@ -35,17 +35,17 @@
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs1
 ; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    vmrglb v2, v3, v2
@@ -57,16 +57,16 @@
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrd f0, r3
+; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -2
@@ -96,23 +96,23 @@
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mtvsrd f1, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    mffprwz r3, f1
+; CHECK-P8-NEXT:    mtfprd f1, r3
+; CHECK-P8-NEXT:    mffprwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r4, f2
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mffprwz r3, f3
+; CHECK-P8-NEXT:    mtfprd f2, r4
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    mtvsrd f3, r3
+; CHECK-P8-NEXT:    mtfprd f3, r3
 ; CHECK-P8-NEXT:    xxswapd v3, vs2
 ; CHECK-P8-NEXT:    xxswapd v5, vs3
 ; CHECK-P8-NEXT:    vmrglb v2, v3, v2
 ; CHECK-P8-NEXT:    vmrglb v3, v4, v5
 ; CHECK-P8-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt:
@@ -120,26 +120,26 @@
 ; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, v2
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglb v3, v4, v3
 ; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 1
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    vmrglb v2, v4, v2
@@ -152,25 +152,25 @@
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xscvspdpn f0, v2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghb v3, v4, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
@@ -207,34 +207,34 @@
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    mfvsrwz r6, f1
-; CHECK-P8-NEXT:    mfvsrwz r5, f0
-; CHECK-P8-NEXT:    mtvsrd f1, r6
-; CHECK-P8-NEXT:    mtvsrd f0, r5
+; CHECK-P8-NEXT:    mffprwz r4, f4
+; CHECK-P8-NEXT:    mffprwz r6, f1
+; CHECK-P8-NEXT:    mffprwz r5, f0
+; CHECK-P8-NEXT:    mtfprd f1, r6
+; CHECK-P8-NEXT:    mtfprd f0, r5
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
 ; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 1
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    xscvspdpn f0, v2
-; CHECK-P8-NEXT:    mtvsrd f4, r4
+; CHECK-P8-NEXT:    mtfprd f4, r4
 ; CHECK-P8-NEXT:    xscvspdpn f1, vs1
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    mffprwz r4, f2
 ; CHECK-P8-NEXT:    xxswapd v1, vs4
 ; CHECK-P8-NEXT:    vmrglb v2, v4, v3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
+; CHECK-P8-NEXT:    mtfprd f2, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
+; CHECK-P8-NEXT:    mffprwz r4, f5
 ; CHECK-P8-NEXT:    xxswapd v5, vs2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
+; CHECK-P8-NEXT:    mffprwz r3, f0
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mffprwz r3, f1
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    mtvsrd f1, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f3, r4
+; CHECK-P8-NEXT:    mtfprd f1, r3
+; CHECK-P8-NEXT:    mffprwz r3, f3
+; CHECK-P8-NEXT:    mtfprd f3, r4
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v6, vs3
 ; CHECK-P8-NEXT:    xxswapd v0, vs0
 ; CHECK-P8-NEXT:    vmrglb v3, v3, v4
@@ -244,7 +244,7 @@
 ; CHECK-P8-NEXT:    vmrglh v3, v5, v4
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt:
@@ -254,24 +254,24 @@
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    lxv vs0, 16(r3)
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs0, vs0, 3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
@@ -280,24 +280,24 @@
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    vmrglb v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglb v3, v4, v3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxswapd v5, vs0
@@ -314,13 +314,13 @@
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
@@ -329,16 +329,16 @@
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    vmrghb v2, v3, v2
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
@@ -346,7 +346,7 @@
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
@@ -355,10 +355,10 @@
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    vmrghb v3, v4, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    vmrghb v4, v4, v5
@@ -400,47 +400,47 @@
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvspdpn f6, vs6
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    mffprwz r4, f2
 ; CHECK-P8-NEXT:    xscvspdpn f7, vs7
-; CHECK-P8-NEXT:    mtvsrd f2, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
+; CHECK-P8-NEXT:    mtfprd f2, r4
+; CHECK-P8-NEXT:    mffprwz r4, f4
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    xscvspdpn f8, vs8
-; CHECK-P8-NEXT:    mtvsrd f4, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    mtfprd f4, r4
+; CHECK-P8-NEXT:    mffprwz r4, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f5
 ; CHECK-P8-NEXT:    xxswapd v0, vs4
 ; CHECK-P8-NEXT:    xscvspdpn f9, vs9
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    mtfprd f5, r4
+; CHECK-P8-NEXT:    mffprwz r4, f1
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f6
 ; CHECK-P8-NEXT:    xxswapd v3, vs5
-; CHECK-P8-NEXT:    mtvsrd f6, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
+; CHECK-P8-NEXT:    mtfprd f6, r4
+; CHECK-P8-NEXT:    mffprwz r4, f3
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f7
 ; CHECK-P8-NEXT:    xxswapd v4, vs6
-; CHECK-P8-NEXT:    mtvsrd f7, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    mtfprd f7, r4
+; CHECK-P8-NEXT:    mffprwz r4, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f8
 ; CHECK-P8-NEXT:    xxswapd v5, vs7
-; CHECK-P8-NEXT:    mtvsrd f8, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    mtfprd f8, r4
+; CHECK-P8-NEXT:    mffprwz r4, f1
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f9
 ; CHECK-P8-NEXT:    xxswapd v1, vs8
-; CHECK-P8-NEXT:    mtvsrd f9, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
+; CHECK-P8-NEXT:    mtfprd f9, r4
+; CHECK-P8-NEXT:    mffprwz r4, f3
 ; CHECK-P8-NEXT:    vmrglb v3, v4, v3
 ; CHECK-P8-NEXT:    xxswapd v4, vs2
-; CHECK-P8-NEXT:    mtvsrd f3, r4
+; CHECK-P8-NEXT:    mtfprd f3, r4
 ; CHECK-P8-NEXT:    xxswapd v6, vs9
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    mffprwz r4, f0
 ; CHECK-P8-NEXT:    xscvspdpn f0, v2
 ; CHECK-P8-NEXT:    xxswapd v7, vs3
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    mtfprd f5, r4
+; CHECK-P8-NEXT:    mffprwz r4, f1
 ; CHECK-P8-NEXT:    vmrglb v4, v4, v5
 ; CHECK-P8-NEXT:    xxswapd v5, vs5
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    li r4, 48
 ; CHECK-P8-NEXT:    lvx v9, r3, r4
 ; CHECK-P8-NEXT:    vmrglb v1, v6, v1
@@ -460,23 +460,23 @@
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f4, r4
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    mffprwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r4, f4
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mtfprd f4, r4
+; CHECK-P8-NEXT:    mffprwz r3, f1
+; CHECK-P8-NEXT:    mffprwz r4, f2
 ; CHECK-P8-NEXT:    xxswapd v9, vs4
-; CHECK-P8-NEXT:    mtvsrd f1, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
+; CHECK-P8-NEXT:    mtfprd f1, r3
+; CHECK-P8-NEXT:    mffprwz r3, f3
+; CHECK-P8-NEXT:    mtfprd f2, r4
 ; CHECK-P8-NEXT:    xxswapd v6, vs1
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
+; CHECK-P8-NEXT:    mffprwz r4, f5
 ; CHECK-P8-NEXT:    vmrglb v2, v0, v7
 ; CHECK-P8-NEXT:    xxswapd v0, vs0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v7, vs2
-; CHECK-P8-NEXT:    mtvsrd f3, r4
+; CHECK-P8-NEXT:    mtfprd f3, r4
 ; CHECK-P8-NEXT:    vmrglb v5, v8, v5
 ; CHECK-P8-NEXT:    xxswapd v8, vs0
 ; CHECK-P8-NEXT:    xxswapd v10, vs3
@@ -501,24 +501,24 @@
 ; CHECK-P9-NEXT:    lxv vs0, 48(r3)
 ; CHECK-P9-NEXT:    lxv vs1, 32(r3)
 ; CHECK-P9-NEXT:    lxv vs4, 16(r3)
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
+; CHECK-P9-NEXT:    mtfprd f3, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs3
 ; CHECK-P9-NEXT:    xxswapd vs3, vs2
 ; CHECK-P9-NEXT:    xscvspdpn f3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
+; CHECK-P9-NEXT:    mtfprd f3, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    xscvspdpn f3, vs2
 ; CHECK-P9-NEXT:    xxsldwi vs2, vs2, vs2, 1
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
+; CHECK-P9-NEXT:    mtfprd f3, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xxsldwi vs2, vs4, vs4, 3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
@@ -527,26 +527,26 @@
 ; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    vmrglb v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs4
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs4
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    vmrglb v3, v4, v3
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xxsldwi vs2, vs4, vs4, 1
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v5, vs2
 ; CHECK-P9-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
@@ -554,24 +554,24 @@
 ; CHECK-P9-NEXT:    vmrglb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v5, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs0, vs0, 3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
@@ -580,24 +580,24 @@
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    vmrglb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v5, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglb v4, v5, v4
 ; CHECK-P9-NEXT:    xxswapd v5, vs1
 ; CHECK-P9-NEXT:    xxswapd v0, vs0
@@ -616,13 +616,13 @@
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
-; CHECK-BE-NEXT:    mfvsrwz r3, f4
+; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xxswapd vs4, vs3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs4
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    mfvsrwz r3, f4
+; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs3
 ; CHECK-BE-NEXT:    xxsldwi vs3, vs3, vs3, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
@@ -631,16 +631,16 @@
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    vmrghb v2, v3, v2
-; CHECK-BE-NEXT:    mfvsrwz r3, f4
+; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xxsldwi vs3, vs2, vs2, 3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs2
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
@@ -648,7 +648,7 @@
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs2
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs2, vs2, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
@@ -657,16 +657,16 @@
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    vmrghb v3, v4, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs1
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
@@ -675,7 +675,7 @@
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
@@ -684,16 +684,16 @@
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    vmrghb v3, v4, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
@@ -701,7 +701,7 @@
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    vmrghh v3, v4, v3
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
@@ -710,10 +710,10 @@
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    vmrghb v4, v5, v4
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v0, r3
 ; CHECK-BE-NEXT:    vmrghb v5, v5, v0
@@ -730,22 +730,22 @@
 define i16 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-P8-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mtvsrd f1, r4
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mffprwz r4, f0
+; CHECK-P8-NEXT:    mffprwz r3, f1
+; CHECK-P8-NEXT:    mtfprd f1, r4
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v3, vs1
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    vmrglb v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    clrldi r3, r3, 48
 ; CHECK-P8-NEXT:    sth r3, -2(r1)
 ; CHECK-P8-NEXT:    lhz r3, -2(r1)
@@ -753,17 +753,17 @@
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs1
 ; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    vmrglb v2, v3, v2
@@ -775,16 +775,16 @@
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrd f0, r3
+; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -2
@@ -814,23 +814,23 @@
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mtvsrd f1, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    mffprwz r3, f1
+; CHECK-P8-NEXT:    mtfprd f1, r3
+; CHECK-P8-NEXT:    mffprwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r4, f2
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mffprwz r3, f3
+; CHECK-P8-NEXT:    mtfprd f2, r4
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    mtvsrd f3, r3
+; CHECK-P8-NEXT:    mtfprd f3, r3
 ; CHECK-P8-NEXT:    xxswapd v3, vs2
 ; CHECK-P8-NEXT:    xxswapd v5, vs3
 ; CHECK-P8-NEXT:    vmrglb v2, v3, v2
 ; CHECK-P8-NEXT:    vmrglb v3, v4, v5
 ; CHECK-P8-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt_signed:
@@ -838,26 +838,26 @@
 ; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f0, v2
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglb v3, v4, v3
 ; CHECK-P9-NEXT:    xxswapd v4, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 1
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    vmrglb v2, v4, v2
@@ -870,25 +870,25 @@
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xscvspdpn f0, v2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghb v3, v4, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
@@ -925,34 +925,34 @@
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    mfvsrwz r6, f1
-; CHECK-P8-NEXT:    mfvsrwz r5, f0
-; CHECK-P8-NEXT:    mtvsrd f1, r6
-; CHECK-P8-NEXT:    mtvsrd f0, r5
+; CHECK-P8-NEXT:    mffprwz r4, f4
+; CHECK-P8-NEXT:    mffprwz r6, f1
+; CHECK-P8-NEXT:    mffprwz r5, f0
+; CHECK-P8-NEXT:    mtfprd f1, r6
+; CHECK-P8-NEXT:    mtfprd f0, r5
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
 ; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 1
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    xscvspdpn f0, v2
-; CHECK-P8-NEXT:    mtvsrd f4, r4
+; CHECK-P8-NEXT:    mtfprd f4, r4
 ; CHECK-P8-NEXT:    xscvspdpn f1, vs1
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    mffprwz r4, f2
 ; CHECK-P8-NEXT:    xxswapd v1, vs4
 ; CHECK-P8-NEXT:    vmrglb v2, v4, v3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
+; CHECK-P8-NEXT:    mtfprd f2, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
+; CHECK-P8-NEXT:    mffprwz r4, f5
 ; CHECK-P8-NEXT:    xxswapd v5, vs2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
+; CHECK-P8-NEXT:    mffprwz r3, f0
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mffprwz r3, f1
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    mtvsrd f1, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f3, r4
+; CHECK-P8-NEXT:    mtfprd f1, r3
+; CHECK-P8-NEXT:    mffprwz r3, f3
+; CHECK-P8-NEXT:    mtfprd f3, r4
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v6, vs3
 ; CHECK-P8-NEXT:    xxswapd v0, vs0
 ; CHECK-P8-NEXT:    vmrglb v3, v3, v4
@@ -962,7 +962,7 @@
 ; CHECK-P8-NEXT:    vmrglh v3, v5, v4
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt_signed:
@@ -972,24 +972,24 @@
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    lxv vs0, 16(r3)
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs0, vs0, 3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
@@ -998,24 +998,24 @@
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    vmrglb v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglb v3, v4, v3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxswapd v5, vs0
@@ -1032,13 +1032,13 @@
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
@@ -1047,16 +1047,16 @@
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    vmrghb v2, v3, v2
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
@@ -1064,7 +1064,7 @@
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
@@ -1073,10 +1073,10 @@
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    vmrghb v3, v4, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    vmrghb v4, v4, v5
@@ -1118,47 +1118,47 @@
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvspdpn f6, vs6
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    mffprwz r4, f2
 ; CHECK-P8-NEXT:    xscvspdpn f7, vs7
-; CHECK-P8-NEXT:    mtvsrd f2, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
+; CHECK-P8-NEXT:    mtfprd f2, r4
+; CHECK-P8-NEXT:    mffprwz r4, f4
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    xscvspdpn f8, vs8
-; CHECK-P8-NEXT:    mtvsrd f4, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    mtfprd f4, r4
+; CHECK-P8-NEXT:    mffprwz r4, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f5
 ; CHECK-P8-NEXT:    xxswapd v0, vs4
 ; CHECK-P8-NEXT:    xscvspdpn f9, vs9
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    mtfprd f5, r4
+; CHECK-P8-NEXT:    mffprwz r4, f1
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f6
 ; CHECK-P8-NEXT:    xxswapd v3, vs5
-; CHECK-P8-NEXT:    mtvsrd f6, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
+; CHECK-P8-NEXT:    mtfprd f6, r4
+; CHECK-P8-NEXT:    mffprwz r4, f3
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f7
 ; CHECK-P8-NEXT:    xxswapd v4, vs6
-; CHECK-P8-NEXT:    mtvsrd f7, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    mtfprd f7, r4
+; CHECK-P8-NEXT:    mffprwz r4, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f8
 ; CHECK-P8-NEXT:    xxswapd v5, vs7
-; CHECK-P8-NEXT:    mtvsrd f8, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    mtfprd f8, r4
+; CHECK-P8-NEXT:    mffprwz r4, f1
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f9
 ; CHECK-P8-NEXT:    xxswapd v1, vs8
-; CHECK-P8-NEXT:    mtvsrd f9, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
+; CHECK-P8-NEXT:    mtfprd f9, r4
+; CHECK-P8-NEXT:    mffprwz r4, f3
 ; CHECK-P8-NEXT:    vmrglb v3, v4, v3
 ; CHECK-P8-NEXT:    xxswapd v4, vs2
-; CHECK-P8-NEXT:    mtvsrd f3, r4
+; CHECK-P8-NEXT:    mtfprd f3, r4
 ; CHECK-P8-NEXT:    xxswapd v6, vs9
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    mffprwz r4, f0
 ; CHECK-P8-NEXT:    xscvspdpn f0, v2
 ; CHECK-P8-NEXT:    xxswapd v7, vs3
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    mtfprd f5, r4
+; CHECK-P8-NEXT:    mffprwz r4, f1
 ; CHECK-P8-NEXT:    vmrglb v4, v4, v5
 ; CHECK-P8-NEXT:    xxswapd v5, vs5
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    li r4, 48
 ; CHECK-P8-NEXT:    lvx v9, r3, r4
 ; CHECK-P8-NEXT:    vmrglb v1, v6, v1
@@ -1178,23 +1178,23 @@
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    xscvdpsxws f5, f5
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f4, r4
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
+; CHECK-P8-NEXT:    mffprwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r4, f4
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mtfprd f4, r4
+; CHECK-P8-NEXT:    mffprwz r3, f1
+; CHECK-P8-NEXT:    mffprwz r4, f2
 ; CHECK-P8-NEXT:    xxswapd v9, vs4
-; CHECK-P8-NEXT:    mtvsrd f1, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r4
+; CHECK-P8-NEXT:    mtfprd f1, r3
+; CHECK-P8-NEXT:    mffprwz r3, f3
+; CHECK-P8-NEXT:    mtfprd f2, r4
 ; CHECK-P8-NEXT:    xxswapd v6, vs1
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
+; CHECK-P8-NEXT:    mffprwz r4, f5
 ; CHECK-P8-NEXT:    vmrglb v2, v0, v7
 ; CHECK-P8-NEXT:    xxswapd v0, vs0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v7, vs2
-; CHECK-P8-NEXT:    mtvsrd f3, r4
+; CHECK-P8-NEXT:    mtfprd f3, r4
 ; CHECK-P8-NEXT:    vmrglb v5, v8, v5
 ; CHECK-P8-NEXT:    xxswapd v8, vs0
 ; CHECK-P8-NEXT:    xxswapd v10, vs3
@@ -1219,24 +1219,24 @@
 ; CHECK-P9-NEXT:    lxv vs0, 48(r3)
 ; CHECK-P9-NEXT:    lxv vs1, 32(r3)
 ; CHECK-P9-NEXT:    lxv vs4, 16(r3)
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
+; CHECK-P9-NEXT:    mtfprd f3, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs3
 ; CHECK-P9-NEXT:    xxswapd vs3, vs2
 ; CHECK-P9-NEXT:    xscvspdpn f3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
+; CHECK-P9-NEXT:    mtfprd f3, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    xscvspdpn f3, vs2
 ; CHECK-P9-NEXT:    xxsldwi vs2, vs2, vs2, 1
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
+; CHECK-P9-NEXT:    mtfprd f3, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xxsldwi vs2, vs4, vs4, 3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
@@ -1245,26 +1245,26 @@
 ; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    vmrglb v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs4
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs4
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    vmrglb v3, v4, v3
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xxsldwi vs2, vs4, vs4, 1
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v5, vs2
 ; CHECK-P9-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
@@ -1272,24 +1272,24 @@
 ; CHECK-P9-NEXT:    vmrglb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xscvspdpn f2, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v5, vs1
 ; CHECK-P9-NEXT:    xxsldwi vs1, vs0, vs0, 3
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
@@ -1298,24 +1298,24 @@
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    vmrglb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs0
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v5, vs1
 ; CHECK-P9-NEXT:    xscvspdpn f1, vs0
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-P9-NEXT:    xscvspdpn f0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglb v4, v5, v4
 ; CHECK-P9-NEXT:    xxswapd v5, vs1
 ; CHECK-P9-NEXT:    xxswapd v0, vs0
@@ -1334,13 +1334,13 @@
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
-; CHECK-BE-NEXT:    mfvsrwz r3, f4
+; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xxswapd vs4, vs3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs4
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    mfvsrwz r3, f4
+; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs3
 ; CHECK-BE-NEXT:    xxsldwi vs3, vs3, vs3, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
@@ -1349,16 +1349,16 @@
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    vmrghb v2, v3, v2
-; CHECK-BE-NEXT:    mfvsrwz r3, f4
+; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xxsldwi vs3, vs2, vs2, 3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs2
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
@@ -1366,7 +1366,7 @@
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs2
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs2, vs2, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
@@ -1375,16 +1375,16 @@
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    vmrghb v3, v4, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs1
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
@@ -1393,7 +1393,7 @@
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
@@ -1402,16 +1402,16 @@
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    vmrghb v3, v4, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
@@ -1419,7 +1419,7 @@
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    vmrghh v3, v4, v3
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
@@ -1428,10 +1428,10 @@
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    vmrghb v4, v5, v4
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v0, r3
 ; CHECK-BE-NEXT:    vmrghb v5, v5, v0
diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll
--- a/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll
@@ -15,27 +15,27 @@
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mffprwz r3, f1
+; CHECK-P8-NEXT:    mffprwz r4, f0
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xxswapd v3, vs1
 ; CHECK-P8-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xscvdpsxws f0, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
@@ -45,12 +45,12 @@
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpsxws f0, v2
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
@@ -75,23 +75,23 @@
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r3, f2
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
-; CHECK-P8-NEXT:    mtvsrd f3, r4
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r3, f2
+; CHECK-P8-NEXT:    mffprwz r4, f3
+; CHECK-P8-NEXT:    mtfprd f2, r3
+; CHECK-P8-NEXT:    mtfprd f3, r4
+; CHECK-P8-NEXT:    mffprwz r3, f0
 ; CHECK-P8-NEXT:    xxswapd v2, vs2
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    mffprwz r4, f1
 ; CHECK-P8-NEXT:    xxswapd v4, vs3
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    xxswapd v5, vs1
 ; CHECK-P8-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P8-NEXT:    vmrglh v3, v5, v4
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt:
@@ -101,19 +101,19 @@
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    lxv vs0, 16(r3)
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
 ; CHECK-P9-NEXT:    xxswapd v2, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xxswapd v4, vs0
@@ -129,20 +129,20 @@
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    vmrghh v2, v2, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghh v3, v3, v4
@@ -176,30 +176,30 @@
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r3, f4
+; CHECK-P8-NEXT:    mffprwz r3, f4
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    mtvsrd f4, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f6
-; CHECK-P8-NEXT:    mtvsrd f5, r4
+; CHECK-P8-NEXT:    mffprwz r4, f5
+; CHECK-P8-NEXT:    mtfprd f4, r3
+; CHECK-P8-NEXT:    mffprwz r3, f6
+; CHECK-P8-NEXT:    mtfprd f5, r4
 ; CHECK-P8-NEXT:    xxswapd v2, vs4
-; CHECK-P8-NEXT:    mfvsrwz r4, f7
-; CHECK-P8-NEXT:    mtvsrd f6, r3
+; CHECK-P8-NEXT:    mffprwz r4, f7
+; CHECK-P8-NEXT:    mtfprd f6, r3
 ; CHECK-P8-NEXT:    xxswapd v3, vs5
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mtvsrd f7, r4
+; CHECK-P8-NEXT:    mffprwz r3, f0
+; CHECK-P8-NEXT:    mtfprd f7, r4
 ; CHECK-P8-NEXT:    xxswapd v4, vs6
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mffprwz r4, f1
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v1, vs7
-; CHECK-P8-NEXT:    mfvsrwz r3, f2
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mffprwz r3, f2
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v5, vs0
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
+; CHECK-P8-NEXT:    mffprwz r4, f3
+; CHECK-P8-NEXT:    mtfprd f2, r3
 ; CHECK-P8-NEXT:    xxswapd v0, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    xxswapd v6, vs2
 ; CHECK-P8-NEXT:    vmrglh v2, v5, v2
 ; CHECK-P8-NEXT:    xxswapd v5, vs0
@@ -220,40 +220,40 @@
 ; CHECK-P9-NEXT:    lxv vs0, 48(r3)
 ; CHECK-P9-NEXT:    lxv vs1, 32(r3)
 ; CHECK-P9-NEXT:    lxv vs2, 16(r3)
-; CHECK-P9-NEXT:    mfvsrwz r3, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
+; CHECK-P9-NEXT:    mffprwz r3, f4
+; CHECK-P9-NEXT:    mtfprd f4, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
 ; CHECK-P9-NEXT:    xxswapd v2, vs4
-; CHECK-P9-NEXT:    mtvsrd f3, r3
+; CHECK-P9-NEXT:    mtfprd f3, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
+; CHECK-P9-NEXT:    mtfprd f3, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
 ; CHECK-P9-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    vmrglh v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglh v3, v3, v4
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxswapd v5, vs0
@@ -271,41 +271,41 @@
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
-; CHECK-BE-NEXT:    mfvsrwz r3, f4
+; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    vmrghh v2, v2, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghh v3, v3, v4
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghh v3, v3, v4
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    vmrghh v4, v4, v5
@@ -350,63 +350,63 @@
 ; CHECK-P8-NEXT:    xxswapd vs7, vs7
 ; CHECK-P8-NEXT:    xscvdpsxws v2, f9
 ; CHECK-P8-NEXT:    xxswapd vs9, vs9
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
+; CHECK-P8-NEXT:    mffprwz r4, f4
 ; CHECK-P8-NEXT:    xscvdpsxws v3, f11
 ; CHECK-P8-NEXT:    xxswapd vs11, vs11
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r6, f6
-; CHECK-P8-NEXT:    mtvsrd f4, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f8
+; CHECK-P8-NEXT:    mffprwz r6, f6
+; CHECK-P8-NEXT:    mtfprd f4, r4
+; CHECK-P8-NEXT:    mffprwz r4, f8
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    xxswapd v4, vs4
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
-; CHECK-P8-NEXT:    mtvsrd f6, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f10
-; CHECK-P8-NEXT:    mtvsrd f8, r4
+; CHECK-P8-NEXT:    mtfprd f6, r6
+; CHECK-P8-NEXT:    mffprwz r6, f10
+; CHECK-P8-NEXT:    mtfprd f8, r4
 ; CHECK-P8-NEXT:    xxswapd v5, vs6
-; CHECK-P8-NEXT:    mfvsrwz r4, f12
+; CHECK-P8-NEXT:    mffprwz r4, f12
 ; CHECK-P8-NEXT:    xscvdpsxws f5, f5
 ; CHECK-P8-NEXT:    xxswapd v0, vs8
-; CHECK-P8-NEXT:    mtvsrd f10, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f13
-; CHECK-P8-NEXT:    mtvsrd f12, r4
+; CHECK-P8-NEXT:    mtfprd f10, r6
+; CHECK-P8-NEXT:    mffprwz r6, f13
+; CHECK-P8-NEXT:    mtfprd f12, r4
 ; CHECK-P8-NEXT:    xxswapd v1, vs10
 ; CHECK-P8-NEXT:    mfvsrwz r4, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    xxswapd v6, vs12
 ; CHECK-P8-NEXT:    xscvdpsxws f9, f9
-; CHECK-P8-NEXT:    mtvsrd f13, r6
+; CHECK-P8-NEXT:    mtfprd f13, r6
 ; CHECK-P8-NEXT:    mfvsrwz r6, v3
 ; CHECK-P8-NEXT:    mtvsrd v2, r4
 ; CHECK-P8-NEXT:    xxswapd v7, vs13
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    mffprwz r4, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f7, f7
 ; CHECK-P8-NEXT:    xxswapd v2, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f11, f11
 ; CHECK-P8-NEXT:    mtvsrd v3, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f1
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mffprwz r6, f1
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    xxswapd v3, v3
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
-; CHECK-P8-NEXT:    mtvsrd f1, r6
+; CHECK-P8-NEXT:    mffprwz r4, f2
+; CHECK-P8-NEXT:    mtfprd f1, r6
 ; CHECK-P8-NEXT:    xxswapd v8, vs0
-; CHECK-P8-NEXT:    mtvsrd f2, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
+; CHECK-P8-NEXT:    mtfprd f2, r4
+; CHECK-P8-NEXT:    mffprwz r4, f5
 ; CHECK-P8-NEXT:    xxswapd v9, vs1
-; CHECK-P8-NEXT:    mfvsrwz r6, f3
+; CHECK-P8-NEXT:    mffprwz r6, f3
 ; CHECK-P8-NEXT:    xxswapd v10, vs2
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f9
-; CHECK-P8-NEXT:    mtvsrd f3, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f7
-; CHECK-P8-NEXT:    mtvsrd f9, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f11
+; CHECK-P8-NEXT:    mtfprd f5, r4
+; CHECK-P8-NEXT:    mffprwz r4, f9
+; CHECK-P8-NEXT:    mtfprd f3, r6
+; CHECK-P8-NEXT:    mffprwz r6, f7
+; CHECK-P8-NEXT:    mtfprd f9, r4
+; CHECK-P8-NEXT:    mffprwz r4, f11
 ; CHECK-P8-NEXT:    vmrglh v4, v8, v4
 ; CHECK-P8-NEXT:    xxswapd v8, vs3
 ; CHECK-P8-NEXT:    vmrglh v5, v9, v5
 ; CHECK-P8-NEXT:    xxswapd v9, vs5
-; CHECK-P8-NEXT:    mtvsrd f7, r6
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mtfprd f7, r6
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    vmrglh v0, v10, v0
 ; CHECK-P8-NEXT:    xxswapd v10, vs7
 ; CHECK-P8-NEXT:    vmrglh v1, v8, v1
@@ -439,32 +439,32 @@
 ; CHECK-P9-NEXT:    xscvdpsxws f8, f1
 ; CHECK-P9-NEXT:    xxswapd vs4, vs4
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f4
-; CHECK-P9-NEXT:    mfvsrwz r5, f5
+; CHECK-P9-NEXT:    mffprwz r5, f5
 ; CHECK-P9-NEXT:    xscvdpsxws f9, f0
 ; CHECK-P9-NEXT:    xxswapd vs3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
-; CHECK-P9-NEXT:    mtvsrd f5, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f6
+; CHECK-P9-NEXT:    mtfprd f5, r5
+; CHECK-P9-NEXT:    mffprwz r5, f6
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mtvsrd f6, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f7
-; CHECK-P9-NEXT:    mtvsrd f7, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f8
-; CHECK-P9-NEXT:    mtvsrd f8, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f9
-; CHECK-P9-NEXT:    mtvsrd f9, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f3
+; CHECK-P9-NEXT:    mtfprd f6, r5
+; CHECK-P9-NEXT:    mffprwz r5, f7
+; CHECK-P9-NEXT:    mtfprd f7, r5
+; CHECK-P9-NEXT:    mffprwz r5, f8
+; CHECK-P9-NEXT:    mtfprd f8, r5
+; CHECK-P9-NEXT:    mffprwz r5, f9
+; CHECK-P9-NEXT:    mtfprd f9, r5
+; CHECK-P9-NEXT:    mffprwz r5, f4
+; CHECK-P9-NEXT:    mtfprd f4, r5
+; CHECK-P9-NEXT:    mffprwz r5, f3
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xxswapd v2, vs5
 ; CHECK-P9-NEXT:    xxswapd v5, vs8
 ; CHECK-P9-NEXT:    xxswapd v0, vs9
-; CHECK-P9-NEXT:    mtvsrd f3, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r5
+; CHECK-P9-NEXT:    mtfprd f3, r5
+; CHECK-P9-NEXT:    mffprwz r5, f2
+; CHECK-P9-NEXT:    mtfprd f2, r5
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    xxswapd v1, vs2
@@ -475,49 +475,49 @@
 ; CHECK-P9-NEXT:    xxswapd v4, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
-; CHECK-P9-NEXT:    mfvsrwz r5, f1
+; CHECK-P9-NEXT:    mffprwz r5, f1
 ; CHECK-P9-NEXT:    vmrglh v3, v3, v4
 ; CHECK-P9-NEXT:    xxswapd v4, vs7
-; CHECK-P9-NEXT:    mtvsrd f1, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f0
+; CHECK-P9-NEXT:    mtfprd f1, r5
+; CHECK-P9-NEXT:    mffprwz r5, f0
 ; CHECK-P9-NEXT:    vmrglh v4, v4, v1
 ; CHECK-P9-NEXT:    xxswapd v1, vs1
-; CHECK-P9-NEXT:    mtvsrd f0, r5
+; CHECK-P9-NEXT:    mtfprd f0, r5
 ; CHECK-P9-NEXT:    vmrglh v5, v5, v1
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    xxswapd v1, vs0
 ; CHECK-P9-NEXT:    lxv vs0, 112(r4)
 ; CHECK-P9-NEXT:    lxv vs1, 96(r4)
-; CHECK-P9-NEXT:    mfvsrwz r4, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r4
-; CHECK-P9-NEXT:    mfvsrwz r4, f2
+; CHECK-P9-NEXT:    mffprwz r4, f3
+; CHECK-P9-NEXT:    mtfprd f3, r4
+; CHECK-P9-NEXT:    mffprwz r4, f2
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    vmrglw v3, v5, v4
 ; CHECK-P9-NEXT:    xxmrgld vs4, v3, v2
 ; CHECK-P9-NEXT:    xxswapd v2, vs3
 ; CHECK-P9-NEXT:    vmrglh v0, v0, v1
-; CHECK-P9-NEXT:    mtvsrd f2, r4
+; CHECK-P9-NEXT:    mtfprd f2, r4
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r4, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r4
-; CHECK-P9-NEXT:    mfvsrwz r4, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r4
+; CHECK-P9-NEXT:    mffprwz r4, f2
+; CHECK-P9-NEXT:    mtfprd f2, r4
+; CHECK-P9-NEXT:    mffprwz r4, f1
+; CHECK-P9-NEXT:    mtfprd f1, r4
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r4, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r4
-; CHECK-P9-NEXT:    mfvsrwz r4, f0
+; CHECK-P9-NEXT:    mffprwz r4, f1
+; CHECK-P9-NEXT:    mtfprd f1, r4
+; CHECK-P9-NEXT:    mffprwz r4, f0
 ; CHECK-P9-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    vmrglh v3, v3, v4
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    xxswapd v5, vs0
 ; CHECK-P9-NEXT:    vmrglh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
@@ -535,7 +535,7 @@
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    mfvsrwz r5, f5
+; CHECK-BE-NEXT:    mffprwz r5, f5
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    lxv vs2, 16(r4)
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
@@ -543,40 +543,40 @@
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mtvsrd v2, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f4
+; CHECK-BE-NEXT:    mffprwz r5, f4
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    lxv vs1, 0(r4)
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mtvsrd v3, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f6
+; CHECK-BE-NEXT:    mffprwz r5, f6
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    lxv vs0, 112(r4)
 ; CHECK-BE-NEXT:    vmrghh v2, v2, v3
 ; CHECK-BE-NEXT:    mtvsrd v3, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f3
+; CHECK-BE-NEXT:    mffprwz r5, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v4, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f7
+; CHECK-BE-NEXT:    mffprwz r5, f7
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    vmrghh v3, v3, v4
 ; CHECK-BE-NEXT:    mtvsrd v4, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f4
+; CHECK-BE-NEXT:    mffprwz r5, f4
 ; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    mtvsrd v5, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f3
+; CHECK-BE-NEXT:    mffprwz r5, f3
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    mtvsrd v0, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f2
+; CHECK-BE-NEXT:    mffprwz r5, f2
 ; CHECK-BE-NEXT:    lxv vs2, 96(r4)
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    mtvsrd v1, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f1
+; CHECK-BE-NEXT:    mffprwz r5, f1
 ; CHECK-BE-NEXT:    lxv vs1, 80(r4)
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
@@ -585,34 +585,34 @@
 ; CHECK-BE-NEXT:    mtvsrd v1, r5
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    vmrghh v5, v5, v1
-; CHECK-BE-NEXT:    mfvsrwz r5, f0
+; CHECK-BE-NEXT:    mffprwz r5, f0
 ; CHECK-BE-NEXT:    lxv vs0, 64(r4)
-; CHECK-BE-NEXT:    mfvsrwz r4, f3
+; CHECK-BE-NEXT:    mffprwz r4, f3
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    vmrghw v3, v5, v4
 ; CHECK-BE-NEXT:    xxmrghd vs3, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v2, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f2
+; CHECK-BE-NEXT:    mffprwz r4, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mtvsrd v3, r4
 ; CHECK-BE-NEXT:    vmrghh v2, v2, v3
-; CHECK-BE-NEXT:    mfvsrwz r4, f2
+; CHECK-BE-NEXT:    mffprwz r4, f2
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    mtvsrd v3, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f1
+; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v4, r4
 ; CHECK-BE-NEXT:    vmrghh v3, v3, v4
-; CHECK-BE-NEXT:    mfvsrwz r4, f1
+; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    mtvsrd v4, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f0
+; CHECK-BE-NEXT:    mffprwz r4, f0
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    mtvsrd v1, r5
 ; CHECK-BE-NEXT:    vmrghh v0, v0, v1
@@ -638,27 +638,27 @@
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mffprwz r3, f1
+; CHECK-P8-NEXT:    mffprwz r4, f0
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xxswapd v3, vs1
 ; CHECK-P8-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xscvdpsxws f0, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
@@ -668,12 +668,12 @@
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpsxws f0, v2
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
@@ -698,23 +698,23 @@
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r3, f2
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
-; CHECK-P8-NEXT:    mtvsrd f3, r4
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r3, f2
+; CHECK-P8-NEXT:    mffprwz r4, f3
+; CHECK-P8-NEXT:    mtfprd f2, r3
+; CHECK-P8-NEXT:    mtfprd f3, r4
+; CHECK-P8-NEXT:    mffprwz r3, f0
 ; CHECK-P8-NEXT:    xxswapd v2, vs2
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    mffprwz r4, f1
 ; CHECK-P8-NEXT:    xxswapd v4, vs3
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    xxswapd v5, vs1
 ; CHECK-P8-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P8-NEXT:    vmrglh v3, v5, v4
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt_signed:
@@ -724,19 +724,19 @@
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    lxv vs0, 16(r3)
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
 ; CHECK-P9-NEXT:    xxswapd v2, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xxswapd v4, vs0
@@ -752,20 +752,20 @@
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    vmrghh v2, v2, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghh v3, v3, v4
@@ -799,30 +799,30 @@
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r3, f4
+; CHECK-P8-NEXT:    mffprwz r3, f4
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    mtvsrd f4, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f6
-; CHECK-P8-NEXT:    mtvsrd f5, r4
+; CHECK-P8-NEXT:    mffprwz r4, f5
+; CHECK-P8-NEXT:    mtfprd f4, r3
+; CHECK-P8-NEXT:    mffprwz r3, f6
+; CHECK-P8-NEXT:    mtfprd f5, r4
 ; CHECK-P8-NEXT:    xxswapd v2, vs4
-; CHECK-P8-NEXT:    mfvsrwz r4, f7
-; CHECK-P8-NEXT:    mtvsrd f6, r3
+; CHECK-P8-NEXT:    mffprwz r4, f7
+; CHECK-P8-NEXT:    mtfprd f6, r3
 ; CHECK-P8-NEXT:    xxswapd v3, vs5
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mtvsrd f7, r4
+; CHECK-P8-NEXT:    mffprwz r3, f0
+; CHECK-P8-NEXT:    mtfprd f7, r4
 ; CHECK-P8-NEXT:    xxswapd v4, vs6
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mffprwz r4, f1
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v1, vs7
-; CHECK-P8-NEXT:    mfvsrwz r3, f2
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mffprwz r3, f2
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v5, vs0
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
+; CHECK-P8-NEXT:    mffprwz r4, f3
+; CHECK-P8-NEXT:    mtfprd f2, r3
 ; CHECK-P8-NEXT:    xxswapd v0, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    xxswapd v6, vs2
 ; CHECK-P8-NEXT:    vmrglh v2, v5, v2
 ; CHECK-P8-NEXT:    xxswapd v5, vs0
@@ -843,40 +843,40 @@
 ; CHECK-P9-NEXT:    lxv vs0, 48(r3)
 ; CHECK-P9-NEXT:    lxv vs1, 32(r3)
 ; CHECK-P9-NEXT:    lxv vs2, 16(r3)
-; CHECK-P9-NEXT:    mfvsrwz r3, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
+; CHECK-P9-NEXT:    mffprwz r3, f4
+; CHECK-P9-NEXT:    mtfprd f4, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
 ; CHECK-P9-NEXT:    xxswapd v2, vs4
-; CHECK-P9-NEXT:    mtvsrd f3, r3
+; CHECK-P9-NEXT:    mtfprd f3, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
+; CHECK-P9-NEXT:    mtfprd f3, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
 ; CHECK-P9-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    vmrglh v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglh v3, v3, v4
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxswapd v5, vs0
@@ -894,41 +894,41 @@
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
-; CHECK-BE-NEXT:    mfvsrwz r3, f4
+; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    vmrghh v2, v2, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghh v3, v3, v4
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghh v3, v3, v4
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 48
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    vmrghh v4, v4, v5
@@ -973,63 +973,63 @@
 ; CHECK-P8-NEXT:    xxswapd vs7, vs7
 ; CHECK-P8-NEXT:    xscvdpsxws v2, f9
 ; CHECK-P8-NEXT:    xxswapd vs9, vs9
-; CHECK-P8-NEXT:    mfvsrwz r4, f4
+; CHECK-P8-NEXT:    mffprwz r4, f4
 ; CHECK-P8-NEXT:    xscvdpsxws v3, f11
 ; CHECK-P8-NEXT:    xxswapd vs11, vs11
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r6, f6
-; CHECK-P8-NEXT:    mtvsrd f4, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f8
+; CHECK-P8-NEXT:    mffprwz r6, f6
+; CHECK-P8-NEXT:    mtfprd f4, r4
+; CHECK-P8-NEXT:    mffprwz r4, f8
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    xxswapd v4, vs4
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
-; CHECK-P8-NEXT:    mtvsrd f6, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f10
-; CHECK-P8-NEXT:    mtvsrd f8, r4
+; CHECK-P8-NEXT:    mtfprd f6, r6
+; CHECK-P8-NEXT:    mffprwz r6, f10
+; CHECK-P8-NEXT:    mtfprd f8, r4
 ; CHECK-P8-NEXT:    xxswapd v5, vs6
-; CHECK-P8-NEXT:    mfvsrwz r4, f12
+; CHECK-P8-NEXT:    mffprwz r4, f12
 ; CHECK-P8-NEXT:    xscvdpsxws f5, f5
 ; CHECK-P8-NEXT:    xxswapd v0, vs8
-; CHECK-P8-NEXT:    mtvsrd f10, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f13
-; CHECK-P8-NEXT:    mtvsrd f12, r4
+; CHECK-P8-NEXT:    mtfprd f10, r6
+; CHECK-P8-NEXT:    mffprwz r6, f13
+; CHECK-P8-NEXT:    mtfprd f12, r4
 ; CHECK-P8-NEXT:    xxswapd v1, vs10
 ; CHECK-P8-NEXT:    mfvsrwz r4, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    xxswapd v6, vs12
 ; CHECK-P8-NEXT:    xscvdpsxws f9, f9
-; CHECK-P8-NEXT:    mtvsrd f13, r6
+; CHECK-P8-NEXT:    mtfprd f13, r6
 ; CHECK-P8-NEXT:    mfvsrwz r6, v3
 ; CHECK-P8-NEXT:    mtvsrd v2, r4
 ; CHECK-P8-NEXT:    xxswapd v7, vs13
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
+; CHECK-P8-NEXT:    mffprwz r4, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f7, f7
 ; CHECK-P8-NEXT:    xxswapd v2, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f11, f11
 ; CHECK-P8-NEXT:    mtvsrd v3, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f1
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mffprwz r6, f1
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    xxswapd v3, v3
-; CHECK-P8-NEXT:    mfvsrwz r4, f2
-; CHECK-P8-NEXT:    mtvsrd f1, r6
+; CHECK-P8-NEXT:    mffprwz r4, f2
+; CHECK-P8-NEXT:    mtfprd f1, r6
 ; CHECK-P8-NEXT:    xxswapd v8, vs0
-; CHECK-P8-NEXT:    mtvsrd f2, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
+; CHECK-P8-NEXT:    mtfprd f2, r4
+; CHECK-P8-NEXT:    mffprwz r4, f5
 ; CHECK-P8-NEXT:    xxswapd v9, vs1
-; CHECK-P8-NEXT:    mfvsrwz r6, f3
+; CHECK-P8-NEXT:    mffprwz r6, f3
 ; CHECK-P8-NEXT:    xxswapd v10, vs2
-; CHECK-P8-NEXT:    mtvsrd f5, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f9
-; CHECK-P8-NEXT:    mtvsrd f3, r6
-; CHECK-P8-NEXT:    mfvsrwz r6, f7
-; CHECK-P8-NEXT:    mtvsrd f9, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f11
+; CHECK-P8-NEXT:    mtfprd f5, r4
+; CHECK-P8-NEXT:    mffprwz r4, f9
+; CHECK-P8-NEXT:    mtfprd f3, r6
+; CHECK-P8-NEXT:    mffprwz r6, f7
+; CHECK-P8-NEXT:    mtfprd f9, r4
+; CHECK-P8-NEXT:    mffprwz r4, f11
 ; CHECK-P8-NEXT:    vmrglh v4, v8, v4
 ; CHECK-P8-NEXT:    xxswapd v8, vs3
 ; CHECK-P8-NEXT:    vmrglh v5, v9, v5
 ; CHECK-P8-NEXT:    xxswapd v9, vs5
-; CHECK-P8-NEXT:    mtvsrd f7, r6
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mtfprd f7, r6
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    vmrglh v0, v10, v0
 ; CHECK-P8-NEXT:    xxswapd v10, vs7
 ; CHECK-P8-NEXT:    vmrglh v1, v8, v1
@@ -1062,32 +1062,32 @@
 ; CHECK-P9-NEXT:    xscvdpsxws f8, f1
 ; CHECK-P9-NEXT:    xxswapd vs4, vs4
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f4
-; CHECK-P9-NEXT:    mfvsrwz r5, f5
+; CHECK-P9-NEXT:    mffprwz r5, f5
 ; CHECK-P9-NEXT:    xscvdpsxws f9, f0
 ; CHECK-P9-NEXT:    xxswapd vs3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f3
-; CHECK-P9-NEXT:    mtvsrd f5, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f6
+; CHECK-P9-NEXT:    mtfprd f5, r5
+; CHECK-P9-NEXT:    mffprwz r5, f6
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mtvsrd f6, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f7
-; CHECK-P9-NEXT:    mtvsrd f7, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f8
-; CHECK-P9-NEXT:    mtvsrd f8, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f9
-; CHECK-P9-NEXT:    mtvsrd f9, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f3
+; CHECK-P9-NEXT:    mtfprd f6, r5
+; CHECK-P9-NEXT:    mffprwz r5, f7
+; CHECK-P9-NEXT:    mtfprd f7, r5
+; CHECK-P9-NEXT:    mffprwz r5, f8
+; CHECK-P9-NEXT:    mtfprd f8, r5
+; CHECK-P9-NEXT:    mffprwz r5, f9
+; CHECK-P9-NEXT:    mtfprd f9, r5
+; CHECK-P9-NEXT:    mffprwz r5, f4
+; CHECK-P9-NEXT:    mtfprd f4, r5
+; CHECK-P9-NEXT:    mffprwz r5, f3
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    xxswapd v2, vs5
 ; CHECK-P9-NEXT:    xxswapd v5, vs8
 ; CHECK-P9-NEXT:    xxswapd v0, vs9
-; CHECK-P9-NEXT:    mtvsrd f3, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r5
+; CHECK-P9-NEXT:    mtfprd f3, r5
+; CHECK-P9-NEXT:    mffprwz r5, f2
+; CHECK-P9-NEXT:    mtfprd f2, r5
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    xxswapd v1, vs2
@@ -1098,49 +1098,49 @@
 ; CHECK-P9-NEXT:    xxswapd v4, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
-; CHECK-P9-NEXT:    mfvsrwz r5, f1
+; CHECK-P9-NEXT:    mffprwz r5, f1
 ; CHECK-P9-NEXT:    vmrglh v3, v3, v4
 ; CHECK-P9-NEXT:    xxswapd v4, vs7
-; CHECK-P9-NEXT:    mtvsrd f1, r5
-; CHECK-P9-NEXT:    mfvsrwz r5, f0
+; CHECK-P9-NEXT:    mtfprd f1, r5
+; CHECK-P9-NEXT:    mffprwz r5, f0
 ; CHECK-P9-NEXT:    vmrglh v4, v4, v1
 ; CHECK-P9-NEXT:    xxswapd v1, vs1
-; CHECK-P9-NEXT:    mtvsrd f0, r5
+; CHECK-P9-NEXT:    mtfprd f0, r5
 ; CHECK-P9-NEXT:    vmrglh v5, v5, v1
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P9-NEXT:    xxswapd v1, vs0
 ; CHECK-P9-NEXT:    lxv vs0, 112(r4)
 ; CHECK-P9-NEXT:    lxv vs1, 96(r4)
-; CHECK-P9-NEXT:    mfvsrwz r4, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r4
-; CHECK-P9-NEXT:    mfvsrwz r4, f2
+; CHECK-P9-NEXT:    mffprwz r4, f3
+; CHECK-P9-NEXT:    mtfprd f3, r4
+; CHECK-P9-NEXT:    mffprwz r4, f2
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    vmrglw v3, v5, v4
 ; CHECK-P9-NEXT:    xxmrgld vs4, v3, v2
 ; CHECK-P9-NEXT:    xxswapd v2, vs3
 ; CHECK-P9-NEXT:    vmrglh v0, v0, v1
-; CHECK-P9-NEXT:    mtvsrd f2, r4
+; CHECK-P9-NEXT:    mtfprd f2, r4
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r4, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r4
-; CHECK-P9-NEXT:    mfvsrwz r4, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r4
+; CHECK-P9-NEXT:    mffprwz r4, f2
+; CHECK-P9-NEXT:    mtfprd f2, r4
+; CHECK-P9-NEXT:    mffprwz r4, f1
+; CHECK-P9-NEXT:    mtfprd f1, r4
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r4, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r4
-; CHECK-P9-NEXT:    mfvsrwz r4, f0
+; CHECK-P9-NEXT:    mffprwz r4, f1
+; CHECK-P9-NEXT:    mtfprd f1, r4
+; CHECK-P9-NEXT:    mffprwz r4, f0
 ; CHECK-P9-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
 ; CHECK-P9-NEXT:    vmrglh v3, v3, v4
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v0
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    xxswapd v5, vs0
 ; CHECK-P9-NEXT:    vmrglh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
@@ -1158,7 +1158,7 @@
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    mfvsrwz r5, f5
+; CHECK-BE-NEXT:    mffprwz r5, f5
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    lxv vs2, 16(r4)
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
@@ -1166,40 +1166,40 @@
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mtvsrd v2, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f4
+; CHECK-BE-NEXT:    mffprwz r5, f4
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    lxv vs1, 0(r4)
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mtvsrd v3, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f6
+; CHECK-BE-NEXT:    mffprwz r5, f6
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    lxv vs0, 112(r4)
 ; CHECK-BE-NEXT:    vmrghh v2, v2, v3
 ; CHECK-BE-NEXT:    mtvsrd v3, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f3
+; CHECK-BE-NEXT:    mffprwz r5, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v4, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f7
+; CHECK-BE-NEXT:    mffprwz r5, f7
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    vmrghh v3, v3, v4
 ; CHECK-BE-NEXT:    mtvsrd v4, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f4
+; CHECK-BE-NEXT:    mffprwz r5, f4
 ; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    mtvsrd v5, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f3
+; CHECK-BE-NEXT:    mffprwz r5, f3
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    mtvsrd v0, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f2
+; CHECK-BE-NEXT:    mffprwz r5, f2
 ; CHECK-BE-NEXT:    lxv vs2, 96(r4)
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    mtvsrd v1, r5
-; CHECK-BE-NEXT:    mfvsrwz r5, f1
+; CHECK-BE-NEXT:    mffprwz r5, f1
 ; CHECK-BE-NEXT:    lxv vs1, 80(r4)
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
@@ -1208,34 +1208,34 @@
 ; CHECK-BE-NEXT:    mtvsrd v1, r5
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    vmrghh v5, v5, v1
-; CHECK-BE-NEXT:    mfvsrwz r5, f0
+; CHECK-BE-NEXT:    mffprwz r5, f0
 ; CHECK-BE-NEXT:    lxv vs0, 64(r4)
-; CHECK-BE-NEXT:    mfvsrwz r4, f3
+; CHECK-BE-NEXT:    mffprwz r4, f3
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    vmrghw v3, v5, v4
 ; CHECK-BE-NEXT:    xxmrghd vs3, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v2, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f2
+; CHECK-BE-NEXT:    mffprwz r4, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mtvsrd v3, r4
 ; CHECK-BE-NEXT:    vmrghh v2, v2, v3
-; CHECK-BE-NEXT:    mfvsrwz r4, f2
+; CHECK-BE-NEXT:    mffprwz r4, f2
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    mtvsrd v3, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f1
+; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v4, r4
 ; CHECK-BE-NEXT:    vmrghh v3, v3, v4
-; CHECK-BE-NEXT:    mfvsrwz r4, f1
+; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    sldi r4, r4, 48
 ; CHECK-BE-NEXT:    mtvsrd v4, r4
-; CHECK-BE-NEXT:    mfvsrwz r4, f0
+; CHECK-BE-NEXT:    mffprwz r4, f0
 ; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    mtvsrd v1, r5
 ; CHECK-BE-NEXT:    vmrghh v0, v0, v1
diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
--- a/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
@@ -15,15 +15,15 @@
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    xscvdpuxws f1, v2
 ; CHECK-P8-NEXT:    xscvdpuxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mffprwz r3, f1
+; CHECK-P8-NEXT:    mffprwz r4, f0
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xxswapd v3, vs1
 ; CHECK-P8-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
@@ -309,15 +309,15 @@
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mffprwz r3, f1
+; CHECK-P8-NEXT:    mffprwz r4, f0
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xxswapd v3, vs1
 ; CHECK-P8-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll
--- a/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll
@@ -15,15 +15,15 @@
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mffprwz r3, f1
+; CHECK-P8-NEXT:    mffprwz r4, f0
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xxswapd v3, vs1
 ; CHECK-P8-NEXT:    vmrglb v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    clrldi r3, r3, 48
 ; CHECK-P8-NEXT:    sth r3, -2(r1)
 ; CHECK-P8-NEXT:    lhz r3, -2(r1)
@@ -32,13 +32,13 @@
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xscvdpsxws f0, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    addi r3, r1, -2
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    vmrglb v2, v3, v2
@@ -50,12 +50,12 @@
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpsxws f0, v2
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -2
@@ -82,23 +82,23 @@
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r3, f2
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
-; CHECK-P8-NEXT:    mtvsrd f3, r4
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r3, f2
+; CHECK-P8-NEXT:    mffprwz r4, f3
+; CHECK-P8-NEXT:    mtfprd f2, r3
+; CHECK-P8-NEXT:    mtfprd f3, r4
+; CHECK-P8-NEXT:    mffprwz r3, f0
 ; CHECK-P8-NEXT:    xxswapd v2, vs2
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    mffprwz r4, f1
 ; CHECK-P8-NEXT:    xxswapd v4, vs3
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    xxswapd v5, vs1
 ; CHECK-P8-NEXT:    vmrglb v2, v3, v2
 ; CHECK-P8-NEXT:    vmrglb v3, v5, v4
 ; CHECK-P8-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt:
@@ -108,19 +108,19 @@
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    lxv vs0, 16(r3)
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
 ; CHECK-P9-NEXT:    xxswapd v2, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglb v2, v2, v3
 ; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xxswapd v4, vs0
@@ -137,20 +137,20 @@
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    vmrghb v2, v2, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    li r3, 0
@@ -185,30 +185,30 @@
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r3, f4
+; CHECK-P8-NEXT:    mffprwz r3, f4
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    mtvsrd f4, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f6
-; CHECK-P8-NEXT:    mtvsrd f5, r4
+; CHECK-P8-NEXT:    mffprwz r4, f5
+; CHECK-P8-NEXT:    mtfprd f4, r3
+; CHECK-P8-NEXT:    mffprwz r3, f6
+; CHECK-P8-NEXT:    mtfprd f5, r4
 ; CHECK-P8-NEXT:    xxswapd v2, vs4
-; CHECK-P8-NEXT:    mfvsrwz r4, f7
-; CHECK-P8-NEXT:    mtvsrd f6, r3
+; CHECK-P8-NEXT:    mffprwz r4, f7
+; CHECK-P8-NEXT:    mtfprd f6, r3
 ; CHECK-P8-NEXT:    xxswapd v3, vs5
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mtvsrd f7, r4
+; CHECK-P8-NEXT:    mffprwz r3, f0
+; CHECK-P8-NEXT:    mtfprd f7, r4
 ; CHECK-P8-NEXT:    xxswapd v4, vs6
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mffprwz r4, f1
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v1, vs7
-; CHECK-P8-NEXT:    mfvsrwz r3, f2
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mffprwz r3, f2
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v5, vs0
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
+; CHECK-P8-NEXT:    mffprwz r4, f3
+; CHECK-P8-NEXT:    mtfprd f2, r3
 ; CHECK-P8-NEXT:    xxswapd v0, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    xxswapd v6, vs2
 ; CHECK-P8-NEXT:    vmrglb v2, v5, v2
 ; CHECK-P8-NEXT:    xxswapd v5, vs0
@@ -219,7 +219,7 @@
 ; CHECK-P8-NEXT:    vmrglh v3, v5, v4
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt:
@@ -231,40 +231,40 @@
 ; CHECK-P9-NEXT:    lxv vs0, 48(r3)
 ; CHECK-P9-NEXT:    lxv vs1, 32(r3)
 ; CHECK-P9-NEXT:    lxv vs2, 16(r3)
-; CHECK-P9-NEXT:    mfvsrwz r3, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
+; CHECK-P9-NEXT:    mffprwz r3, f4
+; CHECK-P9-NEXT:    mtfprd f4, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
 ; CHECK-P9-NEXT:    xxswapd v2, vs4
-; CHECK-P9-NEXT:    mtvsrd f3, r3
+; CHECK-P9-NEXT:    mtfprd f3, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
+; CHECK-P9-NEXT:    mtfprd f3, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
 ; CHECK-P9-NEXT:    vmrglb v2, v2, v3
 ; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    vmrglb v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglb v3, v3, v4
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxswapd v5, vs0
@@ -283,41 +283,41 @@
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
-; CHECK-BE-NEXT:    mfvsrwz r3, f4
+; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    vmrghb v2, v2, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghb v3, v3, v4
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghb v3, v3, v4
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    vmrghb v4, v4, v5
@@ -364,63 +364,63 @@
 ; CHECK-P8-NEXT:    xxswapd vs7, vs7
 ; CHECK-P8-NEXT:    xscvdpsxws v2, f9
 ; CHECK-P8-NEXT:    xxswapd vs9, vs9
-; CHECK-P8-NEXT:    mfvsrwz r3, f4
+; CHECK-P8-NEXT:    mffprwz r3, f4
 ; CHECK-P8-NEXT:    xscvdpsxws v3, f11
 ; CHECK-P8-NEXT:    xxswapd vs11, vs11
-; CHECK-P8-NEXT:    mfvsrwz r4, f6
+; CHECK-P8-NEXT:    mffprwz r4, f6
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mtvsrd f4, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f8
+; CHECK-P8-NEXT:    mtfprd f4, r3
+; CHECK-P8-NEXT:    mffprwz r3, f8
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    xxswapd v4, vs4
-; CHECK-P8-NEXT:    mtvsrd f6, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f10
+; CHECK-P8-NEXT:    mtfprd f6, r4
+; CHECK-P8-NEXT:    mffprwz r4, f10
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xxswapd v5, vs6
-; CHECK-P8-NEXT:    mtvsrd f8, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f12
+; CHECK-P8-NEXT:    mtfprd f8, r3
+; CHECK-P8-NEXT:    mffprwz r3, f12
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    xxswapd v0, vs8
-; CHECK-P8-NEXT:    mtvsrd f10, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f13
+; CHECK-P8-NEXT:    mtfprd f10, r4
+; CHECK-P8-NEXT:    mffprwz r4, f13
 ; CHECK-P8-NEXT:    xscvdpsxws f5, f5
 ; CHECK-P8-NEXT:    xxswapd v1, vs10
-; CHECK-P8-NEXT:    mtvsrd f12, r3
+; CHECK-P8-NEXT:    mtfprd f12, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f7, f7
 ; CHECK-P8-NEXT:    xxswapd v6, vs12
-; CHECK-P8-NEXT:    mtvsrd f13, r4
+; CHECK-P8-NEXT:    mtfprd f13, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, v3
 ; CHECK-P8-NEXT:    mtvsrd v2, r3
 ; CHECK-P8-NEXT:    xxswapd v7, vs13
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r3, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f9, f9
 ; CHECK-P8-NEXT:    xxswapd v2, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f11, f11
 ; CHECK-P8-NEXT:    mtvsrd v3, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mffprwz r4, f1
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v3, v3
-; CHECK-P8-NEXT:    mfvsrwz r3, f2
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mffprwz r3, f2
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v8, vs0
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
+; CHECK-P8-NEXT:    mffprwz r4, f3
+; CHECK-P8-NEXT:    mtfprd f2, r3
 ; CHECK-P8-NEXT:    xxswapd v9, vs1
-; CHECK-P8-NEXT:    mfvsrwz r3, f5
-; CHECK-P8-NEXT:    mtvsrd f3, r4
+; CHECK-P8-NEXT:    mffprwz r3, f5
+; CHECK-P8-NEXT:    mtfprd f3, r4
 ; CHECK-P8-NEXT:    xxswapd v10, vs2
-; CHECK-P8-NEXT:    mfvsrwz r4, f7
-; CHECK-P8-NEXT:    mtvsrd f5, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f9
-; CHECK-P8-NEXT:    mtvsrd f7, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f11
+; CHECK-P8-NEXT:    mffprwz r4, f7
+; CHECK-P8-NEXT:    mtfprd f5, r3
+; CHECK-P8-NEXT:    mffprwz r3, f9
+; CHECK-P8-NEXT:    mtfprd f7, r4
+; CHECK-P8-NEXT:    mffprwz r4, f11
 ; CHECK-P8-NEXT:    vmrglb v4, v8, v4
 ; CHECK-P8-NEXT:    xxswapd v8, vs3
 ; CHECK-P8-NEXT:    vmrglb v5, v9, v5
 ; CHECK-P8-NEXT:    xxswapd v9, vs5
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    vmrglb v0, v10, v0
 ; CHECK-P8-NEXT:    xxswapd v10, vs7
 ; CHECK-P8-NEXT:    vmrglb v1, v8, v1
@@ -452,40 +452,40 @@
 ; CHECK-P9-NEXT:    lxv vs4, 48(r3)
 ; CHECK-P9-NEXT:    lxv vs5, 32(r3)
 ; CHECK-P9-NEXT:    lxv vs6, 16(r3)
-; CHECK-P9-NEXT:    mfvsrwz r3, f8
-; CHECK-P9-NEXT:    mtvsrd f8, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f7
+; CHECK-P9-NEXT:    mffprwz r3, f8
+; CHECK-P9-NEXT:    mtfprd f8, r3
+; CHECK-P9-NEXT:    mffprwz r3, f7
 ; CHECK-P9-NEXT:    xxswapd v2, vs8
-; CHECK-P9-NEXT:    mtvsrd f7, r3
+; CHECK-P9-NEXT:    mtfprd f7, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs7
 ; CHECK-P9-NEXT:    xscvdpsxws f7, f6
 ; CHECK-P9-NEXT:    xxswapd vs6, vs6
 ; CHECK-P9-NEXT:    xscvdpsxws f6, f6
-; CHECK-P9-NEXT:    mfvsrwz r3, f7
-; CHECK-P9-NEXT:    mtvsrd f7, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f6
-; CHECK-P9-NEXT:    mtvsrd f6, r3
+; CHECK-P9-NEXT:    mffprwz r3, f7
+; CHECK-P9-NEXT:    mtfprd f7, r3
+; CHECK-P9-NEXT:    mffprwz r3, f6
+; CHECK-P9-NEXT:    mtfprd f6, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs6
 ; CHECK-P9-NEXT:    xscvdpsxws f6, f5
 ; CHECK-P9-NEXT:    xxswapd vs5, vs5
 ; CHECK-P9-NEXT:    xscvdpsxws f5, f5
-; CHECK-P9-NEXT:    mfvsrwz r3, f6
-; CHECK-P9-NEXT:    mtvsrd f6, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f5
+; CHECK-P9-NEXT:    mffprwz r3, f6
+; CHECK-P9-NEXT:    mtfprd f6, r3
+; CHECK-P9-NEXT:    mffprwz r3, f5
 ; CHECK-P9-NEXT:    vmrglb v2, v2, v3
 ; CHECK-P9-NEXT:    xxswapd v3, vs7
 ; CHECK-P9-NEXT:    vmrglb v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P9-NEXT:    xxswapd v3, vs6
-; CHECK-P9-NEXT:    mtvsrd f5, r3
+; CHECK-P9-NEXT:    mtfprd f5, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs5
 ; CHECK-P9-NEXT:    xscvdpsxws f5, f4
 ; CHECK-P9-NEXT:    xxswapd vs4, vs4
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f4
-; CHECK-P9-NEXT:    mfvsrwz r3, f5
-; CHECK-P9-NEXT:    mtvsrd f5, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r3
+; CHECK-P9-NEXT:    mffprwz r3, f5
+; CHECK-P9-NEXT:    mtfprd f5, r3
+; CHECK-P9-NEXT:    mffprwz r3, f4
+; CHECK-P9-NEXT:    mtfprd f4, r3
 ; CHECK-P9-NEXT:    xxswapd v5, vs4
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f3
 ; CHECK-P9-NEXT:    xxswapd vs3, vs3
@@ -494,18 +494,18 @@
 ; CHECK-P9-NEXT:    xxswapd v4, vs5
 ; CHECK-P9-NEXT:    vmrglb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
-; CHECK-P9-NEXT:    mfvsrwz r3, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
+; CHECK-P9-NEXT:    mffprwz r3, f4
+; CHECK-P9-NEXT:    mtfprd f4, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
+; CHECK-P9-NEXT:    mtfprd f3, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
+; CHECK-P9-NEXT:    mtfprd f3, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v5, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
@@ -516,19 +516,19 @@
 ; CHECK-P9-NEXT:    xxswapd v4, vs3
 ; CHECK-P9-NEXT:    vmrglb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v5, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglb v4, v4, v5
 ; CHECK-P9-NEXT:    xxswapd v5, vs1
 ; CHECK-P9-NEXT:    xxswapd v0, vs0
@@ -551,84 +551,84 @@
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs4, 64(r3)
 ; CHECK-BE-NEXT:    lxv vs5, 80(r3)
-; CHECK-BE-NEXT:    mfvsrwz r3, f8
+; CHECK-BE-NEXT:    mffprwz r3, f8
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f7
+; CHECK-BE-NEXT:    mffprwz r3, f7
 ; CHECK-BE-NEXT:    xscvdpsxws f7, f6
 ; CHECK-BE-NEXT:    xxswapd vs6, vs6
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f6
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    vmrghb v2, v2, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f7
+; CHECK-BE-NEXT:    mffprwz r3, f7
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f6
+; CHECK-BE-NEXT:    mffprwz r3, f6
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f5
 ; CHECK-BE-NEXT:    xxswapd vs5, vs5
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f5
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghb v3, v3, v4
-; CHECK-BE-NEXT:    mfvsrwz r3, f6
+; CHECK-BE-NEXT:    mffprwz r3, f6
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f5
+; CHECK-BE-NEXT:    mffprwz r3, f5
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f4
 ; CHECK-BE-NEXT:    xxswapd vs4, vs4
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghb v3, v3, v4
-; CHECK-BE-NEXT:    mfvsrwz r3, f5
+; CHECK-BE-NEXT:    mffprwz r3, f5
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f4
+; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    vmrghb v4, v4, v5
-; CHECK-BE-NEXT:    mfvsrwz r3, f4
+; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    vmrghh v3, v4, v3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghb v3, v3, v4
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    vmrghb v4, v4, v5
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    vmrghh v3, v4, v3
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    vmrghb v4, v4, v5
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v0, r3
 ; CHECK-BE-NEXT:    vmrghb v5, v5, v0
@@ -648,15 +648,15 @@
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f1, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mfvsrwz r3, f1
-; CHECK-P8-NEXT:    mfvsrwz r4, f0
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mffprwz r3, f1
+; CHECK-P8-NEXT:    mffprwz r4, f0
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xxswapd v3, vs1
 ; CHECK-P8-NEXT:    vmrglb v2, v2, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    clrldi r3, r3, 48
 ; CHECK-P8-NEXT:    sth r3, -2(r1)
 ; CHECK-P8-NEXT:    lhz r3, -2(r1)
@@ -665,13 +665,13 @@
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xscvdpsxws f0, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    addi r3, r1, -2
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    vmrglb v2, v3, v2
@@ -683,12 +683,12 @@
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpsxws f0, v2
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -2
@@ -715,23 +715,23 @@
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r3, f2
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
-; CHECK-P8-NEXT:    mtvsrd f3, r4
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r3, f2
+; CHECK-P8-NEXT:    mffprwz r4, f3
+; CHECK-P8-NEXT:    mtfprd f2, r3
+; CHECK-P8-NEXT:    mtfprd f3, r4
+; CHECK-P8-NEXT:    mffprwz r3, f0
 ; CHECK-P8-NEXT:    xxswapd v2, vs2
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
+; CHECK-P8-NEXT:    mffprwz r4, f1
 ; CHECK-P8-NEXT:    xxswapd v4, vs3
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    xxswapd v5, vs1
 ; CHECK-P8-NEXT:    vmrglb v2, v3, v2
 ; CHECK-P8-NEXT:    vmrglb v3, v5, v4
 ; CHECK-P8-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt_signed:
@@ -741,19 +741,19 @@
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P9-NEXT:    lxv vs0, 16(r3)
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
 ; CHECK-P9-NEXT:    xxswapd v2, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglb v2, v2, v3
 ; CHECK-P9-NEXT:    xxswapd v3, vs1
 ; CHECK-P9-NEXT:    xxswapd v4, vs0
@@ -770,20 +770,20 @@
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    vmrghb v2, v2, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    li r3, 0
@@ -818,30 +818,30 @@
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
-; CHECK-P8-NEXT:    mfvsrwz r3, f4
+; CHECK-P8-NEXT:    mffprwz r3, f4
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
-; CHECK-P8-NEXT:    mfvsrwz r4, f5
-; CHECK-P8-NEXT:    mtvsrd f4, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f6
-; CHECK-P8-NEXT:    mtvsrd f5, r4
+; CHECK-P8-NEXT:    mffprwz r4, f5
+; CHECK-P8-NEXT:    mtfprd f4, r3
+; CHECK-P8-NEXT:    mffprwz r3, f6
+; CHECK-P8-NEXT:    mtfprd f5, r4
 ; CHECK-P8-NEXT:    xxswapd v2, vs4
-; CHECK-P8-NEXT:    mfvsrwz r4, f7
-; CHECK-P8-NEXT:    mtvsrd f6, r3
+; CHECK-P8-NEXT:    mffprwz r4, f7
+; CHECK-P8-NEXT:    mtfprd f6, r3
 ; CHECK-P8-NEXT:    xxswapd v3, vs5
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
-; CHECK-P8-NEXT:    mtvsrd f7, r4
+; CHECK-P8-NEXT:    mffprwz r3, f0
+; CHECK-P8-NEXT:    mtfprd f7, r4
 ; CHECK-P8-NEXT:    xxswapd v4, vs6
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mffprwz r4, f1
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v1, vs7
-; CHECK-P8-NEXT:    mfvsrwz r3, f2
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mffprwz r3, f2
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v5, vs0
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
+; CHECK-P8-NEXT:    mffprwz r4, f3
+; CHECK-P8-NEXT:    mtfprd f2, r3
 ; CHECK-P8-NEXT:    xxswapd v0, vs1
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    xxswapd v6, vs2
 ; CHECK-P8-NEXT:    vmrglb v2, v5, v2
 ; CHECK-P8-NEXT:    xxswapd v5, vs0
@@ -852,7 +852,7 @@
 ; CHECK-P8-NEXT:    vmrglh v3, v5, v4
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt_signed:
@@ -864,40 +864,40 @@
 ; CHECK-P9-NEXT:    lxv vs0, 48(r3)
 ; CHECK-P9-NEXT:    lxv vs1, 32(r3)
 ; CHECK-P9-NEXT:    lxv vs2, 16(r3)
-; CHECK-P9-NEXT:    mfvsrwz r3, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
+; CHECK-P9-NEXT:    mffprwz r3, f4
+; CHECK-P9-NEXT:    mtfprd f4, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
 ; CHECK-P9-NEXT:    xxswapd v2, vs4
-; CHECK-P9-NEXT:    mtvsrd f3, r3
+; CHECK-P9-NEXT:    mtfprd f3, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
+; CHECK-P9-NEXT:    mtfprd f3, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f1
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
 ; CHECK-P9-NEXT:    vmrglb v2, v2, v3
 ; CHECK-P9-NEXT:    xxswapd v3, vs3
 ; CHECK-P9-NEXT:    vmrglb v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P9-NEXT:    xxswapd v3, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglb v3, v3, v4
 ; CHECK-P9-NEXT:    xxswapd v4, vs1
 ; CHECK-P9-NEXT:    xxswapd v5, vs0
@@ -916,41 +916,41 @@
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
-; CHECK-BE-NEXT:    mfvsrwz r3, f4
+; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    vmrghb v2, v2, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghb v3, v3, v4
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghb v3, v3, v4
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    vmrghb v4, v4, v5
@@ -997,63 +997,63 @@
 ; CHECK-P8-NEXT:    xxswapd vs7, vs7
 ; CHECK-P8-NEXT:    xscvdpsxws v2, f9
 ; CHECK-P8-NEXT:    xxswapd vs9, vs9
-; CHECK-P8-NEXT:    mfvsrwz r3, f4
+; CHECK-P8-NEXT:    mffprwz r3, f4
 ; CHECK-P8-NEXT:    xscvdpsxws v3, f11
 ; CHECK-P8-NEXT:    xxswapd vs11, vs11
-; CHECK-P8-NEXT:    mfvsrwz r4, f6
+; CHECK-P8-NEXT:    mffprwz r4, f6
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
-; CHECK-P8-NEXT:    mtvsrd f4, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f8
+; CHECK-P8-NEXT:    mtfprd f4, r3
+; CHECK-P8-NEXT:    mffprwz r3, f8
 ; CHECK-P8-NEXT:    xscvdpsxws f1, f1
 ; CHECK-P8-NEXT:    xxswapd v4, vs4
-; CHECK-P8-NEXT:    mtvsrd f6, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f10
+; CHECK-P8-NEXT:    mtfprd f6, r4
+; CHECK-P8-NEXT:    mffprwz r4, f10
 ; CHECK-P8-NEXT:    xscvdpsxws f2, f2
 ; CHECK-P8-NEXT:    xxswapd v5, vs6
-; CHECK-P8-NEXT:    mtvsrd f8, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f12
+; CHECK-P8-NEXT:    mtfprd f8, r3
+; CHECK-P8-NEXT:    mffprwz r3, f12
 ; CHECK-P8-NEXT:    xscvdpsxws f3, f3
 ; CHECK-P8-NEXT:    xxswapd v0, vs8
-; CHECK-P8-NEXT:    mtvsrd f10, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f13
+; CHECK-P8-NEXT:    mtfprd f10, r4
+; CHECK-P8-NEXT:    mffprwz r4, f13
 ; CHECK-P8-NEXT:    xscvdpsxws f5, f5
 ; CHECK-P8-NEXT:    xxswapd v1, vs10
-; CHECK-P8-NEXT:    mtvsrd f12, r3
+; CHECK-P8-NEXT:    mtfprd f12, r3
 ; CHECK-P8-NEXT:    mfvsrwz r3, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f7, f7
 ; CHECK-P8-NEXT:    xxswapd v6, vs12
-; CHECK-P8-NEXT:    mtvsrd f13, r4
+; CHECK-P8-NEXT:    mtfprd f13, r4
 ; CHECK-P8-NEXT:    mfvsrwz r4, v3
 ; CHECK-P8-NEXT:    mtvsrd v2, r3
 ; CHECK-P8-NEXT:    xxswapd v7, vs13
-; CHECK-P8-NEXT:    mfvsrwz r3, f0
+; CHECK-P8-NEXT:    mffprwz r3, f0
 ; CHECK-P8-NEXT:    xscvdpsxws f9, f9
 ; CHECK-P8-NEXT:    xxswapd v2, v2
 ; CHECK-P8-NEXT:    xscvdpsxws f11, f11
 ; CHECK-P8-NEXT:    mtvsrd v3, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f1
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mffprwz r4, f1
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v3, v3
-; CHECK-P8-NEXT:    mfvsrwz r3, f2
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mffprwz r3, f2
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    xxswapd v8, vs0
-; CHECK-P8-NEXT:    mfvsrwz r4, f3
-; CHECK-P8-NEXT:    mtvsrd f2, r3
+; CHECK-P8-NEXT:    mffprwz r4, f3
+; CHECK-P8-NEXT:    mtfprd f2, r3
 ; CHECK-P8-NEXT:    xxswapd v9, vs1
-; CHECK-P8-NEXT:    mfvsrwz r3, f5
-; CHECK-P8-NEXT:    mtvsrd f3, r4
+; CHECK-P8-NEXT:    mffprwz r3, f5
+; CHECK-P8-NEXT:    mtfprd f3, r4
 ; CHECK-P8-NEXT:    xxswapd v10, vs2
-; CHECK-P8-NEXT:    mfvsrwz r4, f7
-; CHECK-P8-NEXT:    mtvsrd f5, r3
-; CHECK-P8-NEXT:    mfvsrwz r3, f9
-; CHECK-P8-NEXT:    mtvsrd f7, r4
-; CHECK-P8-NEXT:    mfvsrwz r4, f11
+; CHECK-P8-NEXT:    mffprwz r4, f7
+; CHECK-P8-NEXT:    mtfprd f5, r3
+; CHECK-P8-NEXT:    mffprwz r3, f9
+; CHECK-P8-NEXT:    mtfprd f7, r4
+; CHECK-P8-NEXT:    mffprwz r4, f11
 ; CHECK-P8-NEXT:    vmrglb v4, v8, v4
 ; CHECK-P8-NEXT:    xxswapd v8, vs3
 ; CHECK-P8-NEXT:    vmrglb v5, v9, v5
 ; CHECK-P8-NEXT:    xxswapd v9, vs5
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mtvsrd f1, r4
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mtfprd f1, r4
 ; CHECK-P8-NEXT:    vmrglb v0, v10, v0
 ; CHECK-P8-NEXT:    xxswapd v10, vs7
 ; CHECK-P8-NEXT:    vmrglb v1, v8, v1
@@ -1085,40 +1085,40 @@
 ; CHECK-P9-NEXT:    lxv vs4, 48(r3)
 ; CHECK-P9-NEXT:    lxv vs5, 32(r3)
 ; CHECK-P9-NEXT:    lxv vs6, 16(r3)
-; CHECK-P9-NEXT:    mfvsrwz r3, f8
-; CHECK-P9-NEXT:    mtvsrd f8, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f7
+; CHECK-P9-NEXT:    mffprwz r3, f8
+; CHECK-P9-NEXT:    mtfprd f8, r3
+; CHECK-P9-NEXT:    mffprwz r3, f7
 ; CHECK-P9-NEXT:    xxswapd v2, vs8
-; CHECK-P9-NEXT:    mtvsrd f7, r3
+; CHECK-P9-NEXT:    mtfprd f7, r3
 ; CHECK-P9-NEXT:    xxswapd v3, vs7
 ; CHECK-P9-NEXT:    xscvdpsxws f7, f6
 ; CHECK-P9-NEXT:    xxswapd vs6, vs6
 ; CHECK-P9-NEXT:    xscvdpsxws f6, f6
-; CHECK-P9-NEXT:    mfvsrwz r3, f7
-; CHECK-P9-NEXT:    mtvsrd f7, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f6
-; CHECK-P9-NEXT:    mtvsrd f6, r3
+; CHECK-P9-NEXT:    mffprwz r3, f7
+; CHECK-P9-NEXT:    mtfprd f7, r3
+; CHECK-P9-NEXT:    mffprwz r3, f6
+; CHECK-P9-NEXT:    mtfprd f6, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs6
 ; CHECK-P9-NEXT:    xscvdpsxws f6, f5
 ; CHECK-P9-NEXT:    xxswapd vs5, vs5
 ; CHECK-P9-NEXT:    xscvdpsxws f5, f5
-; CHECK-P9-NEXT:    mfvsrwz r3, f6
-; CHECK-P9-NEXT:    mtvsrd f6, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f5
+; CHECK-P9-NEXT:    mffprwz r3, f6
+; CHECK-P9-NEXT:    mtfprd f6, r3
+; CHECK-P9-NEXT:    mffprwz r3, f5
 ; CHECK-P9-NEXT:    vmrglb v2, v2, v3
 ; CHECK-P9-NEXT:    xxswapd v3, vs7
 ; CHECK-P9-NEXT:    vmrglb v3, v3, v4
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P9-NEXT:    xxswapd v3, vs6
-; CHECK-P9-NEXT:    mtvsrd f5, r3
+; CHECK-P9-NEXT:    mtfprd f5, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs5
 ; CHECK-P9-NEXT:    xscvdpsxws f5, f4
 ; CHECK-P9-NEXT:    xxswapd vs4, vs4
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f4
-; CHECK-P9-NEXT:    mfvsrwz r3, f5
-; CHECK-P9-NEXT:    mtvsrd f5, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r3
+; CHECK-P9-NEXT:    mffprwz r3, f5
+; CHECK-P9-NEXT:    mtfprd f5, r3
+; CHECK-P9-NEXT:    mffprwz r3, f4
+; CHECK-P9-NEXT:    mtfprd f4, r3
 ; CHECK-P9-NEXT:    xxswapd v5, vs4
 ; CHECK-P9-NEXT:    xscvdpsxws f4, f3
 ; CHECK-P9-NEXT:    xxswapd vs3, vs3
@@ -1127,18 +1127,18 @@
 ; CHECK-P9-NEXT:    xxswapd v4, vs5
 ; CHECK-P9-NEXT:    vmrglb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
-; CHECK-P9-NEXT:    mfvsrwz r3, f4
-; CHECK-P9-NEXT:    mtvsrd f4, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
+; CHECK-P9-NEXT:    mffprwz r3, f4
+; CHECK-P9-NEXT:    mtfprd f4, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
+; CHECK-P9-NEXT:    mtfprd f3, r3
 ; CHECK-P9-NEXT:    xxswapd v4, vs3
 ; CHECK-P9-NEXT:    xscvdpsxws f3, f2
 ; CHECK-P9-NEXT:    xxswapd vs2, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f2
-; CHECK-P9-NEXT:    mfvsrwz r3, f3
-; CHECK-P9-NEXT:    mtvsrd f3, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f3
+; CHECK-P9-NEXT:    mtfprd f3, r3
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
 ; CHECK-P9-NEXT:    xxswapd v5, vs2
 ; CHECK-P9-NEXT:    xscvdpsxws f2, f1
 ; CHECK-P9-NEXT:    xxswapd vs1, vs1
@@ -1149,19 +1149,19 @@
 ; CHECK-P9-NEXT:    xxswapd v4, vs3
 ; CHECK-P9-NEXT:    vmrglb v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
-; CHECK-P9-NEXT:    mfvsrwz r3, f2
-; CHECK-P9-NEXT:    mtvsrd f2, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
+; CHECK-P9-NEXT:    mffprwz r3, f2
+; CHECK-P9-NEXT:    mtfprd f2, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
 ; CHECK-P9-NEXT:    xxswapd v4, vs2
-; CHECK-P9-NEXT:    mtvsrd f1, r3
+; CHECK-P9-NEXT:    mtfprd f1, r3
 ; CHECK-P9-NEXT:    xxswapd v5, vs1
 ; CHECK-P9-NEXT:    xscvdpsxws f1, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, vs0
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f1
-; CHECK-P9-NEXT:    mtvsrd f1, r3
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mffprwz r3, f1
+; CHECK-P9-NEXT:    mtfprd f1, r3
+; CHECK-P9-NEXT:    mffprwz r3, f0
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    vmrglb v4, v4, v5
 ; CHECK-P9-NEXT:    xxswapd v5, vs1
 ; CHECK-P9-NEXT:    xxswapd v0, vs0
@@ -1184,84 +1184,84 @@
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs4, 64(r3)
 ; CHECK-BE-NEXT:    lxv vs5, 80(r3)
-; CHECK-BE-NEXT:    mfvsrwz r3, f8
+; CHECK-BE-NEXT:    mffprwz r3, f8
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f7
+; CHECK-BE-NEXT:    mffprwz r3, f7
 ; CHECK-BE-NEXT:    xscvdpsxws f7, f6
 ; CHECK-BE-NEXT:    xxswapd vs6, vs6
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f6
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    vmrghb v2, v2, v3
-; CHECK-BE-NEXT:    mfvsrwz r3, f7
+; CHECK-BE-NEXT:    mffprwz r3, f7
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f6
+; CHECK-BE-NEXT:    mffprwz r3, f6
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f5
 ; CHECK-BE-NEXT:    xxswapd vs5, vs5
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f5
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghb v3, v3, v4
-; CHECK-BE-NEXT:    mfvsrwz r3, f6
+; CHECK-BE-NEXT:    mffprwz r3, f6
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f5
+; CHECK-BE-NEXT:    mffprwz r3, f5
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f4
 ; CHECK-BE-NEXT:    xxswapd vs4, vs4
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghb v3, v3, v4
-; CHECK-BE-NEXT:    mfvsrwz r3, f5
+; CHECK-BE-NEXT:    mffprwz r3, f5
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f4
+; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    vmrghb v4, v4, v5
-; CHECK-BE-NEXT:    mfvsrwz r3, f4
+; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    vmrghh v3, v4, v3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    vmrghb v3, v3, v4
-; CHECK-BE-NEXT:    mfvsrwz r3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    vmrghb v4, v4, v5
-; CHECK-BE-NEXT:    mfvsrwz r3, f2
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    vmrghh v3, v4, v3
 ; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
 ; CHECK-BE-NEXT:    vmrghb v4, v4, v5
-; CHECK-BE-NEXT:    mfvsrwz r3, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    sldi r3, r3, 56
 ; CHECK-BE-NEXT:    mtvsrd v0, r3
 ; CHECK-BE-NEXT:    vmrghb v5, v5, v0
diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_4byte_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_4byte_elts.ll
--- a/llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_4byte_elts.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_4byte_elts.ll
@@ -12,16 +12,16 @@
 define i64 @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xvcvspuxws vs0, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    xvcvspuxws vs0, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, vs0
@@ -29,9 +29,9 @@
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrd f0, r3
+; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    xvcvspuxws vs0, vs0
-; CHECK-BE-NEXT:    mfvsrd r3, f0
+; CHECK-BE-NEXT:    mffprd r3, f0
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <2 x float>
@@ -159,16 +159,16 @@
 define i64 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xvcvspsxws vs0, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    xvcvspsxws vs0, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, vs0
@@ -176,9 +176,9 @@
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrd f0, r3
+; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    xvcvspsxws vs0, vs0
-; CHECK-BE-NEXT:    mfvsrd r3, f0
+; CHECK-BE-NEXT:    mffprd r3, f0
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <2 x float>
diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
--- a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
@@ -12,12 +12,12 @@
 define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    clrldi r4, r3, 48
 ; CHECK-P8-NEXT:    rldicl r3, r3, 48, 48
-; CHECK-P8-NEXT:    rlwinm r4, r4, 0, 16, 31
-; CHECK-P8-NEXT:    rlwinm r3, r3, 0, 16, 31
+; CHECK-P8-NEXT:    clrlwi r4, r4, 16
+; CHECK-P8-NEXT:    clrlwi r3, r3, 16
 ; CHECK-P8-NEXT:    mtfprwz f0, r4
 ; CHECK-P8-NEXT:    mtfprwz f1, r3
 ; CHECK-P8-NEXT:    xscvuxdsp f0, f0
@@ -28,7 +28,7 @@
 ; CHECK-P8-NEXT:    xxsldwi v3, vs1, vs1, 1
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
@@ -36,13 +36,13 @@
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vextuhrx r3, r3, v2
-; CHECK-P9-NEXT:    rlwinm r3, r3, 0, 16, 31
+; CHECK-P9-NEXT:    clrlwi r3, r3, 16
 ; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    li r3, 2
 ; CHECK-P9-NEXT:    xscvuxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    vextuhrx r3, r3, v2
-; CHECK-P9-NEXT:    rlwinm r3, r3, 0, 16, 31
+; CHECK-P9-NEXT:    clrlwi r3, r3, 16
 ; CHECK-P9-NEXT:    xxsldwi v3, vs0, vs0, 1
 ; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    xscvuxdsp f0, f0
@@ -57,12 +57,12 @@
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
 ; CHECK-BE-NEXT:    li r3, 2
 ; CHECK-BE-NEXT:    vextuhlx r3, r3, v2
-; CHECK-BE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; CHECK-BE-NEXT:    clrlwi r3, r3, 16
 ; CHECK-BE-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-NEXT:    li r3, 0
 ; CHECK-BE-NEXT:    xscvuxdsp f0, f0
 ; CHECK-BE-NEXT:    vextuhlx r3, r3, v2
-; CHECK-BE-NEXT:    rlwinm r3, r3, 0, 16, 31
+; CHECK-BE-NEXT:    clrlwi r3, r3, 16
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
 ; CHECK-BE-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-NEXT:    xscvuxdsp f0, f0
@@ -81,7 +81,7 @@
 ; CHECK-P8-LABEL: test4elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    addi r3, r4, .LCPI1_0@toc@l
 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
@@ -92,7 +92,7 @@
 ;
 ; CHECK-P9-LABEL: test4elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI1_0@toc@l
 ; CHECK-P9-NEXT:    lxvx v3, 0, r3
@@ -264,8 +264,8 @@
 define i64 @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    clrldi r4, r3, 48
 ; CHECK-P8-NEXT:    rldicl r3, r3, 48, 48
 ; CHECK-P8-NEXT:    extsh r4, r4
@@ -280,7 +280,7 @@
 ; CHECK-P8-NEXT:    xxsldwi v3, vs1, vs1, 1
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
@@ -332,7 +332,7 @@
 define <4 x float> @test4elt_signed(i64 %a.coerce) local_unnamed_addr #1 {
 ; CHECK-P8-LABEL: test4elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    vspltisw v3, 8
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    vadduwm v3, v3, v3
@@ -344,7 +344,7 @@
 ;
 ; CHECK-P9-LABEL: test4elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    vmrglh v2, v2, v2
 ; CHECK-P9-NEXT:    vextsh2w v2, v2
diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
--- a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
@@ -13,7 +13,7 @@
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    addi r3, r4, .LCPI0_0@toc@l
 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
@@ -53,7 +53,7 @@
 ; CHECK-P8-LABEL: test4elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r5, r2, .LCPI1_0@toc@ha
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI1_1@toc@ha
 ; CHECK-P8-NEXT:    addi r5, r5, .LCPI1_0@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI1_1@toc@l
@@ -74,7 +74,7 @@
 ;
 ; CHECK-P9-LABEL: test4elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
 ; CHECK-P9-NEXT:    addi r4, r4, .LCPI1_0@toc@l
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
@@ -370,7 +370,7 @@
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI4_0@toc@ha
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    addi r3, r4, .LCPI4_0@toc@l
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
@@ -415,7 +415,7 @@
 ; CHECK-P8-LABEL: test4elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r5, r2, .LCPI5_0@toc@ha
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI5_2@toc@ha
 ; CHECK-P8-NEXT:    addi r5, r5, .LCPI5_0@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI5_2@toc@l
@@ -443,7 +443,7 @@
 ;
 ; CHECK-P9-LABEL: test4elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
 ; CHECK-P9-NEXT:    addi r4, r4, .LCPI5_0@toc@l
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll
--- a/llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll
@@ -12,7 +12,7 @@
 define <2 x double> @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xxmrglw v2, v2, v2
 ; CHECK-P8-NEXT:    xvcvuxwdp v2, v2
@@ -20,7 +20,7 @@
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    xxmrglw v2, v2, v2
 ; CHECK-P9-NEXT:    xvcvuxwdp v2, v2
@@ -28,7 +28,7 @@
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrd f0, r3
+; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    xxmrghw v2, vs0, vs0
 ; CHECK-BE-NEXT:    xvcvuxwdp v2, v2
 ; CHECK-BE-NEXT:    blr
@@ -266,7 +266,7 @@
 define <2 x double> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xxmrglw v2, v2, v2
 ; CHECK-P8-NEXT:    xvcvsxwdp v2, v2
@@ -274,7 +274,7 @@
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    xxmrglw v2, v2, v2
 ; CHECK-P9-NEXT:    xvcvsxwdp v2, v2
@@ -282,7 +282,7 @@
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrd f0, r3
+; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    xxmrghw v2, vs0, vs0
 ; CHECK-BE-NEXT:    xvcvsxwdp v2, v2
 ; CHECK-BE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll
--- a/llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll
@@ -22,7 +22,7 @@
 ; CHECK-P8-NEXT:    xxsldwi v2, vs0, vs0, 1
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
@@ -315,7 +315,7 @@
 ; CHECK-P8-NEXT:    xxsldwi v2, vs0, vs0, 1
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
--- a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
@@ -12,12 +12,12 @@
 define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    clrldi r4, r3, 56
 ; CHECK-P8-NEXT:    rldicl r3, r3, 56, 56
-; CHECK-P8-NEXT:    rlwinm r4, r4, 0, 24, 31
-; CHECK-P8-NEXT:    rlwinm r3, r3, 0, 24, 31
+; CHECK-P8-NEXT:    clrlwi r4, r4, 24
+; CHECK-P8-NEXT:    clrlwi r3, r3, 24
 ; CHECK-P8-NEXT:    mtfprwz f0, r4
 ; CHECK-P8-NEXT:    mtfprwz f1, r3
 ; CHECK-P8-NEXT:    xscvuxdsp f0, f0
@@ -28,7 +28,7 @@
 ; CHECK-P8-NEXT:    xxsldwi v3, vs1, vs1, 1
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
@@ -36,13 +36,13 @@
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vextubrx r3, r3, v2
-; CHECK-P9-NEXT:    rlwinm r3, r3, 0, 24, 31
+; CHECK-P9-NEXT:    clrlwi r3, r3, 24
 ; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    li r3, 1
 ; CHECK-P9-NEXT:    xscvuxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    vextubrx r3, r3, v2
-; CHECK-P9-NEXT:    rlwinm r3, r3, 0, 24, 31
+; CHECK-P9-NEXT:    clrlwi r3, r3, 24
 ; CHECK-P9-NEXT:    xxsldwi v3, vs0, vs0, 1
 ; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    xscvuxdsp f0, f0
@@ -57,12 +57,12 @@
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
 ; CHECK-BE-NEXT:    li r3, 1
 ; CHECK-BE-NEXT:    vextublx r3, r3, v2
-; CHECK-BE-NEXT:    rlwinm r3, r3, 0, 24, 31
+; CHECK-BE-NEXT:    clrlwi r3, r3, 24
 ; CHECK-BE-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-NEXT:    li r3, 0
 ; CHECK-BE-NEXT:    xscvuxdsp f0, f0
 ; CHECK-BE-NEXT:    vextublx r3, r3, v2
-; CHECK-BE-NEXT:    rlwinm r3, r3, 0, 24, 31
+; CHECK-BE-NEXT:    clrlwi r3, r3, 24
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
 ; CHECK-BE-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-NEXT:    xscvuxdsp f0, f0
@@ -81,7 +81,7 @@
 ; CHECK-P8-LABEL: test4elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    addi r3, r4, .LCPI1_0@toc@l
 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
@@ -121,7 +121,7 @@
 ; CHECK-P8-LABEL: test8elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r5, r2, .LCPI2_0@toc@ha
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI2_1@toc@ha
 ; CHECK-P8-NEXT:    addi r5, r5, .LCPI2_0@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI2_1@toc@l
@@ -140,7 +140,7 @@
 ;
 ; CHECK-P9-LABEL: test8elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
 ; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_0@toc@l
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
@@ -280,8 +280,8 @@
 define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mtfprd f0, r3
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    clrldi r4, r3, 56
 ; CHECK-P8-NEXT:    rldicl r3, r3, 56, 56
 ; CHECK-P8-NEXT:    extsb r4, r4
@@ -296,7 +296,7 @@
 ; CHECK-P8-NEXT:    xxsldwi v3, vs1, vs1, 1
 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
@@ -349,7 +349,7 @@
 ; CHECK-P8-LABEL: test4elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    addi r3, r4, .LCPI5_0@toc@l
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
@@ -392,7 +392,7 @@
 ; CHECK-P8-LABEL: test8elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r5, r2, .LCPI6_0@toc@ha
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI6_1@toc@ha
 ; CHECK-P8-NEXT:    vspltisw v5, 12
 ; CHECK-P8-NEXT:    addi r5, r5, .LCPI6_0@toc@l
@@ -416,7 +416,7 @@
 ;
 ; CHECK-P9-LABEL: test8elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
 ; CHECK-P9-NEXT:    addi r4, r4, .LCPI6_0@toc@l
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
--- a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
@@ -13,7 +13,7 @@
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    addi r3, r4, .LCPI0_0@toc@l
 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
@@ -53,7 +53,7 @@
 ; CHECK-P8-LABEL: test4elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r5, r2, .LCPI1_0@toc@ha
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI1_1@toc@ha
 ; CHECK-P8-NEXT:    addi r5, r5, .LCPI1_0@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI1_1@toc@l
@@ -118,7 +118,7 @@
 ; CHECK-P8-LABEL: test8elt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r5, r2, .LCPI2_0@toc@ha
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI2_2@toc@ha
 ; CHECK-P8-NEXT:    addi r5, r5, .LCPI2_0@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI2_2@toc@l
@@ -155,7 +155,7 @@
 ;
 ; CHECK-P9-LABEL: test8elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
 ; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_0@toc@l
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
@@ -404,7 +404,7 @@
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI4_0@toc@ha
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    addi r3, r4, .LCPI4_0@toc@l
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
@@ -449,7 +449,7 @@
 ; CHECK-P8-LABEL: test4elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r5, r2, .LCPI5_0@toc@ha
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI5_2@toc@ha
 ; CHECK-P8-NEXT:    addi r5, r5, .LCPI5_0@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI5_2@toc@l
@@ -523,7 +523,7 @@
 define void @test8elt_signed(<8 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
 ; CHECK-P8-LABEL: test8elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r4
+; CHECK-P8-NEXT:    mtfprd f0, r4
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI6_2@toc@ha
 ; CHECK-P8-NEXT:    addis r5, r2, .LCPI6_0@toc@ha
 ; CHECK-P8-NEXT:    addis r6, r2, .LCPI6_3@toc@ha
@@ -572,7 +572,7 @@
 ;
 ; CHECK-P9-LABEL: test8elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r4
+; CHECK-P9-NEXT:    mtfprd f0, r4
 ; CHECK-P9-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
 ; CHECK-P9-NEXT:    addi r4, r4, .LCPI6_0@toc@l
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_4byte_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_4byte_elts.ll
--- a/llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_4byte_elts.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_4byte_elts.ll
@@ -12,16 +12,16 @@
 define i64 @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xvcvuxwsp vs0, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    xvcvuxwsp vs0, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, vs0
@@ -29,9 +29,9 @@
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrd f0, r3
+; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    xvcvuxwsp vs0, vs0
-; CHECK-BE-NEXT:    mfvsrd r3, f0
+; CHECK-BE-NEXT:    mffprd r3, f0
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <2 x i32>
@@ -159,16 +159,16 @@
 define i64 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    mtvsrd f0, r3
+; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xvcvsxwsp vs0, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
-; CHECK-P8-NEXT:    mfvsrd r3, f0
+; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd f0, r3
+; CHECK-P9-NEXT:    mtfprd f0, r3
 ; CHECK-P9-NEXT:    xxswapd v2, vs0
 ; CHECK-P9-NEXT:    xvcvsxwsp vs0, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, vs0
@@ -176,9 +176,9 @@
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrd f0, r3
+; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    xvcvsxwsp vs0, vs0
-; CHECK-BE-NEXT:    mfvsrd r3, f0
+; CHECK-BE-NEXT:    mffprd r3, f0
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <2 x i32>
diff --git a/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll b/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
--- a/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
@@ -6375,7 +6375,7 @@
 ; PC64LE-NEXT:    addis 3, 2, .LCPI103_0@toc@ha
 ; PC64LE-NEXT:    addi 3, 3, .LCPI103_0@toc@l
 ; PC64LE-NEXT:    lfiwzx 0, 0, 3
-; PC64LE-NEXT:    xxpermdi 34, 0, 0, 2
+; PC64LE-NEXT:    xxswapd 34, 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_ceil_v1f32:
@@ -6383,7 +6383,7 @@
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI103_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI103_0@toc@l
 ; PC64LE9-NEXT:    lfiwzx 0, 0, 3
-; PC64LE9-NEXT:    xxpermdi 34, 0, 0, 2
+; PC64LE9-NEXT:    xxswapd 34, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %ceil = call <1 x float> @llvm.experimental.constrained.ceil.v1f32(
@@ -6464,7 +6464,7 @@
 ; PC64LE-NEXT:    addis 3, 2, .LCPI107_0@toc@ha
 ; PC64LE-NEXT:    addi 3, 3, .LCPI107_0@toc@l
 ; PC64LE-NEXT:    lfiwzx 0, 0, 3
-; PC64LE-NEXT:    xxpermdi 34, 0, 0, 2
+; PC64LE-NEXT:    xxswapd 34, 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_floor_v1f32:
@@ -6472,7 +6472,7 @@
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI107_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI107_0@toc@l
 ; PC64LE9-NEXT:    lfiwzx 0, 0, 3
-; PC64LE9-NEXT:    xxpermdi 34, 0, 0, 2
+; PC64LE9-NEXT:    xxswapd 34, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %floor = call <1 x float> @llvm.experimental.constrained.floor.v1f32(
@@ -6554,7 +6554,7 @@
 ; PC64LE-NEXT:    addis 3, 2, .LCPI111_0@toc@ha
 ; PC64LE-NEXT:    addi 3, 3, .LCPI111_0@toc@l
 ; PC64LE-NEXT:    lfiwzx 0, 0, 3
-; PC64LE-NEXT:    xxpermdi 34, 0, 0, 2
+; PC64LE-NEXT:    xxswapd 34, 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_round_v1f32:
@@ -6562,7 +6562,7 @@
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI111_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI111_0@toc@l
 ; PC64LE9-NEXT:    lfiwzx 0, 0, 3
-; PC64LE9-NEXT:    xxpermdi 34, 0, 0, 2
+; PC64LE9-NEXT:    xxswapd 34, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %round = call <1 x float> @llvm.experimental.constrained.round.v1f32(
@@ -6646,7 +6646,7 @@
 ; PC64LE-NEXT:    addis 3, 2, .LCPI115_0@toc@ha
 ; PC64LE-NEXT:    addi 3, 3, .LCPI115_0@toc@l
 ; PC64LE-NEXT:    lfiwzx 0, 0, 3
-; PC64LE-NEXT:    xxpermdi 34, 0, 0, 2
+; PC64LE-NEXT:    xxswapd 34, 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_trunc_v1f32:
@@ -6654,7 +6654,7 @@
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI115_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI115_0@toc@l
 ; PC64LE9-NEXT:    lfiwzx 0, 0, 3
-; PC64LE9-NEXT:    xxpermdi 34, 0, 0, 2
+; PC64LE9-NEXT:    xxswapd 34, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %trunc = call <1 x float> @llvm.experimental.constrained.trunc.v1f32(
diff --git a/llvm/test/CodeGen/PowerPC/vsx.ll b/llvm/test/CodeGen/PowerPC/vsx.ll
--- a/llvm/test/CodeGen/PowerPC/vsx.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx.ll
@@ -2437,7 +2437,7 @@
 ;
 ; CHECK-LE-LABEL: test80:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    mtvsrd f0, r3
+; CHECK-LE-NEXT:    mtfprd f0, r3
 ; CHECK-LE-NEXT:    addis r4, r2, .LCPI65_0@toc@ha
 ; CHECK-LE-NEXT:    addi r3, r4, .LCPI65_0@toc@l
 ; CHECK-LE-NEXT:    xxswapd vs0, vs0
diff --git a/llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll b/llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
--- a/llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
@@ -34,7 +34,7 @@
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    lfd f1, 0(r4)
 ; CHECK-P9-NEXT:    lxv vs0, 0(r3)
-; CHECK-P9-NEXT:    xxpermdi vs1, f1, f1, 2
+; CHECK-P9-NEXT:    xxswapd vs1, f1
 ; CHECK-P9-NEXT:    xxpermdi v2, vs0, vs1, 1
 ; CHECK-P9-NEXT:    blr
   %v = load <2 x double>, <2 x double>* %p1
@@ -68,7 +68,7 @@
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    lfd f1, 0(r4)
 ; CHECK-P9-NEXT:    lxv vs0, 0(r3)
-; CHECK-P9-NEXT:    xxpermdi vs1, f1, f1, 2
+; CHECK-P9-NEXT:    xxswapd vs1, f1
 ; CHECK-P9-NEXT:    xxmrgld v2, vs1, vs0
 ; CHECK-P9-NEXT:    blr
   %v = load <2 x double>, <2 x double>* %p1
diff --git a/llvm/test/CodeGen/PowerPC/xray-conditional-return.ll b/llvm/test/CodeGen/PowerPC/xray-conditional-return.ll
--- a/llvm/test/CodeGen/PowerPC/xray-conditional-return.ll
+++ b/llvm/test/CodeGen/PowerPC/xray-conditional-return.ll
@@ -2,8 +2,8 @@
 
 define void @Foo(i32 signext %a, i32 signext %b) #0 {
 ; CHECK-LABEL: @Foo
-; CHECK:   cmpw [[CR:[0-9]+]]
-; CHECK-NEXT:   ble [[CR]], [[LABEL:\.[a-zA-Z0-9]+]]
+; CHECK:   cmpw
+; CHECK-NEXT:   ble 0, [[LABEL:\.[a-zA-Z0-9]+]]
 ; CHECK-NEXT:   .p2align  3
 ; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}:
 ; CHECK-NEXT:   blr
@@ -39,8 +39,8 @@
 
 define void @Foo2(i32 signext %a, i32 signext %b) #0 {
 ; CHECK-LABEL: @Foo2
-; CHECK:   cmpw [[CR:[0-9]+]]
-; CHECK-NEXT:   bge [[CR]], [[LABEL:\.[a-zA-Z0-9]+]]
+; CHECK:   cmpw
+; CHECK-NEXT:   bge 0, [[LABEL:\.[a-zA-Z0-9]+]]
 ; CHECK-NEXT:   .p2align  3
 ; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}:
 ; CHECK-NEXT:   blr