diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -711,6 +711,7 @@
 def : InstAlias<"wfi",  (HINT 0b011)>;
 def : InstAlias<"sev",  (HINT 0b100)>;
 def : InstAlias<"sevl", (HINT 0b101)>;
+def : InstAlias<"dgh",  (HINT 0b110)>;
 def : InstAlias<"esb",  (HINT 0b10000)>, Requires<[HasRAS]>;
 def : InstAlias<"csdb", (HINT 20)>;
 def : InstAlias<"bti",  (HINT 32)>, Requires<[HasBTI]>;
diff --git a/llvm/test/MC/AArch64/armv8.6a-dgh.s b/llvm/test/MC/AArch64/armv8.6a-dgh.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv8.6a-dgh.s
@@ -0,0 +1,4 @@
+// RUN:     llvm-mc -triple aarch64 -show-encoding   < %s | FileCheck %s
+
+dgh
+// CHECK: dgh                             // encoding: [0xdf,0x20,0x03,0xd5]
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.6a-dgh.txt b/llvm/test/MC/Disassembler/AArch64/armv8.6a-dgh.txt
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.6a-dgh.txt
@@ -0,0 +1,4 @@
+# RUN: llvm-mc -triple=aarch64  -disassemble < %s      | FileCheck %s
+
+[0xdf,0x20,0x03,0xd5]
+# CHECK: dgh