diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -3829,9 +3829,8 @@ def QSUB8 : AAIIntrinsic<0b01100010, 0b11111111, "qsub8", int_arm_qsub8>; def QDADD : AAIRevOpr<0b00010100, 0b00000101, "qdadd", - [(set GPRnopc:$Rd, (int_arm_qadd (int_arm_qadd GPRnopc:$Rm, - GPRnopc:$Rm), - GPRnopc:$Rn))]>; + [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, + (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>; def QDSUB : AAIRevOpr<0b00010110, 0b00000101, "qdsub", [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>; @@ -3846,7 +3845,7 @@ (QADD GPR:$a, GPR:$b)>; def : ARMV5TEPat<(ssubsat GPR:$a, GPR:$b), (QSUB GPR:$a, GPR:$b)>; -def : ARMV5TEPat<(saddsat(saddsat rGPR:$Rm, rGPR:$Rm), rGPR:$Rn), +def : ARMV5TEPat<(saddsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)), (QDADD rGPR:$Rm, rGPR:$Rn)>; def : ARMV5TEPat<(ssubsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)), (QDSUB rGPR:$Rm, rGPR:$Rn)>; diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -2485,7 +2485,7 @@ (t2QADD rGPR:$Rm, rGPR:$Rn)>; def : Thumb2DSPPat<(int_arm_qsub rGPR:$Rm, rGPR:$Rn), (t2QSUB rGPR:$Rm, rGPR:$Rn)>; -def : Thumb2DSPPat<(int_arm_qadd(int_arm_qadd rGPR:$Rm, rGPR:$Rm), rGPR:$Rn), +def : Thumb2DSPPat<(int_arm_qadd rGPR:$Rm, (int_arm_qadd rGPR:$Rn, rGPR:$Rn)), (t2QDADD rGPR:$Rm, rGPR:$Rn)>; def : Thumb2DSPPat<(int_arm_qsub rGPR:$Rm, (int_arm_qadd rGPR:$Rn, rGPR:$Rn)), (t2QDSUB rGPR:$Rm, rGPR:$Rn)>; @@ -2494,7 +2494,7 @@ (t2QADD rGPR:$Rm, rGPR:$Rn)>; def : Thumb2DSPPat<(ssubsat rGPR:$Rm, rGPR:$Rn), (t2QSUB rGPR:$Rm, rGPR:$Rn)>; -def : Thumb2DSPPat<(saddsat(saddsat rGPR:$Rm, rGPR:$Rm), rGPR:$Rn), +def : Thumb2DSPPat<(saddsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)), (t2QDADD rGPR:$Rm, rGPR:$Rn)>; def : Thumb2DSPPat<(ssubsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)), (t2QDSUB rGPR:$Rm, rGPR:$Rn)>; diff --git a/llvm/test/CodeGen/ARM/acle-intrinsics-v5.ll b/llvm/test/CodeGen/ARM/acle-intrinsics-v5.ll --- a/llvm/test/CodeGen/ARM/acle-intrinsics-v5.ll +++ b/llvm/test/CodeGen/ARM/acle-intrinsics-v5.ll @@ -80,7 +80,7 @@ define i32 @qdadd(i32 %a, i32 %b) nounwind { ; CHECK-LABEL: qdadd -; CHECK: qdadd r0, r0, r1 +; CHECK: qdadd r0, r1, r0 %dbl = call i32 @llvm.arm.qadd(i32 %a, i32 %a) %add = call i32 @llvm.arm.qadd(i32 %dbl, i32 %b) ret i32 %add diff --git a/llvm/test/CodeGen/ARM/qdadd.ll b/llvm/test/CodeGen/ARM/qdadd.ll --- a/llvm/test/CodeGen/ARM/qdadd.ll +++ b/llvm/test/CodeGen/ARM/qdadd.ll @@ -36,12 +36,12 @@ ; ; CHECK-T2DSP-LABEL: qdadd: ; CHECK-T2DSP: @ %bb.0: -; CHECK-T2DSP-NEXT: qdadd r0, r0, r1 +; CHECK-T2DSP-NEXT: qdadd r0, r1, r0 ; CHECK-T2DSP-NEXT: bx lr ; ; CHECK-ARM-LABEL: qdadd: ; CHECK-ARM: @ %bb.0: -; CHECK-ARM-NEXT: qdadd r0, r0, r1 +; CHECK-ARM-NEXT: qdadd r0, r1, r0 ; CHECK-ARM-NEXT: bx lr %z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x) %tmp = call i32 @llvm.sadd.sat.i32(i32 %z, i32 %y) @@ -80,12 +80,12 @@ ; ; CHECK-T2DSP-LABEL: qdadd_c: ; CHECK-T2DSP: @ %bb.0: -; CHECK-T2DSP-NEXT: qdadd r0, r0, r1 +; CHECK-T2DSP-NEXT: qdadd r0, r1, r0 ; CHECK-T2DSP-NEXT: bx lr ; ; CHECK-ARM-LABEL: qdadd_c: ; CHECK-ARM: @ %bb.0: -; CHECK-ARM-NEXT: qdadd r0, r0, r1 +; CHECK-ARM-NEXT: qdadd r0, r1, r0 ; CHECK-ARM-NEXT: bx lr %z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x) %tmp = call i32 @llvm.sadd.sat.i32(i32 %y, i32 %z)