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Minor fixups to LLDB AArch64 register infos macros for SVE register infos
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Authored by omjavaid on Mar 30 2020, 2:38 AM.

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Summary

This patch adds some cosmetic changes to LLDB AArch64 register infos macros in order to use them in SVE register infos struct in follow up patches.
This patch initially added invalidate lists to register infos struct but that is no longer needed and problem disappeared after updating qemu testing environment.

old headline comments for reference:
AArch64 reigster X and V registers are primary GPR and vector registers respectively. If these registers are modified their corresponding children w regs or s/d regs should be invalidated. Specially when a register write fails it is important that failure gets reflected to all the registers which draw their value from a particular value register.

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Event Timeline

omjavaid created this revision.Mar 30 2020, 2:38 AM
labath added a comment.Apr 1 2020, 5:06 AM

This sounds like it could use a test case.

lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
593–594

What's up with the indirection?

omjavaid marked an inline comment as done.Apr 2 2020, 3:30 AM

This sounds like it could use a test case.

Adding a testcase would be tricky as these register overlap in memory and we store them with overlapping offsets with their children we should not need to invalidate the children when we write the parent but for some strange unexplainable reason QEMU was behaving strangely and not updating the first half in certain random cases. I just thought invalidation of children will force a read after write for that case.

lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
593–594

We want to pass nullptr or register name as is then do stringize on regname only. According to C macro expansion rules if we want our macros expanded first and then do the # then we ll need double indirection.

labath added a comment.Apr 6 2020, 7:01 AM

Adding a testcase would be tricky as these register overlap in memory and we store them with overlapping offsets with their children we should not need to invalidate the children when we write the parent but for some strange unexplainable reason QEMU was behaving strangely and not updating the first half in certain random cases. I just thought invalidation of children will force a read after write for that case.

Thanks for the explanation, but I'm afraid I still don't get what is going on here. Can you walk me through the individual steps here? Something like:

  1. user does "register write x0 xxxxxx"
  2. lldb translates that to the appropriate p packet
  3. ???
  4. user does "register read w0"
  5. bad value comes out because...
lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
593–594

I've figured it's something like that, though it's still not clear to me why that is needed in this particular case.

However, now I have a different question. As the only thing you're using the alt_name argument for is to turn it into a string, why not just pass a string in the first place:

DEFINE_GPR64(x0, nullptr, ...)
...
DEFINE_GPR64(fp, "x29", ...)
...
597

This comment is out of date now.

Adding a testcase would be tricky as these register overlap in memory and we store them with overlapping offsets with their children we should not need to invalidate the children when we write the parent but for some strange unexplainable reason QEMU was behaving strangely and not updating the first half in certain random cases. I just thought invalidation of children will force a read after write for that case.

Thanks for the explanation, but I'm afraid I still don't get what is going on here. Can you walk me through the individual steps here? Something like:

  1. user does "register write x0 xxxxxx"
  2. lldb translates that to the appropriate p packet
  3. ???
  4. user does "register read w0"
  5. bad value comes out because...

Let me debug it separately from SVE and I will get back to you with an update.

omjavaid retitled this revision from Add invalidate list to primary regs in arm64 register infos to Minor fixups to LLDB AArch64 register infos macros for SVE register infos.May 10 2020, 11:32 PM
omjavaid edited the summary of this revision. (Show Details)
omjavaid updated this revision to Diff 263105.May 10 2020, 11:34 PM

Adding a testcase would be tricky as these register overlap in memory and we store them with overlapping offsets with their children we should not need to invalidate the children when we write the parent but for some strange unexplainable reason QEMU was behaving strangely and not updating the first half in certain random cases. I just thought invalidation of children will force a read after write for that case.

Thanks for the explanation, but I'm afraid I still don't get what is going on here. Can you walk me through the individual steps here? Something like:

  1. user does "register write x0 xxxxxx"
  2. lldb translates that to the appropriate p packet
  3. ???
  4. user does "register read w0"
  5. bad value comes out because...

Let me debug it separately from SVE and I will get back to you with an update.

I have tried to figure this out and eventually problem disappeared after updating test environment. I could not really figure out the exact issue.

omjavaid updated this revision to Diff 271533.Jun 17 2020, 5:09 PM
labath accepted this revision.Jun 24 2020, 7:25 AM
This revision is now accepted and ready to land.Jun 24 2020, 7:25 AM
This revision was automatically updated to reflect the committed changes.
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