Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -7897,10 +7897,12 @@
 
   // Emit a store to the stack slot.
   SDValue Chain;
+  unsigned Alignment = 0;
   if (i32Stack) {
     MachineFunction &MF = DAG.getMachineFunction();
     MachineMemOperand *MMO =
         MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, Align(4));
+    Alignment = 4;
     SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
     Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
               DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
@@ -7918,6 +7920,7 @@
   RLI.Chain = Chain;
   RLI.Ptr = FIPtr;
   RLI.MPI = MPI;
+  RLI.Alignment = Alignment;
 }
 
 /// Custom lowers floating point to integer conversions to use
Index: llvm/test/CodeGen/PowerPC/kernel-fp-round.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/kernel-fp-round.ll
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -ppc-asm-full-reg-names < %s | FileCheck %s
+
+define float @test(float %arg) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fctiwz f0, f1
+; CHECK-NEXT:    addi r3, r1, -4
+; CHECK-NEXT:    stfiwx f0, 0, r3
+; CHECK-NEXT:    lfiwax f0, 0, r3
+; CHECK-NEXT:    fcfids f1, f0
+; CHECK-NEXT:    blr
+entry:
+  %conv = fptosi float %arg to i32
+  %res = sitofp i32 %conv to float
+  ret float %res
+}