diff --git a/llvm/lib/Target/X86/X86InstructionSelector.cpp b/llvm/lib/Target/X86/X86InstructionSelector.cpp --- a/llvm/lib/Target/X86/X86InstructionSelector.cpp +++ b/llvm/lib/Target/X86/X86InstructionSelector.cpp @@ -1435,7 +1435,7 @@ const Register DstReg = I.getOperand(0).getReg(); const LLT DstTy = MRI.getType(DstReg); const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); - unsigned Align = DstTy.getSizeInBits(); + unsigned Align = DstTy.getSizeInBits() / 8; const DebugLoc &DbgLoc = I.getDebugLoc(); unsigned Opc = getLoadStoreOp(DstTy, RegBank, TargetOpcode::G_LOAD, Align); diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fconstant.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fconstant.mir --- a/llvm/test/CodeGen/X86/GlobalISel/select-fconstant.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-fconstant.mir @@ -35,7 +35,7 @@ ; CHECK_NOPIC64: RET 0, implicit $xmm0 ; CHECK_LARGE64-LABEL: name: test_float ; CHECK_LARGE64: [[MOV64ri:%[0-9]+]]:gr64 = MOV64ri %const.0 - ; CHECK_LARGE64: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt [[MOV64ri]], 1, $noreg, 0, $noreg :: (load 8 from constant-pool, align 32) + ; CHECK_LARGE64: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt [[MOV64ri]], 1, $noreg, 0, $noreg :: (load 8 from constant-pool, align 4) ; CHECK_LARGE64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm_alt]] ; CHECK_LARGE64: $xmm0 = COPY [[COPY]] ; CHECK_LARGE64: RET 0, implicit $xmm0 @@ -82,7 +82,7 @@ ; CHECK_NOPIC64: RET 0, implicit $xmm0 ; CHECK_LARGE64-LABEL: name: test_double ; CHECK_LARGE64: [[MOV64ri:%[0-9]+]]:gr64 = MOV64ri %const.0 - ; CHECK_LARGE64: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt [[MOV64ri]], 1, $noreg, 0, $noreg :: (load 8 from constant-pool, align 64) + ; CHECK_LARGE64: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt [[MOV64ri]], 1, $noreg, 0, $noreg :: (load 8 from constant-pool) ; CHECK_LARGE64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm_alt]] ; CHECK_LARGE64: $xmm0 = COPY [[COPY]] ; CHECK_LARGE64: RET 0, implicit $xmm0