Index: llvm/lib/Target/SystemZ/SystemZInstrFormats.td =================================================================== --- llvm/lib/Target/SystemZ/SystemZInstrFormats.td +++ llvm/lib/Target/SystemZ/SystemZInstrFormats.td @@ -4773,7 +4773,9 @@ class MemFoldPseudo bytes, AddressingMode mode> : Pseudo<(outs cls:$R1), (ins cls:$R2, mode:$XBD2), []> { - let OpKey = mnemonic#"rk"#cls; + let OpKey = !subst("mscrk", "msrkc", + !subst("msgcrk", "msgrkc", + mnemonic#"rk"#cls)); let OpType = "mem"; let MemKey = mnemonic#cls; let MemType = "pseudo"; Index: llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp =================================================================== --- llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -1176,7 +1176,7 @@ // commutable, try to change R into . unsigned NumOps = MI.getNumExplicitOperands(); int MemOpcode = SystemZ::getMemOpcode(Opcode); - if (MemOpcode == -1) + if (VRM == nullptr || MemOpcode == -1 || return nullptr; // Try to swap compare operands if possible. @@ -1196,27 +1196,21 @@ } // See if this is a 3-address instruction that is convertible to 2-address - // and suitable for folding below. Only try this with virtual registers - // and a provided VRM (during regalloc). - if (SystemZ::getTwoOperandOpcode(Opcode) != -1) { - if (VRM == nullptr) + // and suitable for folding below. + if (NumOps == 3 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == -1) { + Register DstReg = MI.getOperand(0).getReg(); + Register DstPhys = + (Register::isVirtualRegister(DstReg) ? VRM->getPhys(DstReg) : DstReg); + Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg() + : ((OpNum == 1 && MI.isCommutable()) + ? MI.getOperand(2).getReg() + : Register())); + if (DstPhys && !SystemZ::GRH32BitRegClass.contains(DstPhys) && SrcReg && + Register::isVirtualRegister(SrcReg) && + DstPhys == VRM->getPhys(SrcReg)) + NeedsCommute = (OpNum == 1); + else return nullptr; - else { - assert(NumOps == 3 && "Expected two source registers."); - Register DstReg = MI.getOperand(0).getReg(); - Register DstPhys = - (Register::isVirtualRegister(DstReg) ? VRM->getPhys(DstReg) : DstReg); - Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg() - : ((OpNum == 1 && MI.isCommutable()) - ? MI.getOperand(2).getReg() - : Register())); - if (DstPhys && !SystemZ::GRH32BitRegClass.contains(DstPhys) && SrcReg && - Register::isVirtualRegister(SrcReg) && - DstPhys == VRM->getPhys(SrcReg)) - NeedsCommute = (OpNum == 1); - else - return nullptr; - } } if ((OpNum == NumOps - 1) || NeedsCommute) { Index: llvm/lib/Target/SystemZ/SystemZInstrInfo.td =================================================================== --- llvm/lib/Target/SystemZ/SystemZInstrInfo.td +++ llvm/lib/Target/SystemZ/SystemZInstrInfo.td @@ -1348,8 +1348,8 @@ // Multiplication of memory, setting the condition code. let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { - def MSC : BinaryRXY<"msc", 0xE353, null_frag, GR32, load, 4>; - def MSGC : BinaryRXY<"msgc", 0xE383, null_frag, GR64, load, 8>; + defm MSC : BinaryRXYAndPseudo<"msc", 0xE353, null_frag, GR32, load, 4>; + defm MSGC : BinaryRXYAndPseudo<"msgc", 0xE383, null_frag, GR64, load, 8>; } // Multiplication of a register, producing two results. Index: llvm/test/CodeGen/SystemZ/foldmemop-msc.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/SystemZ/foldmemop-msc.mir @@ -0,0 +1,219 @@ +# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z14 -start-before=greedy %s -o - \ +# RUN: | FileCheck %s +# +# Test folding of a memory operand into logical compare with an immediate. + +--- | + define i32 @fun0(i32* %src, i32 %arg) { ret i32 0 } + define i64 @fun1(i64* %src, i64 %arg) { ret i64 0 } + define i32 @fun2(i32* %src, i32 %arg) { ret i32 0 } + define i64 @fun3(i64* %src, i64 %arg) { ret i64 0 } +... + + +# CHECK-LABEL: fun0: +# CHECK-LABEL: .LBB0_2: +# CHECK: msc %r0, 164(%r15) # 4-byte Folded Reload +--- +name: fun0 +alignment: 16 +tracksRegLiveness: true +registers: + - { id: 0, class: grx32bit } + - { id: 1, class: grx32bit } + - { id: 2, class: addr64bit } + - { id: 3, class: gr32bit } + - { id: 4, class: grx32bit } + - { id: 5, class: grx32bit } + - { id: 6, class: gr32bit } + - { id: 7, class: gr32bit } + - { id: 8, class: gr32bit } +liveins: + - { reg: '$r2d', virtual-reg: '%2' } + - { reg: '$r3l', virtual-reg: '%3' } +frameInfo: + maxAlignment: 1 + hasOpaqueSPAdjustment: true +machineFunctionInfo: {} +body: | + bb.0: + successors: %bb.1(0x30000000), %bb.2(0x50000000) + liveins: $r2d, $r3l + + %3:gr32bit = COPY $r3l + %2:addr64bit = COPY $r2d + %6:gr32bit = LHIMux 0 + CHIMux %3, 0, implicit-def $cc + %8:gr32bit = LHIMux 0 + BRC 14, 6, %bb.2, implicit killed $cc + J %bb.1 + + bb.1: + %8:gr32bit = LMux %2, 0, $noreg :: (load 4 from %ir.src) + INLINEASM &"", 1, 12, implicit-def dead early-clobber $r0d, 12, implicit-def dead early-clobber $r1d, 12, implicit-def dead early-clobber $r2d, 12, implicit-def dead early-clobber $r3d, 12, implicit-def dead early-clobber $r4d, 12, implicit-def dead early-clobber $r5d, 12, implicit-def dead early-clobber $r6d, 12, implicit-def dead early-clobber $r7d, 12, implicit-def dead early-clobber $r8d, 12, implicit-def dead early-clobber $r9d, 12, implicit-def dead early-clobber $r10d, 12, implicit-def dead early-clobber $r11d, 12, implicit-def dead early-clobber $r12d, 12, implicit-def dead early-clobber $r13d, 12, implicit-def dead early-clobber $r14d, 12, implicit-def early-clobber $r15d + + bb.2: + INLINEASM &"", 1, 12, implicit-def dead early-clobber $r0d, 12, implicit-def dead early-clobber $r1d, 12, implicit-def dead early-clobber $r2d, 12, implicit-def dead early-clobber $r3d, 12, implicit-def dead early-clobber $r4d, 12, implicit-def dead early-clobber $r5d, 12, implicit-def dead early-clobber $r6d, 12, implicit-def dead early-clobber $r7d, 12, implicit-def dead early-clobber $r8d, 12, implicit-def dead early-clobber $r9d, 12, implicit-def dead early-clobber $r10d, 12, implicit-def dead early-clobber $r11d, 12, implicit-def dead early-clobber $r12d, 12, implicit-def dead early-clobber $r13d, 12, implicit-def dead early-clobber $r14d, 12, implicit-def early-clobber $r15d + %6:gr32bit = MSRKC %8, %6, implicit-def $cc + %6:gr32bit = LOCHIMux %6, 1, 14, 6, implicit killed $cc + %7:gr32bit = NRK %3, %6, implicit-def dead $cc + $r2l = COPY %7 + Return implicit $r2l + +... + + +# CHECK-LABEL: fun1: +# CHECK-LABEL: .LBB1_2: +# CHECK: msc %r0, 164(%r15) # 4-byte Folded Reload +--- +name: fun1 +alignment: 16 +tracksRegLiveness: true +registers: + - { id: 0, class: grx32bit } + - { id: 1, class: grx32bit } + - { id: 2, class: addr64bit } + - { id: 3, class: gr32bit } + - { id: 4, class: grx32bit } + - { id: 5, class: grx32bit } + - { id: 6, class: gr32bit } + - { id: 7, class: gr32bit } + - { id: 8, class: gr32bit } +liveins: + - { reg: '$r2d', virtual-reg: '%2' } + - { reg: '$r3l', virtual-reg: '%3' } +frameInfo: + maxAlignment: 1 + hasOpaqueSPAdjustment: true +machineFunctionInfo: {} +body: | + bb.0: + successors: %bb.1(0x30000000), %bb.2(0x50000000) + liveins: $r2d, $r3l + + %3:gr32bit = COPY $r3l + %2:addr64bit = COPY $r2d + %6:gr32bit = LHIMux 0 + CHIMux %3, 0, implicit-def $cc + %8:gr32bit = LHIMux 0 + BRC 14, 6, %bb.2, implicit killed $cc + J %bb.1 + + bb.1: + %8:gr32bit = LMux %2, 0, $noreg :: (load 4 from %ir.src) + INLINEASM &"", 1, 12, implicit-def dead early-clobber $r0d, 12, implicit-def dead early-clobber $r1d, 12, implicit-def dead early-clobber $r2d, 12, implicit-def dead early-clobber $r3d, 12, implicit-def dead early-clobber $r4d, 12, implicit-def dead early-clobber $r5d, 12, implicit-def dead early-clobber $r6d, 12, implicit-def dead early-clobber $r7d, 12, implicit-def dead early-clobber $r8d, 12, implicit-def dead early-clobber $r9d, 12, implicit-def dead early-clobber $r10d, 12, implicit-def dead early-clobber $r11d, 12, implicit-def dead early-clobber $r12d, 12, implicit-def dead early-clobber $r13d, 12, implicit-def dead early-clobber $r14d, 12, implicit-def early-clobber $r15d + + bb.2: + INLINEASM &"", 1, 12, implicit-def dead early-clobber $r0d, 12, implicit-def dead early-clobber $r1d, 12, implicit-def dead early-clobber $r2d, 12, implicit-def dead early-clobber $r3d, 12, implicit-def dead early-clobber $r4d, 12, implicit-def dead early-clobber $r5d, 12, implicit-def dead early-clobber $r6d, 12, implicit-def dead early-clobber $r7d, 12, implicit-def dead early-clobber $r8d, 12, implicit-def dead early-clobber $r9d, 12, implicit-def dead early-clobber $r10d, 12, implicit-def dead early-clobber $r11d, 12, implicit-def dead early-clobber $r12d, 12, implicit-def dead early-clobber $r13d, 12, implicit-def dead early-clobber $r14d, 12, implicit-def early-clobber $r15d + %6:gr32bit = MSRKC %6, %8, implicit-def $cc + %6:gr32bit = LOCHIMux %6, 1, 14, 6, implicit killed $cc + %7:gr32bit = NRK %3, %6, implicit-def dead $cc + $r2l = COPY %7 + Return implicit $r2l + +... + + +# CHECK-LABEL: fun2: +# CHECK-LABEL: .LBB2_2: +# CHECK: msgc %r0, 168(%r15) # 8-byte Folded Reload +--- +name: fun2 +alignment: 16 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64bit } + - { id: 1, class: gr64bit } + - { id: 2, class: addr64bit } + - { id: 3, class: gr64bit } + - { id: 4, class: gr64bit } + - { id: 5, class: gr64bit } + - { id: 6, class: gr64bit } + - { id: 7, class: gr64bit } + - { id: 8, class: gr64bit } +liveins: + - { reg: '$r2d', virtual-reg: '%2' } + - { reg: '$r3d', virtual-reg: '%3' } +frameInfo: + maxAlignment: 1 + hasOpaqueSPAdjustment: true +machineFunctionInfo: {} +body: | + bb.0: + successors: %bb.1(0x30000000), %bb.2(0x50000000) + liveins: $r2d, $r3d + + %3:gr64bit = COPY $r3d + %2:addr64bit = COPY $r2d + %6:gr64bit = LGHI 0 + CGHI %3, 0, implicit-def $cc + %8:gr64bit = LGHI 0 + BRC 14, 6, %bb.2, implicit killed $cc + J %bb.1 + + bb.1: + %8:gr64bit = LG %2, 0, $noreg :: (load 8 from %ir.src) + INLINEASM &"", 1, 12, implicit-def dead early-clobber $r0d, 12, implicit-def dead early-clobber $r1d, 12, implicit-def dead early-clobber $r2d, 12, implicit-def dead early-clobber $r3d, 12, implicit-def dead early-clobber $r4d, 12, implicit-def dead early-clobber $r5d, 12, implicit-def dead early-clobber $r6d, 12, implicit-def dead early-clobber $r7d, 12, implicit-def dead early-clobber $r8d, 12, implicit-def dead early-clobber $r9d, 12, implicit-def dead early-clobber $r10d, 12, implicit-def dead early-clobber $r11d, 12, implicit-def dead early-clobber $r12d, 12, implicit-def dead early-clobber $r13d, 12, implicit-def dead early-clobber $r14d, 12, implicit-def early-clobber $r15d + + bb.2: + INLINEASM &"", 1, 12, implicit-def dead early-clobber $r0d, 12, implicit-def dead early-clobber $r1d, 12, implicit-def dead early-clobber $r2d, 12, implicit-def dead early-clobber $r3d, 12, implicit-def dead early-clobber $r4d, 12, implicit-def dead early-clobber $r5d, 12, implicit-def dead early-clobber $r6d, 12, implicit-def dead early-clobber $r7d, 12, implicit-def dead early-clobber $r8d, 12, implicit-def dead early-clobber $r9d, 12, implicit-def dead early-clobber $r10d, 12, implicit-def dead early-clobber $r11d, 12, implicit-def dead early-clobber $r12d, 12, implicit-def dead early-clobber $r13d, 12, implicit-def dead early-clobber $r14d, 12, implicit-def early-clobber $r15d + %6:gr64bit = MSGRKC %8, %6, implicit-def $cc + %6:gr64bit = LOCGHI %6, 1, 14, 6, implicit killed $cc + %7:gr64bit = NGRK %3, %6, implicit-def dead $cc + $r2d = COPY %7 + Return implicit $r2d + +... + + +# CHECK-LABEL: fun3: +# CHECK-LABEL: .LBB3_2: +# CHECK: msgc %r0, 168(%r15) # 8-byte Folded Reload +--- +name: fun3 +alignment: 16 +tracksRegLiveness: true +registers: + - { id: 0, class: gr64bit } + - { id: 1, class: gr64bit } + - { id: 2, class: addr64bit } + - { id: 3, class: gr64bit } + - { id: 4, class: gr64bit } + - { id: 5, class: gr64bit } + - { id: 6, class: gr64bit } + - { id: 7, class: gr64bit } + - { id: 8, class: gr64bit } +liveins: + - { reg: '$r2d', virtual-reg: '%2' } + - { reg: '$r3d', virtual-reg: '%3' } +frameInfo: + maxAlignment: 1 + hasOpaqueSPAdjustment: true +machineFunctionInfo: {} +body: | + bb.0: + successors: %bb.1(0x30000000), %bb.2(0x50000000) + liveins: $r2d, $r3d + + %3:gr64bit = COPY $r3d + %2:addr64bit = COPY $r2d + %6:gr64bit = LGHI 0 + CGHI %3, 0, implicit-def $cc + %8:gr64bit = LGHI 0 + BRC 14, 6, %bb.2, implicit killed $cc + J %bb.1 + + bb.1: + %8:gr64bit = LG %2, 0, $noreg :: (load 8 from %ir.src) + INLINEASM &"", 1, 12, implicit-def dead early-clobber $r0d, 12, implicit-def dead early-clobber $r1d, 12, implicit-def dead early-clobber $r2d, 12, implicit-def dead early-clobber $r3d, 12, implicit-def dead early-clobber $r4d, 12, implicit-def dead early-clobber $r5d, 12, implicit-def dead early-clobber $r6d, 12, implicit-def dead early-clobber $r7d, 12, implicit-def dead early-clobber $r8d, 12, implicit-def dead early-clobber $r9d, 12, implicit-def dead early-clobber $r10d, 12, implicit-def dead early-clobber $r11d, 12, implicit-def dead early-clobber $r12d, 12, implicit-def dead early-clobber $r13d, 12, implicit-def dead early-clobber $r14d, 12, implicit-def early-clobber $r15d + + bb.2: + INLINEASM &"", 1, 12, implicit-def dead early-clobber $r0d, 12, implicit-def dead early-clobber $r1d, 12, implicit-def dead early-clobber $r2d, 12, implicit-def dead early-clobber $r3d, 12, implicit-def dead early-clobber $r4d, 12, implicit-def dead early-clobber $r5d, 12, implicit-def dead early-clobber $r6d, 12, implicit-def dead early-clobber $r7d, 12, implicit-def dead early-clobber $r8d, 12, implicit-def dead early-clobber $r9d, 12, implicit-def dead early-clobber $r10d, 12, implicit-def dead early-clobber $r11d, 12, implicit-def dead early-clobber $r12d, 12, implicit-def dead early-clobber $r13d, 12, implicit-def dead early-clobber $r14d, 12, implicit-def early-clobber $r15d + %6:gr64bit = MSGRKC %6, %8, implicit-def $cc + %6:gr64bit = LOCGHI %6, 1, 14, 6, implicit killed $cc + %7:gr64bit = NGRK %3, %6, implicit-def dead $cc + $r2d = COPY %7 + Return implicit $r2d + +...