Index: llvm/lib/Target/ARM/ARM.h =================================================================== --- llvm/lib/Target/ARM/ARM.h +++ llvm/lib/Target/ARM/ARM.h @@ -47,6 +47,7 @@ FunctionPass *createMLxExpansionPass(); FunctionPass *createThumb2ITBlockPass(); FunctionPass *createMVEVPTBlockPass(); +FunctionPass *createMVEVPTOptimisationsPass(); FunctionPass *createARMOptimizeBarriersPass(); FunctionPass *createThumb2SizeReductionPass( std::function Ftor = nullptr); @@ -66,6 +67,7 @@ void initializeThumb2SizeReducePass(PassRegistry &); void initializeThumb2ITBlockPass(PassRegistry &); void initializeMVEVPTBlockPass(PassRegistry &); +void initializeMVEVPTOptimisationsPass(PassRegistry &); void initializeARMLowOverheadLoopsPass(PassRegistry &); void initializeMVETailPredicationPass(PassRegistry &); void initializeMVEGatherScatterLoweringPass(PassRegistry &); Index: llvm/lib/Target/ARM/ARMTargetMachine.cpp =================================================================== --- llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -96,6 +96,7 @@ initializeARMExpandPseudoPass(Registry); initializeThumb2SizeReducePass(Registry); initializeMVEVPTBlockPass(Registry); + initializeMVEVPTOptimisationsPass(Registry); initializeMVETailPredicationPass(Registry); initializeARMLowOverheadLoopsPass(Registry); initializeMVEGatherScatterLoweringPass(Registry); @@ -486,6 +487,8 @@ void ARMPassConfig::addPreRegAlloc() { if (getOptLevel() != CodeGenOpt::None) { + addPass(createMVEVPTOptimisationsPass()); + addPass(createMLxExpansionPass()); if (EnableARMLoadStoreOpt) Index: llvm/lib/Target/ARM/CMakeLists.txt =================================================================== --- llvm/lib/Target/ARM/CMakeLists.txt +++ llvm/lib/Target/ARM/CMakeLists.txt @@ -54,6 +54,7 @@ MVEGatherScatterLowering.cpp MVETailPredication.cpp MVEVPTBlockPass.cpp + MVEVPTOptimisationsPass.cpp Thumb1FrameLowering.cpp Thumb1InstrInfo.cpp ThumbRegisterInfo.cpp Index: llvm/lib/Target/ARM/MVEVPTOptimisationsPass.cpp =================================================================== --- /dev/null +++ llvm/lib/Target/ARM/MVEVPTOptimisationsPass.cpp @@ -0,0 +1,222 @@ +//===-- MVEVPTOptimisationsPass.cpp ---------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +/// \file This pass does a few optimisations related to MVE VPT blocks before +/// register allocation is performed. The goal is to maximize the sizes of the +/// blocks that will be created by the MVE VPT Block Insertion pass (which runs +/// after register allocation). Currently, this pass replaces VCMPs with VPNOTs +/// when possible, so the Block Insertion pass can delete them later to create +/// larger VPT blocks. +//===----------------------------------------------------------------------===// + +#include "ARM.h" +#include "ARMSubtarget.h" +#include "MCTargetDesc/ARMBaseInfo.h" +#include "Thumb2InstrInfo.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/Support/Debug.h" +#include + +using namespace llvm; + +#define DEBUG_TYPE "arm-mve-vpt-opts" + +namespace { +class MVEVPTOptimisations : public MachineFunctionPass { +public: + static char ID; + const Thumb2InstrInfo *TII; + MachineRegisterInfo *MRI; + + MVEVPTOptimisations() : MachineFunctionPass(ID) {} + + bool runOnMachineFunction(MachineFunction &Fn) override; + + StringRef getPassName() const override { return "MVE VPT Optimisation Pass"; } + +private: + MachineInstrBuilder BuildVPNOTBefore(MachineBasicBlock &MBB, + MachineInstr &Instr); + MachineInstr &ReplaceUsageOfRegisterByVPNOT(MachineBasicBlock &MBB, + MachineInstr &Instr, + unsigned OpIdx, Register Target); + bool InsertVPNOTs(MachineBasicBlock &MBB); +}; + +char MVEVPTOptimisations::ID = 0; + +} // end anonymous namespace + +INITIALIZE_PASS(MVEVPTOptimisations, DEBUG_TYPE, + "ARM MVE VPT Optimisations pass", false, false) + +// Returns true if Opcode is any VCMP Opcode. +static bool IsVCMP(unsigned Opcode) { return VCMPOpcodeToVPT(Opcode) != 0; } + +// Returns true if a VCMP with this Opcode can have its operands swapped. +// There is 2 kind of VCMP that can't have their operands swapped: Float VCMPs, +// and VCMPr instructions (since the r is always on the right). +static bool CanHaveSwappedOperands(unsigned Opcode) { + switch (Opcode) { + default: + return true; + case ARM::MVE_VCMPf32: + case ARM::MVE_VCMPf16: + case ARM::MVE_VCMPf32r: + case ARM::MVE_VCMPf16r: + case ARM::MVE_VCMPi8r: + case ARM::MVE_VCMPi16r: + case ARM::MVE_VCMPi32r: + case ARM::MVE_VCMPu8r: + case ARM::MVE_VCMPu16r: + case ARM::MVE_VCMPu32r: + case ARM::MVE_VCMPs8r: + case ARM::MVE_VCMPs16r: + case ARM::MVE_VCMPs32r: + return false; + } +} + +// Returns the CondCode of a VCMP Instruction. +static ARMCC::CondCodes GetCondCode(MachineInstr &Instr) { + assert(IsVCMP(Instr.getOpcode()) && "Inst must be a VCMP"); + return ARMCC::CondCodes(Instr.getOperand(3).getImm()); +} + +// Returns true if Cond is equivalent to a VPNOT instruction on the result of +// Prev. Cond and Prev must be VCMPs. +static bool IsVPNOTEquivalent(MachineInstr &Cond, MachineInstr &Prev) { + assert(IsVCMP(Cond.getOpcode()) && IsVCMP(Prev.getOpcode())); + + // Opcodes must match. + if (Cond.getOpcode() != Prev.getOpcode()) + return false; + + MachineOperand &CondOP1 = Cond.getOperand(1), &CondOP2 = Cond.getOperand(2); + MachineOperand &PrevOP1 = Prev.getOperand(1), &PrevOP2 = Prev.getOperand(2); + + // If the VCMP has the opposite condition with the same operands, we can + // replace it with a VPNOT + ARMCC::CondCodes ExpectedCode = GetCondCode(Cond); + ExpectedCode = ARMCC::getOppositeCondition(ExpectedCode); + if (ExpectedCode == GetCondCode(Prev)) + if (CondOP1.isIdenticalTo(PrevOP1) && CondOP2.isIdenticalTo(PrevOP2)) + return true; + // Check again with operands swapped if possible + if (!CanHaveSwappedOperands(Cond.getOpcode())) + return false; + ExpectedCode = ARMCC::getSwappedCondition(ExpectedCode); + return ExpectedCode == GetCondCode(Prev) && CondOP1.isIdenticalTo(PrevOP2) && + CondOP2.isIdenticalTo(PrevOP1); +} + +// Returns true if Instr writes to VCCR or VPR. +static bool IsWritingToVCCRorVPR(MachineInstr &Instr) { + if (Instr.getNumOperands() == 0) + return false; + if (Instr.definesRegister(ARM::VPR)) + return true; + MachineOperand &Dst = Instr.getOperand(0); + if (!Dst.isReg()) + return false; + Register DstReg = Dst.getReg(); + if (!DstReg.isVirtual()) + return false; + MachineRegisterInfo &RegInfo = Instr.getMF()->getRegInfo(); + const TargetRegisterClass *RegClass = RegInfo.getRegClassOrNull(DstReg); + return RegClass && (RegClass->getID() == ARM::VCCRRegClassID); +} + +// Creates a VPNOT before Instr. +MachineInstrBuilder +MVEVPTOptimisations::BuildVPNOTBefore(MachineBasicBlock &MBB, + MachineInstr &Instr) { + return BuildMI(MBB, &Instr, Instr.getDebugLoc(), TII->get(ARM::MVE_VPNOT)); +} + +bool MVEVPTOptimisations::InsertVPNOTs(MachineBasicBlock &MBB) { + SmallVector DeadInstructions; + + // The last VCMP that we have seen and that couldn't be replaced. + // This is reset when an instruction that writes to VCCR/VPR is found, or when + // a VCMP is replaced with a VPNOT. + // We'll only replace VCMPs with VPNOTs when this is not null, and when the + // current VCMP is the opposite of PrevVCMP. + MachineInstr *PrevVCMP = nullptr; + + for (MachineInstr &Instr : MBB.instrs()) { + // Ignore predicated instructions. + if (getVPTInstrPredicate(Instr) != ARMVCC::None) + continue; + + // Only look at VCMPs + if (!IsVCMP(Instr.getOpcode())) { + // If the instruction writes to VPR (VCCR), forget the previous VCMP. + if (IsWritingToVCCRorVPR(Instr)) + PrevVCMP = nullptr; + continue; + } + + if (!PrevVCMP || !IsVPNOTEquivalent(Instr, *PrevVCMP)) { + PrevVCMP = &Instr; + continue; + } + + // The register containing the result of the VCMP that we're going to + // replace. + Register PrevVCMPResultReg = PrevVCMP->getOperand(0).getReg(); + + // Build a VPNOT to replace the VCMP, reusing its operands. + MachineInstrBuilder MIBuilder = BuildVPNOTBefore(MBB, Instr); + MIBuilder.add(Instr.getOperand(0)); + MIBuilder.addReg(PrevVCMPResultReg); + MIBuilder.add(Instr.getOperand(4)); + MIBuilder.add(Instr.getOperand(5)); + LLVM_DEBUG(dbgs() << " Inserting VPNOT (to replace VCMP): "; + MIBuilder.getInstr()->dump()); + + // Finally, mark the old VCMP for removal and reset PrevVCMP. + DeadInstructions.push_back(&Instr); + PrevVCMP = nullptr; + } + + for (MachineInstr *DeadInstruction : DeadInstructions) + DeadInstruction->removeFromParent(); + + return !DeadInstructions.empty(); +} + +bool MVEVPTOptimisations::runOnMachineFunction(MachineFunction &Fn) { + const ARMSubtarget &STI = + static_cast(Fn.getSubtarget()); + + if (!STI.isThumb2() || !STI.hasMVEIntegerOps()) + return false; + + TII = static_cast(STI.getInstrInfo()); + MRI = &Fn.getRegInfo(); + + LLVM_DEBUG(dbgs() << "********** ARM MVE VPT Optimisations **********\n" + << "********** Function: " << Fn.getName() << '\n'); + + bool Modified = false; + for (MachineBasicBlock &MBB : Fn) + Modified |= InsertVPNOTs(MBB); + + LLVM_DEBUG(dbgs() << "**************************************\n"); + return Modified; +} + +/// createMVEVPTOptimisationsPass +FunctionPass *llvm::createMVEVPTOptimisationsPass() { + return new MVEVPTOptimisations(); +} Index: llvm/test/CodeGen/ARM/O3-pipeline.ll =================================================================== --- llvm/test/CodeGen/ARM/O3-pipeline.ll +++ llvm/test/CodeGen/ARM/O3-pipeline.ll @@ -92,6 +92,7 @@ ; CHECK-NEXT: Machine code sinking ; CHECK-NEXT: Peephole Optimizations ; CHECK-NEXT: Remove dead machine instructions +; CHECK-NEXT: MVE VPT Optimisation Pass ; CHECK-NEXT: ARM MLA / MLS expansion pass ; CHECK-NEXT: ARM pre- register allocation load / store optimization pass ; CHECK-NEXT: ARM A15 S->D optimizer Index: llvm/test/CodeGen/Thumb2/mve-vpt-optimisations.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/Thumb2/mve-vpt-optimisations.mir @@ -0,0 +1,521 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -run-pass arm-mve-vpt-opts %s -o - | FileCheck %s + +--- | + target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" + target triple = "thumbv8.1m.main-arm-none-eabi" + + ; Functions are intentionally left blank - see the MIR sequences below. + + define arm_aapcs_vfpcc <4 x float> @vcmp_with_opposite_cond(<4 x float> %inactive1) #0 { + entry: + ret <4 x float> %inactive1 + } + + define arm_aapcs_vfpcc <4 x float> @vcmp_with_opposite_cond_and_swapped_operands(<4 x float> %inactive1) #0 { + entry: + ret <4 x float> %inactive1 + } + + define arm_aapcs_vfpcc <4 x float> @triple_vcmp(<4 x float> %inactive1) #0 { + entry: + ret <4 x float> %inactive1 + } + + define arm_aapcs_vfpcc <4 x float> @flt_with_swapped_operands(<4 x float> %inactive1) #0 { + entry: + ret <4 x float> %inactive1 + } + + define arm_aapcs_vfpcc <4 x float> @different_opcodes(<4 x float> %inactive1) #0 { + entry: + ret <4 x float> %inactive1 + } + + define arm_aapcs_vfpcc <4 x float> @incorrect_condcode(<4 x float> %inactive1) #0 { + entry: + ret <4 x float> %inactive1 + } + + define arm_aapcs_vfpcc <4 x float> @vpr_or_vccr_write_between_vcmps(<4 x float> %inactive1) #0 { + entry: + ret <4 x float> %inactive1 + } + + attributes #0 = { "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" } +... +--- +name: vcmp_with_opposite_cond +alignment: 4 +liveins: + - { reg: '$q0', virtual-reg: '' } + - { reg: '$q1', virtual-reg: '' } + - { reg: '$r0', virtual-reg: '' } + - { reg: '$zr', virtual-reg: '' } +body: | + ; CHECK-LABEL: name: vcmp_with_opposite_cond + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPf16 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.1: + ; CHECK: successors: %bb.2(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPf32 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.2: + ; CHECK: successors: %bb.3(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPi16 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.3: + ; CHECK: successors: %bb.4(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPi32 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.4: + ; CHECK: successors: %bb.5(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPi8 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.5: + ; CHECK: successors: %bb.6(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPs16 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.6: + ; CHECK: successors: %bb.7(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.7: + ; CHECK: successors: %bb.8(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPs8 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.8: + ; CHECK: successors: %bb.9(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPu16 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.9: + ; CHECK: successors: %bb.10(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.10: + ; CHECK: successors: %bb.11(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPu8 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.11: + ; CHECK: successors: %bb.12(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPf16r renamable $q0, renamable $r0, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.12: + ; CHECK: successors: %bb.13(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPf32r renamable $q0, renamable $r0, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.13: + ; CHECK: successors: %bb.14(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPi16r renamable $q0, renamable $r0, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.14: + ; CHECK: successors: %bb.15(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPi32r renamable $q0, renamable $r0, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.15: + ; CHECK: successors: %bb.16(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPi8r renamable $q0, renamable $r0, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.16: + ; CHECK: successors: %bb.17(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPs16r renamable $q0, renamable $r0, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.17: + ; CHECK: successors: %bb.18(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r0, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.18: + ; CHECK: successors: %bb.19(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPs8r renamable $q0, renamable $r0, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.19: + ; CHECK: successors: %bb.20(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPu16r renamable $q0, renamable $r0, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.20: + ; CHECK: successors: %bb.21(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPu32r renamable $q0, renamable $r0, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.21: + ; CHECK: successors: %bb.22(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPu8r renamable $q0, renamable $r0, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.22: + ; CHECK: renamable $vpr = MVE_VCMPu8r renamable $q0, $zr, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 + ; + ; Tests that VCMPs with an opposite condition are correctly converted into VPNOTs. + ; + bb.0: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPf16 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPf16 renamable $q0, renamable $q1, 11, 0, $noreg + + bb.1: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPf32 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPf32 renamable $q0, renamable $q1, 11, 0, $noreg + + bb.2: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPi16 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPi16 renamable $q0, renamable $q1, 11, 0, $noreg + + bb.3: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPi32 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPi32 renamable $q0, renamable $q1, 11, 0, $noreg + + bb.4: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPi8 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPi8 renamable $q0, renamable $q1, 11, 0, $noreg + + bb.5: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPs16 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPs16 renamable $q0, renamable $q1, 11, 0, $noreg + + bb.6: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 11, 0, $noreg + + bb.7: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPs8 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPs8 renamable $q0, renamable $q1, 11, 0, $noreg + + bb.8: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPu16 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPu16 renamable $q0, renamable $q1, 11, 0, $noreg + + bb.9: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q1, 11, 0, $noreg + + bb.10: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPu8 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPu8 renamable $q0, renamable $q1, 11, 0, $noreg + + bb.11: + liveins: $q0, $r0 + renamable $vpr = MVE_VCMPf16r renamable $q0, renamable $r0, 10, 0, $noreg + renamable $vpr = MVE_VCMPf16r renamable $q0, renamable $r0, 11, 0, $noreg + + bb.12: + liveins: $q0, $r0 + renamable $vpr = MVE_VCMPf32r renamable $q0, renamable $r0, 10, 0, $noreg + renamable $vpr = MVE_VCMPf32r renamable $q0, renamable $r0, 11, 0, $noreg + + bb.13: + liveins: $q0, $r0 + renamable $vpr = MVE_VCMPi16r renamable $q0, renamable $r0, 10, 0, $noreg + renamable $vpr = MVE_VCMPi16r renamable $q0, renamable $r0, 11, 0, $noreg + + bb.14: + liveins: $q0, $r0 + renamable $vpr = MVE_VCMPi32r renamable $q0, renamable $r0, 10, 0, $noreg + renamable $vpr = MVE_VCMPi32r renamable $q0, renamable $r0, 11, 0, $noreg + + bb.15: + liveins: $q0, $r0 + renamable $vpr = MVE_VCMPi8r renamable $q0, renamable $r0, 10, 0, $noreg + renamable $vpr = MVE_VCMPi8r renamable $q0, renamable $r0, 11, 0, $noreg + + bb.16: + liveins: $q0, $r0 + renamable $vpr = MVE_VCMPs16r renamable $q0, renamable $r0, 10, 0, $noreg + renamable $vpr = MVE_VCMPs16r renamable $q0, renamable $r0, 11, 0, $noreg + + bb.17: + liveins: $q0, $r0 + renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r0, 10, 0, $noreg + renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r0, 11, 0, $noreg + + bb.18: + liveins: $q0, $r0 + renamable $vpr = MVE_VCMPs8r renamable $q0, renamable $r0, 10, 0, $noreg + renamable $vpr = MVE_VCMPs8r renamable $q0, renamable $r0, 11, 0, $noreg + + bb.19: + liveins: $q0, $r0 + renamable $vpr = MVE_VCMPu16r renamable $q0, renamable $r0, 10, 0, $noreg + renamable $vpr = MVE_VCMPu16r renamable $q0, renamable $r0, 11, 0, $noreg + + bb.20: + liveins: $q0, $r0 + renamable $vpr = MVE_VCMPu32r renamable $q0, renamable $r0, 10, 0, $noreg + renamable $vpr = MVE_VCMPu32r renamable $q0, renamable $r0, 11, 0, $noreg + + bb.21: + liveins: $q0, $r0 + renamable $vpr = MVE_VCMPu8r renamable $q0, renamable $r0, 10, 0, $noreg + renamable $vpr = MVE_VCMPu8r renamable $q0, renamable $r0, 11, 0, $noreg + + bb.22: + ; There shouldn't be any exception for $zr, so the second VCMP should + ; be transformed into a VPNOT. + liveins: $q0, $zr + renamable $vpr = MVE_VCMPu8r renamable $q0, $zr, 10, 0, $noreg + renamable $vpr = MVE_VCMPu8r renamable $q0, $zr, 11, 0, $noreg + + tBX_RET 14, $noreg, implicit $q0 +... +--- +name: vcmp_with_opposite_cond_and_swapped_operands +alignment: 4 +liveins: + - { reg: '$q0', virtual-reg: '' } + - { reg: '$q1', virtual-reg: '' } +body: | + ; CHECK-LABEL: name: vcmp_with_opposite_cond_and_swapped_operands + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPi16 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.1: + ; CHECK: successors: %bb.2(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPi32 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.2: + ; CHECK: successors: %bb.3(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPi8 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.3: + ; CHECK: successors: %bb.4(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPs16 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.4: + ; CHECK: successors: %bb.5(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.5: + ; CHECK: successors: %bb.6(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPs8 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.6: + ; CHECK: successors: %bb.7(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPu16 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.7: + ; CHECK: successors: %bb.8(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: bb.8: + ; CHECK: renamable $vpr = MVE_VCMPu8 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 + ; + ; Tests that VCMPs with an opposite condition and swapped operands are + ; correctly converted into VPNOTs. + ; + bb.0: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPi16 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPi16 renamable $q1, renamable $q0, 12, 0, $noreg + + bb.1: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPi32 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPi32 renamable $q1, renamable $q0, 12, 0, $noreg + + bb.2: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPi8 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPi8 renamable $q1, renamable $q0, 12, 0, $noreg + + bb.3: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPs16 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPs16 renamable $q1, renamable $q0, 12, 0, $noreg + + bb.4: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPs32 renamable $q1, renamable $q0, 12, 0, $noreg + + bb.5: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPs8 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPs8 renamable $q1, renamable $q0, 12, 0, $noreg + + bb.6: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPu16 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPu16 renamable $q1, renamable $q0, 12, 0, $noreg + + bb.7: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 12, 0, $noreg + + bb.8: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPu8 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPu8 renamable $q1, renamable $q0, 12, 0, $noreg + + tBX_RET 14, $noreg, implicit $q0 +... +--- +name: triple_vcmp +alignment: 4 +liveins: + - { reg: '$q0', virtual-reg: '' } + - { reg: '$q1', virtual-reg: '' } +body: | + ; + ; Tests that, when there are 2 "VPNOT-like VCMPs" in a row, only the first + ; becomes a VPNOT. + ; + bb.0: + liveins: $q0, $q1 + ; CHECK-LABEL: name: triple_vcmp + ; CHECK: renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT $vpr, 0, $noreg + ; CHECK: renamable $vpr = MVE_VCMPs32 renamable $q1, renamable $q0, 12, 0, $noreg + ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 + renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPs32 renamable $q1, renamable $q0, 12, 0, $noreg + renamable $vpr = MVE_VCMPs32 renamable $q1, renamable $q0, 12, 0, $noreg + tBX_RET 14, $noreg, implicit $q0 +... +--- +name: flt_with_swapped_operands +alignment: 4 +liveins: + - { reg: '$q0', virtual-reg: '' } + - { reg: '$q1', virtual-reg: '' } +body: | + ; CHECK-LABEL: name: flt_with_swapped_operands + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPf16 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VCMPf16 renamable $q1, renamable $q0, 12, 0, $noreg + ; CHECK: bb.1: + ; CHECK: successors: %bb.2(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPf32 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 0, $noreg + ; CHECK: bb.2: + ; CHECK: successors: %bb.3(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPf16 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VCMPf16 renamable $q1, renamable $q0, 11, 0, $noreg + ; CHECK: bb.3: + ; CHECK: renamable $vpr = MVE_VCMPf32 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 11, 0, $noreg + ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 + ; + ; Tests that float VCMPs with an opposite condition and swapped operands + ; are not transformed into VPNOTs. + ; + bb.1: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPf16 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPf16 renamable $q1, renamable $q0, 12, 0, $noreg + + bb.2: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPf32 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 0, $noreg + + bb.3: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPf16 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPf16 renamable $q1, renamable $q0, 11, 0, $noreg + + bb.4: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPf32 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 11, 0, $noreg + tBX_RET 14, $noreg, implicit $q0 +... +--- +name: different_opcodes +alignment: 4 +liveins: + - { reg: '$q0', virtual-reg: '' } + - { reg: '$q1', virtual-reg: '' } +body: | + ; + ; Tests that a "VPNOT-like VCMP" with an opcode different from the previous VCMP + ; is not transformed into a VPNOT. + ; + bb.0: + liveins: $q0, $q1 + ; CHECK-LABEL: name: different_opcodes + ; CHECK: renamable $vpr = MVE_VCMPf16 renamable $q0, renamable $q1, 0, 0, $noreg + ; CHECK: renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 1, 0, $noreg + ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 + renamable $vpr = MVE_VCMPf16 renamable $q0, renamable $q1, 0, 0, $noreg + renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 1, 0, $noreg + tBX_RET 14, $noreg, implicit $q0 +... +--- +name: incorrect_condcode +alignment: 4 +liveins: + - { reg: '$q0', virtual-reg: '' } + - { reg: '$q1', virtual-reg: '' } +body: | + ; CHECK-LABEL: name: incorrect_condcode + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VCMPs32 renamable $q1, renamable $q0, 11, 0, $noreg + ; CHECK: bb.1: + ; CHECK: renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 10, 0, $noreg + ; CHECK: renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 12, 0, $noreg + ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 + ; + ; Tests that a VCMP is not transformed into a VPNOT if its CondCode is not + ; the opposite CondCode. + ; + bb.0: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPs32 renamable $q1, renamable $q0, 11, 0, $noreg + bb.1: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 10, 0, $noreg + renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 12, 0, $noreg + tBX_RET 14, $noreg, implicit $q0 +... +--- +name: vpr_or_vccr_write_between_vcmps +alignment: 4 +liveins: + - { reg: '$q0', virtual-reg: '' } + - { reg: '$q1', virtual-reg: '' } +body: | + ; CHECK-LABEL: name: vpr_or_vccr_write_between_vcmps + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 11, 0, $noreg + ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg + ; CHECK: renamable $vpr = MVE_VCMPs32 renamable $q1, renamable $q0, 13, 0, $noreg + ; CHECK: bb.1: + ; CHECK: renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 12, 0, $noreg + ; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT killed renamable $vpr, 0, $noreg + ; CHECK: renamable $vpr = MVE_VCMPs32 renamable $q1, renamable $q0, 10, 0, $noreg + ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 + ; + ; Tests that a "VPNOT-like VCMP" will not be transformed into a VPNOT if + ; VCCR/VPR is written to in-between. + ; + bb.0: + liveins: $q0, $q1 + renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 11, 0, $noreg + renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg + renamable $vpr = MVE_VCMPs32 renamable $q1, renamable $q0, 13, 0, $noreg + bb.1: + renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q1, 12, 0, $noreg + %0:vccr = MVE_VPNOT killed renamable $vpr, 0, $noreg + renamable $vpr = MVE_VCMPs32 renamable $q1, renamable $q0, 10, 0, $noreg + tBX_RET 14, $noreg, implicit $q0 +...