Index: llvm/lib/Target/ARM/ARMInstrMVE.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrMVE.td
+++ llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -607,6 +607,7 @@
let Inst{3-1} = Qm{2-0};
let Inst{0} = 0b0;
let horizontalReduction = 1;
+ let validForTailPredication = 1;
}
def ARMVADDVs : SDNode<"ARMISD::VADDVs", SDTVecReduce>;
Index: llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -550,6 +550,12 @@
return (Flags & ARMII::RetainsPreviousHalfElement) != 0;
}
+static bool isHorizontalReduction(const MachineInstr &MI) {
+ const MCInstrDesc &MCID = MI.getDesc();
+ uint64_t Flags = MCID.TSFlags;
+ return (Flags & ARMII::HorizontalReduction) != 0;
+}
+
// Look at its register uses to see if it only can only receive zeros
// into its false lanes which would then produce zeros. Also check that
// the output register is also defined by an FalseLaneZeros instruction
@@ -561,9 +567,13 @@
InstSet &FalseLaneZeros) {
if (canGenerateNonZeros(MI))
return false;
+
+ bool AllowScalars = isHorizontalReduction(MI);
for (auto &MO : MI.operands()) {
if (!MO.isReg() || !MO.getReg())
continue;
+ if (!isRegInClass(MO, QPRs) && AllowScalars)
+ continue;
if (auto *OpDef = RDA.getMIOperand(&MI, MO))
if (FalseLaneZeros.count(OpDef))
continue;
@@ -607,6 +617,9 @@
if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
continue;
+ if (isVCTP(&MI) || MI.getOpcode() == ARM::MVE_VPST)
+ continue;
+
if (isVectorPredicated(&MI)) {
if (MI.mayLoad())
FalseLaneZeros.insert(&MI);
@@ -617,12 +630,13 @@
if (MI.getNumDefs() == 0)
continue;
- if (producesFalseLaneZeros(MI, QPRs, RDA, FalseLaneZeros))
+ if (!producesFalseLaneZeros(MI, QPRs, RDA, FalseLaneZeros)) {
+ if (retainsPreviousHalfElement(MI) || isHorizontalReduction(MI))
+ return false;
+ else
+ Unknown.insert(&MI);
+ } else if (!isHorizontalReduction(MI))
FalseLaneZeros.insert(&MI);
- else if (retainsPreviousHalfElement(MI))
- return false;
- else
- Unknown.insert(&MI);
}
auto HasPredicatedUsers = [this](MachineInstr *MI, const MachineOperand &MO,
Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir
===================================================================
--- llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir
+++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir
@@ -751,6 +751,53 @@
ret i32 %res
}
+ define hidden i64 @illegal_scalar_reg_use(i16* %x, i16* %y, i16* %z, i32 %n, i32 %arg) local_unnamed_addr #0 {
+ entry:
+ %cmp22 = icmp sgt i32 %n, 0
+ %0 = add i32 %n, 7
+ %1 = icmp slt i32 %n, 8
+ %smin = select i1 %1, i32 %n, i32 8
+ %2 = sub i32 %0, %smin
+ %3 = lshr i32 %2, 3
+ %4 = add nuw nsw i32 %3, 1
+ br i1 %cmp22, label %while.body.preheader, label %while.end
+
+ while.body.preheader: ; preds = %entry
+ call void @llvm.set.loop.iterations.i32(i32 %4)
+ br label %while.body
+
+ while.body: ; preds = %while.body.preheader, %while.body
+ %x.addr.026 = phi i16* [ %add.ptr, %while.body ], [ %x, %while.body.preheader ]
+ %y.addr.025 = phi i16* [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ]
+ %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ]
+ %acc = phi i64 [ %acc.next, %while.body ], [ 0, %while.body.preheader ]
+ %5 = phi i32 [ %4, %while.body.preheader ], [ %6, %while.body ]
+ %tmp3 = bitcast i16* %y.addr.025 to <4 x i16>*
+ %tmp1 = bitcast i16* %x.addr.026 to <4 x i16>*
+ %tmp = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %n.addr.023)
+ %tmp2 = tail call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %tmp1, i32 2, <4 x i1> %tmp, <4 x i16> zeroinitializer)
+ %tmp4 = tail call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %tmp3, i32 2, <4 x i1> %tmp, <4 x i16> zeroinitializer)
+ %tmp5 = zext <4 x i16> %tmp2 to <4 x i32>
+ %tmp6 = zext <4 x i16> %tmp4 to <4 x i32>
+ %add = add <4 x i32> %tmp5, %tmp6
+ %splatinsert = insertelement <4 x i32> undef, i32 %arg, i32 0
+ %splat = shufflevector <4 x i32> %splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
+ %vsub = sub <4 x i32> %add, %splat
+ %reduce = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %vsub)
+ %reduce64 = zext i32 %reduce to i64
+ %acc.next = add i64 %reduce64, %acc
+ %add.ptr = getelementptr inbounds i16, i16* %x.addr.026, i32 8
+ %add.ptr4 = getelementptr inbounds i16, i16* %y.addr.025, i32 8
+ %sub = add nsw i32 %n.addr.023, -8
+ %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)
+ %7 = icmp ne i32 %6, 0
+ br i1 %7, label %while.body, label %while.end
+
+ while.end: ; preds = %while.body, %entry
+ %res = phi i64 [ 0, %entry ], [ %acc.next, %while.body ]
+ ret i64 %res
+ }
+
declare <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>*, i32 immarg, <8 x i1>, <8 x i8>)
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>)
@@ -812,25 +859,14 @@
; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 8, implicit-def $itstate
; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
- ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: dead $lr = t2DLS renamable $r12
- ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
- ; CHECK: MVE_VPST 8, implicit $vpr
- ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
+ ; CHECK: liveins: $lr, $r0, $r1
+ ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg :: (load 8 from %ir.lsr.iv17, align 2)
; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
- ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr)
- ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
- ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.exit:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry:
@@ -914,25 +950,14 @@
; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 8, implicit-def $itstate
; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
- ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: dead $lr = t2DLS renamable $r12
- ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
+ ; CHECK: $lr = MVE_DLSTP_16 killed renamable $r2
; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg
- ; CHECK: MVE_VPST 8, implicit $vpr
- ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 2)
+ ; CHECK: liveins: $lr, $r0, $r1
+ ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg :: (load 16 from %ir.lsr.iv17, align 2)
; CHECK: renamable $r12 = MVE_VADDVs16no_acc killed renamable $q0, 0, $noreg
- ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr)
- ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg
- ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.exit:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry:
@@ -1016,25 +1041,14 @@
; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 8, implicit-def $itstate
; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
- ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: dead $lr = t2DLS renamable $r12
- ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
+ ; CHECK: $lr = MVE_DLSTP_8 killed renamable $r2
; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg
- ; CHECK: MVE_VPST 8, implicit $vpr
- ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1)
+ ; CHECK: liveins: $lr, $r0, $r1
+ ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU8_post killed renamable $r0, 16, 0, killed $noreg :: (load 16 from %ir.lsr.iv17, align 1)
; CHECK: renamable $r12 = MVE_VADDVs8no_acc killed renamable $q0, 0, $noreg
- ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr)
- ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
- ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.exit:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry:
@@ -1118,25 +1132,14 @@
; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1
- ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: dead $lr = t2DLS renamable $r2
- ; CHECK: $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
- ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
- ; CHECK: MVE_VPST 8, implicit $vpr
- ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
+ ; CHECK: liveins: $lr, $r0, $r2
+ ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg :: (load 8 from %ir.lsr.iv17, align 2)
; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg
- ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.exit:
; CHECK: liveins: $r2
; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
@@ -2664,32 +2667,21 @@
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
- ; CHECK: tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: $r3 = tMOVr $r2, 14 /* CC::al */, $noreg
- ; CHECK: t2IT 10, 8, implicit-def $itstate
- ; CHECK: renamable $r3 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate
; CHECK: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr
; CHECK: bb.1.while.body.preheader:
; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: renamable $r3, dead $cpsr = tSUBrr renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r12 = t2ADDri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $lr = t2DLS killed renamable $lr
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2.while.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r12
- ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
- ; CHECK: MVE_VPST 4, implicit $vpr
- ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.tmp3, align 2)
- ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.tmp1, align 2)
+ ; CHECK: liveins: $lr, $r0, $r1, $r12
+ ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 0, $noreg :: (load 8 from %ir.tmp3, align 2)
+ ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 8, 0, killed $noreg :: (load 8 from %ir.tmp1, align 2)
; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
- ; CHECK: renamable $r2, dead $cpsr = nsw tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = MVE_VADDVu32acc killed renamable $r12, killed renamable $q0, 0, $noreg
- ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.while.end:
; CHECK: liveins: $r12
; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
@@ -2790,33 +2782,22 @@
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
- ; CHECK: tCMPi8 renamable $r2, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: $r3 = tMOVr $r2, 14 /* CC::al */, $noreg
- ; CHECK: t2IT 10, 8, implicit-def $itstate
- ; CHECK: renamable $r3 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate
; CHECK: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr
; CHECK: bb.1.while.body.preheader:
; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: liveins: $r0, $r1, $r2, $r3
- ; CHECK: renamable $r3, dead $cpsr = tSUBrr renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg
- ; CHECK: renamable $r12 = t2ADDri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
- ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
- ; CHECK: $lr = t2DLS killed renamable $lr
+ ; CHECK: $lr = MVE_DLSTP_16 killed renamable $r2
; CHECK: bb.2.while.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
- ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
- ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg
- ; CHECK: MVE_VPST 4, implicit $vpr
- ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.tmp3, align 2)
- ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.tmp1, align 2)
+ ; CHECK: liveins: $lr, $r0, $r1, $r3
+ ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.tmp3, align 2)
+ ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg :: (load 16 from %ir.tmp1, align 2)
; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
- ; CHECK: renamable $r2, dead $cpsr = nsw tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg
; CHECK: renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r12, 0, 14 /* CC::al */, $noreg
- ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.while.end:
; CHECK: liveins: $r3
; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg
@@ -3009,3 +2990,150 @@
tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
...
+---
+name: illegal_scalar_reg_use
+alignment: 2
+tracksRegLiveness: true
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r3', virtual-reg: '' }
+frameInfo:
+ stackSize: 16
+ offsetAdjustment: 0
+ maxAlignment: 4
+fixedStack:
+ - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+constants: []
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: illegal_scalar_reg_use
+ ; CHECK: bb.0.entry:
+ ; CHECK: successors: %bb.1(0x50000000), %bb.3(0x30000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r3, $r4, $r6, $r7
+ ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16
+ ; CHECK: tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK: $r2 = tMOVr $r3, 14 /* CC::al */, $noreg
+ ; CHECK: t2IT 10, 8, implicit-def $itstate
+ ; CHECK: renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate
+ ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK: tBcc %bb.3, 11 /* CC::lt */, killed $cpsr
+ ; CHECK: bb.1.while.body.preheader:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: liveins: $r0, $r1, $r2, $r3
+ ; CHECK: renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg
+ ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ ; CHECK: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg
+ ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: renamable $r4 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8)
+ ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK: $lr = t2DLS killed renamable $lr
+ ; CHECK: bb.2.while.body:
+ ; CHECK: successors: %bb.2(0x7c000000), %bb.4(0x04000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r12
+ ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
+ ; CHECK: MVE_VPST 4, implicit $vpr
+ ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 8 from %ir.tmp3, align 2)
+ ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 8 from %ir.tmp1, align 2)
+ ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
+ ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg
+ ; CHECK: renamable $q0 = MVE_VSUB_qr_i32 killed renamable $q0, renamable $r4, 0, $noreg, undef renamable $q0
+ ; CHECK: renamable $r6 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
+ ; CHECK: renamable $r12 = t2ADDrr killed renamable $r12, killed renamable $r6, 14 /* CC::al */, $noreg, def $cpsr
+ ; CHECK: renamable $r2 = t2ADCri killed renamable $r2, 0, 14 /* CC::al */, $noreg, $noreg, implicit killed $cpsr, implicit-def dead $cpsr
+ ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
+ ; CHECK: tB %bb.4, 14 /* CC::al */, $noreg
+ ; CHECK: bb.3:
+ ; CHECK: successors: %bb.4(0x80000000)
+ ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ ; CHECK: bb.4.while.end:
+ ; CHECK: liveins: $r2, $r12
+ ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
+ ; CHECK: $r1 = tMOVr killed $r2, 14 /* CC::al */, $noreg
+ ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc, implicit killed $r0, implicit killed $r1
+ bb.0.entry:
+ successors: %bb.1(0x50000000), %bb.3(0x30000000)
+ liveins: $r0, $r1, $r3, $r4, $r6, $r7, $lr
+
+ frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 16
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ frame-setup CFI_INSTRUCTION offset $r6, -12
+ frame-setup CFI_INSTRUCTION offset $r4, -16
+ tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ $r2 = tMOVr $r3, 14 /* CC::al */, $noreg
+ t2IT 10, 8, implicit-def $itstate
+ renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate
+ tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ tBcc %bb.3, 11 /* CC::lt */, killed $cpsr
+
+ bb.1.while.body.preheader:
+ successors: %bb.2(0x80000000)
+ liveins: $r0, $r1, $r2, $r3
+
+ renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg
+ renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg
+ renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg
+ renamable $r4 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8)
+ renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ t2DoLoopStart renamable $lr
+
+ bb.2.while.body:
+ successors: %bb.2(0x7c000000), %bb.4(0x04000000)
+ liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r12
+
+ renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
+ MVE_VPST 4, implicit $vpr
+ renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 8 from %ir.tmp3, align 2)
+ renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 8 from %ir.tmp1, align 2)
+ renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
+ renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg
+ renamable $q0 = MVE_VSUB_qr_i32 killed renamable $q0, renamable $r4, 0, $noreg, undef renamable $q0
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ renamable $r6 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
+ renamable $r12 = t2ADDrr killed renamable $r12, killed renamable $r6, 14 /* CC::al */, $noreg, def $cpsr
+ renamable $r2 = t2ADCri killed renamable $r2, 0, 14 /* CC::al */, $noreg, $noreg, implicit killed $cpsr, implicit-def $cpsr
+ t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
+ tB %bb.4, 14 /* CC::al */, $noreg
+
+ bb.3:
+ successors: %bb.4(0x80000000)
+
+ renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+
+ bb.4.while.end:
+ liveins: $r2, $r12
+
+ $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
+ $r1 = tMOVr killed $r2, 14 /* CC::al */, $noreg
+ frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc, implicit killed $r0, implicit killed $r1
+
+...