diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -291,10 +291,8 @@ uint64_t CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0; if (!hasReservedCallFrame(MF)) { - unsigned Align = getStackAlignment(); - int64_t Amount = I->getOperand(0).getImm(); - Amount = alignTo(Amount, Align); + Amount = alignTo(Amount, getStackAlign()); if (!IsDestroy) Amount = -Amount; @@ -3103,5 +3101,5 @@ MF.getInfo()->getCalleeSavedStackSize(); // This is the amount of stack a funclet needs to allocate. return alignTo(CSSize + MF.getFrameInfo().getMaxCallFrameSize(), - getStackAlignment()); + getStackAlign()); } diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -1013,9 +1013,7 @@ uint64_t CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0; if (!hasReservedCallFrame(MF)) { - unsigned Align = getStackAlignment(); - - Amount = alignTo(Amount, Align); + Amount = alignTo(Amount, getStackAlign()); assert(isUInt<32>(Amount) && "exceeded stack address space size"); const SIMachineFunctionInfo *MFI = MF.getInfo(); unsigned SPReg = MFI->getStackPtrOffsetReg(); diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -601,9 +601,9 @@ // The FP is only available if there is no dynamic realignment. We // don't know for sure yet whether we'll need that, so we guess based // on whether there are any local variables that would trigger it. - unsigned StackAlign = TFI->getStackAlignment(); if (TFI->hasFP(MF) && - !((MFI.getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { + !((MFI.getLocalFrameMaxAlign() > TFI->getStackAlign()) && + canRealignStack(MF))) { if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset)) return false; } diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -1596,7 +1596,7 @@ return; // Don't bother if the default stack alignment is sufficiently high. - if (MF.getSubtarget().getFrameLowering()->getStackAlignment() >= 8) + if (MF.getSubtarget().getFrameLowering()->getStackAlign() >= Align(8)) return; // Aligned spills require stack realignment. @@ -2292,8 +2292,8 @@ // of GPRs, spill one extra callee save GPR so we won't have to pad between // the integer and double callee save areas. LLVM_DEBUG(dbgs() << "NumGPRSpills = " << NumGPRSpills << "\n"); - unsigned TargetAlign = getStackAlignment(); - if (TargetAlign >= 8 && (NumGPRSpills & 1)) { + const Align TargetAlign = getStackAlign(); + if (TargetAlign >= Align(8) && (NumGPRSpills & 1)) { if (CS1Spilled && !UnspilledCS1GPRs.empty()) { for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { unsigned Reg = UnspilledCS1GPRs[i]; @@ -2330,7 +2330,7 @@ if (BigFrameOffsets && !ExtraCSSpill) { // If any non-reserved CS register isn't spilled, just spill one or two // extra. That should take care of it! - unsigned NumExtras = TargetAlign / 4; + unsigned NumExtras = TargetAlign.value() / 4; SmallVector Extras; while (NumExtras && !UnspilledCS1GPRs.empty()) { unsigned Reg = UnspilledCS1GPRs.back(); diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp --- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp +++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp @@ -127,7 +127,7 @@ // We need to keep the stack aligned properly. To do this, we round the // amount of space needed for the outgoing arguments up to the next // alignment boundary. - Amount = alignTo(Amount, getStackAlignment()); + Amount = alignTo(Amount, getStackAlign()); // Replace the pseudo instruction with a new instruction... unsigned Opc = Old.getOpcode(); diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -1711,9 +1711,8 @@ const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R); unsigned Size = TRI->getSpillSize(*RC); int Off = MinOffset - Size; - unsigned Align = std::min(TRI->getSpillAlignment(*RC), getStackAlignment()); - assert(isPowerOf2_32(Align)); - Off &= -Align; + Align Alignment = std::min(TRI->getSpillAlign(*RC), getStackAlign()); + Off &= -Alignment.value(); int FI = MFI.CreateFixedSpillStackObject(Size, Off); MinOffset = std::min(MinOffset, Off); CSI.push_back(CalleeSavedInfo(R, FI)); diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -729,7 +729,7 @@ auto &HFI = *Subtarget.getFrameLowering(); // "Zero" means natural stack alignment. if (A == 0) - A = HFI.getStackAlignment(); + A = HFI.getStackAlign().value(); LLVM_DEBUG({ dbgs () << __func__ << " Align: " << A << " Size: "; diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -3447,10 +3447,7 @@ /// ensure minimum alignment required for target. static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering, unsigned NumBytes) { - unsigned TargetAlign = Lowering->getStackAlignment(); - unsigned AlignMask = TargetAlign - 1; - NumBytes = (NumBytes + AlignMask) & ~AlignMask; - return NumBytes; + return alignTo(NumBytes, Lowering->getStackAlign()); } SDValue PPCTargetLowering::LowerFormalArguments( diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -2544,15 +2544,15 @@ const SparcSubtarget *Subtarget) { SDValue Chain = Op.getOperand(0); // Legalize the chain. SDValue Size = Op.getOperand(1); // Legalize the size. - unsigned Align = cast(Op.getOperand(2))->getZExtValue(); - unsigned StackAlign = Subtarget->getFrameLowering()->getStackAlignment(); + MaybeAlign Alignment(cast(Op.getOperand(2))->getZExtValue()); + Align StackAlign = Subtarget->getFrameLowering()->getStackAlign(); EVT VT = Size->getValueType(0); SDLoc dl(Op); // TODO: implement over-aligned alloca. (Note: also implies // supporting support for overaligned function frames + dynamic // allocations, at all, which currently isn't supported) - if (Align > StackAlign) { + if (Alignment && *Alignment > StackAlign) { const MachineFunction &MF = DAG.getMachineFunction(); report_fatal_error("Function \"" + Twine(MF.getName()) + "\": " "over-aligned dynamic alloca not supported.");