diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32.mir
@@ -0,0 +1,132 @@
+# RUN: llc -march=riscv32 -x mir -run-pass=instruction-select -simplify-mir -verify-machineinstrs < %s \
+# RUN: | FileCheck -check-prefix=RV32I %s
+
+--- |
+
+  define void @add_i32() { entry: ret void }
+  define void @sub_i32() { entry: ret void }
+  define void @and_i32() { entry: ret void }
+  define void @or_i32() { entry: ret void }
+  define void @xor_i32() { entry: ret void }
+
+...
+---
+name:            add_i32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: add_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV32I-NEXT:   [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[ADD]]
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(s32) = COPY $x11
+    %2:gprb(s32) = G_ADD %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            sub_i32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: sub_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV32I-NEXT:   [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[SUB]]
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(s32) = COPY $x11
+    %2:gprb(s32) = G_SUB %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            and_i32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: and_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV32I-NEXT:   [[AND:%[0-9]+]]:gpr = AND [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[AND]]
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(s32) = COPY $x11
+    %2:gprb(s32) = G_AND %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            or_i32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: or_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV32I-NEXT:   [[OR:%[0-9]+]]:gpr = OR [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[OR]]
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(s32) = COPY $x11
+    %2:gprb(s32) = G_OR %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            xor_i32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: xor_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV32I-NEXT:   [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[XOR]]
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(s32) = COPY $x11
+    %2:gprb(s32) = G_XOR %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32_m.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32_m.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32_m.mir
@@ -0,0 +1,132 @@
+# RUN: llc -march=riscv32 -mattr=+m -x mir -run-pass=instruction-select -simplify-mir -verify-machineinstrs < %s \
+# RUN: | FileCheck -check-prefix=RV32I %s
+
+--- |
+
+  define void @mul_i32() { entry: ret void }
+  define void @sdiv_i32() { entry: ret void }
+  define void @srem_i32() { entry: ret void }
+  define void @udiv_i32() { entry: ret void }
+  define void @urem_i32() { entry: ret void }
+
+...
+---
+name:            mul_i32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: mul_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV32I-NEXT:   [[ADD:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[ADD]]
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(s32) = COPY $x11
+    %2:gprb(s32) = G_MUL %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            sdiv_i32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: sdiv_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV32I-NEXT:   [[ADD:%[0-9]+]]:gpr = DIV [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[ADD]]
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(s32) = COPY $x11
+    %2:gprb(s32) = G_SDIV %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            srem_i32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: srem_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV32I-NEXT:   [[ADD:%[0-9]+]]:gpr = REM [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[ADD]]
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(s32) = COPY $x11
+    %2:gprb(s32) = G_SREM %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            udiv_i32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: udiv_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV32I-NEXT:   [[ADD:%[0-9]+]]:gpr = DIVU [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[ADD]]
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(s32) = COPY $x11
+    %2:gprb(s32) = G_UDIV %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            urem_i32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: urem_i32
+    ; RV32I: bb.0.entry:
+    ; RV32I-NEXT:   liveins: $x10, $x11
+    ; RV32I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV32I-NEXT:   [[ADD:%[0-9]+]]:gpr = REMU [[COPY]], [[COPY1]]
+    ; RV32I-NEXT:   $x10 = COPY [[ADD]]
+    ; RV32I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(s32) = COPY $x11
+    %2:gprb(s32) = G_UREM %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64.mir
@@ -0,0 +1,132 @@
+# RUN: llc -march=riscv64 -x mir -run-pass=instruction-select -simplify-mir -verify-machineinstrs < %s \
+# RUN: | FileCheck -check-prefix=RV64I %s
+
+--- |
+
+  define void @add_i64() { entry: ret void }
+  define void @sub_i64() { entry: ret void }
+  define void @and_i64() { entry: ret void }
+  define void @or_i64() { entry: ret void }
+  define void @xor_i64() { entry: ret void }
+
+...
+---
+name:            add_i64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: add_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV64I-NEXT:   [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[ADD]]
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s64) = COPY $x11
+    %2:gprb(s64) = G_ADD %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            sub_i64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: sub_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV64I-NEXT:   [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[SUB]]
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s64) = COPY $x11
+    %2:gprb(s64) = G_SUB %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            and_i64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: and_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV64I-NEXT:   [[AND:%[0-9]+]]:gpr = AND [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[AND]]
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s64) = COPY $x11
+    %2:gprb(s64) = G_AND %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            or_i64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: or_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV64I-NEXT:   [[OR:%[0-9]+]]:gpr = OR [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[OR]]
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s64) = COPY $x11
+    %2:gprb(s64) = G_OR %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            xor_i64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: xor_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV64I-NEXT:   [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[XOR]]
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s64) = COPY $x11
+    %2:gprb(s64) = G_XOR %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64_m.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64_m.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64_m.mir
@@ -0,0 +1,132 @@
+# RUN: llc -march=riscv64 -mattr=+m -x mir -run-pass=instruction-select -simplify-mir -verify-machineinstrs < %s \
+# RUN: | FileCheck -check-prefix=RV64I %s
+
+--- |
+
+  define void @mul_i64() { entry: ret void }
+  define void @sdiv_i64() { entry: ret void }
+  define void @srem_i64() { entry: ret void }
+  define void @udiv_i64() { entry: ret void }
+  define void @urem_i64() { entry: ret void }
+
+...
+---
+name:            mul_i64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: mul_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV64I-NEXT:   [[ADD:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[ADD]]
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s64) = COPY $x11
+    %2:gprb(s64) = G_MUL %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            sdiv_i64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: sdiv_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV64I-NEXT:   [[ADD:%[0-9]+]]:gpr = DIV [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[ADD]]
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s64) = COPY $x11
+    %2:gprb(s64) = G_SDIV %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            srem_i64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: srem_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV64I-NEXT:   [[ADD:%[0-9]+]]:gpr = REM [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[ADD]]
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s64) = COPY $x11
+    %2:gprb(s64) = G_SREM %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            udiv_i64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: udiv_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV64I-NEXT:   [[ADD:%[0-9]+]]:gpr = DIVU [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[ADD]]
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s64) = COPY $x11
+    %2:gprb(s64) = G_UDIV %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            urem_i64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: urem_i64
+    ; RV64I: bb.0.entry:
+    ; RV64I-NEXT:   liveins: $x10, $x11
+    ; RV64I:        [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV64I-NEXT:   [[ADD:%[0-9]+]]:gpr = REMU [[COPY]], [[COPY1]]
+    ; RV64I-NEXT:   $x10 = COPY [[ADD]]
+    ; RV64I-NEXT:   PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s64) = COPY $x11
+    %2:gprb(s64) = G_UREM %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...