diff --git a/llvm/include/llvm/CodeGen/CallingConvLower.h b/llvm/include/llvm/CodeGen/CallingConvLower.h --- a/llvm/include/llvm/CodeGen/CallingConvLower.h +++ b/llvm/include/llvm/CodeGen/CallingConvLower.h @@ -435,7 +435,7 @@ void ensureMaxAlignment(Align Alignment) { if (!AnalyzingMustTailForwardedRegs) - MF.getFrameInfo().ensureMaxAlignment(Alignment.value()); + MF.getFrameInfo().ensureMaxAlignment(Alignment); } /// Version of AllocateStack with extra register to be shadowed. diff --git a/llvm/include/llvm/CodeGen/MachineFrameInfo.h b/llvm/include/llvm/CodeGen/MachineFrameInfo.h --- a/llvm/include/llvm/CodeGen/MachineFrameInfo.h +++ b/llvm/include/llvm/CodeGen/MachineFrameInfo.h @@ -484,7 +484,7 @@ // Only ensure max alignment for the default stack. if (getStackID(ObjectIdx) == 0) - ensureMaxAlignment(Align); + ensureMaxAlignment(assumeAligned(Align)); } /// setObjectAlignment - Change the alignment of the specified stack object. @@ -594,7 +594,8 @@ /// Make sure the function is at least Align bytes aligned. void ensureMaxAlignment(Align Alignment); /// FIXME: Remove this once transition to Align is over. - inline void ensureMaxAlignment(unsigned Align) { + LLVM_ATTRIBUTE_DEPRECATED(inline void ensureMaxAlignment(unsigned Align), + "Use the version that uses Align instead") { ensureMaxAlignment(assumeAligned(Align)); } diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h --- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h @@ -285,6 +285,12 @@ return getRegClassInfo(RC).SpillAlignment / 8; } + /// Return the minimum required alignment in bytes for a spill slot for + /// a register of this class. + Align getSpillAlign(const TargetRegisterClass &RC) const { + return Align(getRegClassInfo(RC).SpillAlignment / 8); + } + /// Return true if the given TargetRegisterClass has the ValueType T. bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I) diff --git a/llvm/include/llvm/IR/Function.h b/llvm/include/llvm/IR/Function.h --- a/llvm/include/llvm/IR/Function.h +++ b/llvm/include/llvm/IR/Function.h @@ -349,6 +349,13 @@ return 0; } + /// Return the stack alignment for the function. + MaybeAlign getFnStackAlign() const { + if (!hasFnAttribute(Attribute::StackAlignment)) + return None; + return AttributeSets.getStackAlignment(AttributeList::FunctionIndex); + } + /// hasGC/getGC/setGC/clearGC - The name of the garbage collection algorithm /// to use during code generation. bool hasGC() const { diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp --- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp @@ -654,7 +654,7 @@ MFI.setStackSize(YamlMFI.StackSize); MFI.setOffsetAdjustment(YamlMFI.OffsetAdjustment); if (YamlMFI.MaxAlignment) - MFI.ensureMaxAlignment(YamlMFI.MaxAlignment); + MFI.ensureMaxAlignment(Align(YamlMFI.MaxAlignment)); MFI.setAdjustsStack(YamlMFI.AdjustsStack); MFI.setHasCalls(YamlMFI.HasCalls); if (YamlMFI.MaxCallFrameSize != ~0u) diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -172,7 +172,7 @@ F.hasFnAttribute(Attribute::StackAlignment)); if (F.hasFnAttribute(Attribute::StackAlignment)) - FrameInfo->ensureMaxAlignment(F.getFnStackAlignment()); + FrameInfo->ensureMaxAlignment(*F.getFnStackAlign()); ConstantPool = new (Allocator) MachineConstantPool(getDataLayout()); Alignment = STI->getTargetLowering()->getMinFunctionAlignment(); diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -432,7 +432,7 @@ DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT); bool NeedsArgAlign = false; - unsigned LargestAlignSeen = 0; + Align LargestAlignSeen; // Walk the register/memloc assignments, inserting copies/loads. for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; @@ -469,8 +469,8 @@ StackPtr.getValueType()); MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr); if (ArgAlign) - LargestAlignSeen = std::max(LargestAlignSeen, - (unsigned)VA.getLocVT().getStoreSizeInBits() >> 3); + LargestAlignSeen = std::max( + LargestAlignSeen, Align(VA.getLocVT().getStoreSizeInBits() / 8)); if (Flags.isByVal()) { // The argument is a struct passed by value. According to LLVM, "Arg" // is a pointer. @@ -493,7 +493,7 @@ if (NeedsArgAlign && Subtarget.hasV60Ops()) { LLVM_DEBUG(dbgs() << "Function needs byte stack align due to call args\n"); - unsigned VecAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); + Align VecAlign(HRI.getSpillAlignment(Hexagon::HvxVRRegClass)); LargestAlignSeen = std::max(LargestAlignSeen, VecAlign); MFI.ensureMaxAlignment(LargestAlignSeen); } diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp --- a/llvm/lib/Target/X86/X86FrameLowering.cpp +++ b/llvm/lib/Target/X86/X86FrameLowering.cpp @@ -2250,16 +2250,16 @@ const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT); unsigned Size = TRI->getSpillSize(*RC); - unsigned Align = TRI->getSpillAlignment(*RC); + Align Alignment = TRI->getSpillAlign(*RC); // ensure alignment assert(SpillSlotOffset < 0 && "SpillSlotOffset should always < 0 on X86"); - SpillSlotOffset = -alignTo(-SpillSlotOffset, Align); + SpillSlotOffset = -alignTo(-SpillSlotOffset, Alignment); // spill into slot SpillSlotOffset -= Size; int SlotIndex = MFI.CreateFixedSpillStackObject(Size, SpillSlotOffset); CSI[i - 1].setFrameIdx(SlotIndex); - MFI.ensureMaxAlignment(Align); + MFI.ensureMaxAlignment(Alignment); // Save the start offset and size of XMM in stack frame for funclets. if (X86::VR128RegClass.contains(Reg)) {