diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -17830,6 +17830,14 @@ return SDValue(); if (VT.getSizeInBits() == 8) { + // If IdxVal is 0, it's cheaper to do a move instead of a pextrb, unless + // we're going to zero extend the register or fold the store. + if (llvm::isNullConstant(Idx) && !MayFoldIntoZeroExtend(Op) && + !MayFoldIntoStore(Op)) + return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, + DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, + DAG.getBitcast(MVT::v4i32, Vec), Idx)); + SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, Vec, Idx); return DAG.getNode(ISD::TRUNCATE, dl, VT, Extract); }