Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -1154,12 +1154,14 @@ def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>; def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; +let AdditionalPredicates = [NotInMicroMips] in { def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>; def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>; def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>; +} def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; /// Shift Instructions Index: test/CodeGen/Mips/micromips-and16.ll =================================================================== --- /dev/null +++ test/CodeGen/Mips/micromips-and16.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: -relocation-model=pic -O3 < %s | FileCheck %s + +define i32 @main() { +entry: + %retval = alloca i32, align 4 + %a = alloca i32, align 4 + %b = alloca i32, align 4 + %c = alloca i32, align 4 + store i32 0, i32* %retval + %0 = load i32* %b, align 4 + %1 = load i32* %c, align 4 + %and = and i32 %0, %1 + store i32 %and, i32* %a, align 4 + ret i32 0 +} + +; CHECK: and16 Index: test/CodeGen/Mips/micromips-or16.ll =================================================================== --- /dev/null +++ test/CodeGen/Mips/micromips-or16.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: -relocation-model=pic -O3 < %s | FileCheck %s + +define i32 @main() { +entry: + %retval = alloca i32, align 4 + %a = alloca i32, align 4 + %b = alloca i32, align 4 + %c = alloca i32, align 4 + store i32 0, i32* %retval + %0 = load i32* %b, align 4 + %1 = load i32* %c, align 4 + %or = or i32 %0, %1 + store i32 %or, i32* %a, align 4 + ret i32 0 +} + +; CHECK: or16 Index: test/CodeGen/Mips/micromips-xor16.ll =================================================================== --- /dev/null +++ test/CodeGen/Mips/micromips-xor16.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: -relocation-model=pic -O3 < %s | FileCheck %s + +define i32 @main() { +entry: + %retval = alloca i32, align 4 + %a = alloca i32, align 4 + %b = alloca i32, align 4 + %c = alloca i32, align 4 + store i32 0, i32* %retval + %0 = load i32* %b, align 4 + %1 = load i32* %c, align 4 + %xor = xor i32 %0, %1 + store i32 %xor, i32* %a, align 4 + ret i32 0 +} + +; CHECK: xor16