Index: llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -58,131 +58,152 @@ static cl::opt EnableR600StructurizeCFG( "r600-ir-structurize", cl::desc("Use StructurizeCFG IR pass"), - cl::init(true)); + cl::init(true), + cl::ZeroOrMore); static cl::opt EnableSROA( "amdgpu-sroa", cl::desc("Run SROA after promote alloca pass"), cl::ReallyHidden, - cl::init(true)); + cl::init(true), + cl::ZeroOrMore); static cl::opt EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), - cl::init(false)); + cl::init(false), + cl::ZeroOrMore); static cl::opt OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden, cl::desc("Run pre-RA exec mask optimizations"), - cl::init(true)); + cl::init(true), + cl::ZeroOrMore); static cl::opt EnableR600IfConvert( "r600-if-convert", cl::desc("Use if conversion pass"), cl::ReallyHidden, - cl::init(true)); + cl::init(true), + cl::ZeroOrMore); // Option to disable vectorizer for tests. static cl::opt EnableLoadStoreVectorizer( "amdgpu-load-store-vectorizer", cl::desc("Enable load store vectorizer"), cl::init(true), - cl::Hidden); + cl::Hidden, + cl::ZeroOrMore); // Option to control global loads scalarization static cl::opt ScalarizeGlobal( "amdgpu-scalarize-global-loads", cl::desc("Enable global load scalarization"), cl::init(true), - cl::Hidden); + cl::Hidden, + cl::ZeroOrMore); // Option to run internalize pass. static cl::opt InternalizeSymbols( "amdgpu-internalize-symbols", cl::desc("Enable elimination of non-kernel functions and unused globals"), cl::init(false), - cl::Hidden); + cl::Hidden, + cl::ZeroOrMore); // Option to inline all early. static cl::opt EarlyInlineAll( "amdgpu-early-inline-all", cl::desc("Inline all functions early"), cl::init(false), - cl::Hidden); + cl::Hidden, + cl::ZeroOrMore); static cl::opt EnableSDWAPeephole( "amdgpu-sdwa-peephole", cl::desc("Enable SDWA peepholer"), - cl::init(true)); + cl::init(true), + cl::ZeroOrMore); static cl::opt EnableDPPCombine( "amdgpu-dpp-combine", cl::desc("Enable DPP combiner"), - cl::init(true)); + cl::init(true), + cl::ZeroOrMore); // Enable address space based alias analysis static cl::opt EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden, cl::desc("Enable AMDGPU Alias Analysis"), - cl::init(true)); + cl::init(true), + cl::ZeroOrMore); // Option to run late CFG structurizer static cl::opt LateCFGStructurize( "amdgpu-late-structurize", cl::desc("Enable late CFG structurization"), cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG), - cl::Hidden); + cl::Hidden, + cl::ZeroOrMore); static cl::opt EnableAMDGPUFunctionCallsOpt( "amdgpu-function-calls", cl::desc("Enable AMDGPU function call support"), cl::location(AMDGPUTargetMachine::EnableFunctionCalls), cl::init(true), - cl::Hidden); + cl::Hidden, + cl::ZeroOrMore); // Enable lib calls simplifications static cl::opt EnableLibCallSimplify( "amdgpu-simplify-libcall", cl::desc("Enable amdgpu library simplifications"), cl::init(true), - cl::Hidden); + cl::Hidden, + cl::ZeroOrMore); static cl::opt EnableLowerKernelArguments( "amdgpu-ir-lower-kernel-arguments", cl::desc("Lower kernel argument loads in IR pass"), cl::init(true), - cl::Hidden); + cl::Hidden, + cl::ZeroOrMore); static cl::opt EnableRegReassign( "amdgpu-reassign-regs", cl::desc("Enable register reassign optimizations on gfx10+"), cl::init(true), - cl::Hidden); + cl::Hidden, + cl::ZeroOrMore); // Enable atomic optimization static cl::opt EnableAtomicOptimizations( "amdgpu-atomic-optimizations", cl::desc("Enable atomic optimizations"), cl::init(false), - cl::Hidden); + cl::Hidden, + cl::ZeroOrMore); // Enable Mode register optimization static cl::opt EnableSIModeRegisterPass( "amdgpu-mode-register", cl::desc("Enable mode register pass"), cl::init(true), - cl::Hidden); + cl::Hidden, + cl::ZeroOrMore); // Option is used in lit tests to prevent deadcoding of patterns inspected. static cl::opt EnableDCEInRA("amdgpu-dce-in-ra", cl::init(true), cl::Hidden, - cl::desc("Enable machine DCE inside regalloc")); + cl::desc("Enable machine DCE inside regalloc"), + cl::ZeroOrMore); static cl::opt EnableScalarIRPasses( "amdgpu-scalar-ir-passes", cl::desc("Enable scalar IR passes"), cl::init(true), - cl::Hidden); + cl::Hidden, + cl::ZeroOrMore); extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() { // Register the target