Index: llvm/lib/Target/ARM/ARMISelLowering.cpp =================================================================== --- llvm/lib/Target/ARM/ARMISelLowering.cpp +++ llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -15370,13 +15370,25 @@ if (!Subtarget->hasMVEIntegerOps()) return false; - auto IsSinker = [](Instruction *I, int Operand) { + auto IsFMSMul = [&](Instruction *I) { + if (!I->hasOneUse()) + return false; + auto *Sub = cast(*I->users().begin()); + return Sub->getOpcode() == Instruction::FSub && Sub->getOperand(1) == I; + }; + + auto IsSinker = [&](Instruction *I, int Operand) { switch (I->getOpcode()) { case Instruction::Add: case Instruction::Mul: + case Instruction::FAdd: case Instruction::ICmp: + case Instruction::FCmp: return true; + case Instruction::FMul: + return !IsFMSMul(I); case Instruction::Sub: + case Instruction::FSub: case Instruction::Shl: case Instruction::LShr: case Instruction::AShr: Index: llvm/test/CodeGen/Thumb2/mve-floatregloops.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-floatregloops.ll +++ llvm/test/CodeGen/Thumb2/mve-floatregloops.ll @@ -7,13 +7,12 @@ ; CHECK-NEXT: cmp r2, #1 ; CHECK-NEXT: it lt ; CHECK-NEXT: bxlt lr -; CHECK-NEXT: vmov r3, s0 -; CHECK-NEXT: vdup.32 q0, r3 ; CHECK-NEXT: .LBB0_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r0], #16 +; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: subs r2, #4 -; CHECK-NEXT: vadd.f32 q1, q1, q0 +; CHECK-NEXT: vadd.f32 q1, q1, r3 ; CHECK-NEXT: vstrb.8 q1, [r1], #16 ; CHECK-NEXT: bne .LBB0_1 ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup @@ -53,13 +52,12 @@ ; CHECK-NEXT: cmp r2, #1 ; CHECK-NEXT: it lt ; CHECK-NEXT: bxlt lr -; CHECK-NEXT: vmov r3, s0 -; CHECK-NEXT: vdup.32 q0, r3 ; CHECK-NEXT: .LBB1_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r0], #16 +; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: subs r2, #4 -; CHECK-NEXT: vadd.f32 q1, q0, q1 +; CHECK-NEXT: vadd.f32 q1, q1, r3 ; CHECK-NEXT: vstrb.8 q1, [r1], #16 ; CHECK-NEXT: bne .LBB1_1 ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup @@ -99,13 +97,12 @@ ; CHECK-NEXT: cmp r2, #1 ; CHECK-NEXT: it lt ; CHECK-NEXT: bxlt lr -; CHECK-NEXT: vmov r3, s0 -; CHECK-NEXT: vdup.32 q0, r3 ; CHECK-NEXT: .LBB2_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r0], #16 +; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: subs r2, #4 -; CHECK-NEXT: vmul.f32 q1, q1, q0 +; CHECK-NEXT: vmul.f32 q1, q1, r3 ; CHECK-NEXT: vstrb.8 q1, [r1], #16 ; CHECK-NEXT: bne .LBB2_1 ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup @@ -145,13 +142,12 @@ ; CHECK-NEXT: cmp r2, #1 ; CHECK-NEXT: it lt ; CHECK-NEXT: bxlt lr -; CHECK-NEXT: vmov r3, s0 -; CHECK-NEXT: vdup.32 q0, r3 ; CHECK-NEXT: .LBB3_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r0], #16 +; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: subs r2, #4 -; CHECK-NEXT: vmul.f32 q1, q0, q1 +; CHECK-NEXT: vmul.f32 q1, q1, r3 ; CHECK-NEXT: vstrb.8 q1, [r1], #16 ; CHECK-NEXT: bne .LBB3_1 ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup @@ -191,13 +187,12 @@ ; CHECK-NEXT: cmp r2, #1 ; CHECK-NEXT: it lt ; CHECK-NEXT: bxlt lr -; CHECK-NEXT: vmov r3, s0 -; CHECK-NEXT: vdup.32 q0, r3 ; CHECK-NEXT: .LBB4_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r0], #16 +; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: subs r2, #4 -; CHECK-NEXT: vsub.f32 q1, q1, q0 +; CHECK-NEXT: vsub.f32 q1, q1, r3 ; CHECK-NEXT: vstrb.8 q1, [r1], #16 ; CHECK-NEXT: bne .LBB4_1 ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup @@ -284,16 +279,14 @@ ; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: it lt ; CHECK-NEXT: bxlt lr -; CHECK-NEXT: vmov r12, s0 -; CHECK-NEXT: vdup.32 q0, r12 ; CHECK-NEXT: .LBB6_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q2, [r1], #16 -; CHECK-NEXT: vmov q3, q0 +; CHECK-NEXT: vmov r12, s0 ; CHECK-NEXT: subs r3, #4 -; CHECK-NEXT: vfma.f32 q3, q2, q1 -; CHECK-NEXT: vstrb.8 q3, [r2], #16 +; CHECK-NEXT: vfmas.f32 q2, q1, r12 +; CHECK-NEXT: vstrb.8 q2, [r2], #16 ; CHECK-NEXT: bne .LBB6_1 ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: bx lr @@ -336,16 +329,14 @@ ; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: it lt ; CHECK-NEXT: bxlt lr -; CHECK-NEXT: vmov r12, s0 -; CHECK-NEXT: vdup.32 q0, r12 ; CHECK-NEXT: .LBB7_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q2, [r1], #16 -; CHECK-NEXT: vmov q3, q0 +; CHECK-NEXT: vmov r12, s0 ; CHECK-NEXT: subs r3, #4 -; CHECK-NEXT: vfma.f32 q3, q2, q1 -; CHECK-NEXT: vstrb.8 q3, [r2], #16 +; CHECK-NEXT: vfmas.f32 q2, q1, r12 +; CHECK-NEXT: vstrb.8 q2, [r2], #16 ; CHECK-NEXT: bne .LBB7_1 ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: bx lr @@ -388,14 +379,13 @@ ; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: it lt ; CHECK-NEXT: bxlt lr -; CHECK-NEXT: vmov r12, s0 -; CHECK-NEXT: vdup.32 q0, r12 ; CHECK-NEXT: .LBB8_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q2, [r1], #16 +; CHECK-NEXT: vmov r12, s0 ; CHECK-NEXT: subs r3, #4 -; CHECK-NEXT: vfma.f32 q2, q1, q0 +; CHECK-NEXT: vfma.f32 q2, q1, r12 ; CHECK-NEXT: vstrb.8 q2, [r2], #16 ; CHECK-NEXT: bne .LBB8_1 ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup @@ -439,15 +429,15 @@ ; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: it lt ; CHECK-NEXT: bxlt lr -; CHECK-NEXT: vmov r12, s0 -; CHECK-NEXT: vdup.32 q0, r12 ; CHECK-NEXT: .LBB9_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vldrw.u32 q1, [r0], #16 -; CHECK-NEXT: vldrw.u32 q2, [r1], #16 +; CHECK-NEXT: vmov r12, s0 +; CHECK-NEXT: vldrw.u32 q2, [r0], #16 +; CHECK-NEXT: vldrw.u32 q3, [r1], #16 +; CHECK-NEXT: vdup.32 q1, r12 ; CHECK-NEXT: subs r3, #4 -; CHECK-NEXT: vfma.f32 q2, q0, q1 -; CHECK-NEXT: vstrb.8 q2, [r2], #16 +; CHECK-NEXT: vfma.f32 q3, q1, q2 +; CHECK-NEXT: vstrb.8 q3, [r2], #16 ; CHECK-NEXT: bne .LBB9_1 ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: bx lr @@ -491,17 +481,16 @@ ; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: it lt ; CHECK-NEXT: bxlt lr -; CHECK-NEXT: vmov r12, s0 -; CHECK-NEXT: vdup.32 q0, r12 -; CHECK-NEXT: vneg.f32 q0, q0 ; CHECK-NEXT: .LBB10_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vldrw.u32 q1, [r0], #16 -; CHECK-NEXT: vldrw.u32 q2, [r1], #16 -; CHECK-NEXT: vmov q3, q0 +; CHECK-NEXT: vmov r12, s0 +; CHECK-NEXT: vldrw.u32 q2, [r0], #16 +; CHECK-NEXT: vdup.32 q1, r12 +; CHECK-NEXT: vldrw.u32 q3, [r1], #16 +; CHECK-NEXT: vneg.f32 q1, q1 ; CHECK-NEXT: subs r3, #4 -; CHECK-NEXT: vfma.f32 q3, q2, q1 -; CHECK-NEXT: vstrb.8 q3, [r2], #16 +; CHECK-NEXT: vfma.f32 q1, q3, q2 +; CHECK-NEXT: vstrb.8 q1, [r2], #16 ; CHECK-NEXT: bne .LBB10_1 ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: bx lr @@ -596,15 +585,14 @@ ; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: it lt ; CHECK-NEXT: bxlt lr -; CHECK-NEXT: vmov r12, s0 -; CHECK-NEXT: vdup.32 q0, r12 ; CHECK-NEXT: .LBB12_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrw.u32 q1, [r1], #16 ; CHECK-NEXT: vldrw.u32 q2, [r0], #16 +; CHECK-NEXT: vmov r12, s0 ; CHECK-NEXT: subs r3, #4 ; CHECK-NEXT: vneg.f32 q1, q1 -; CHECK-NEXT: vfma.f32 q1, q2, q0 +; CHECK-NEXT: vfma.f32 q1, q2, r12 ; CHECK-NEXT: vstrb.8 q1, [r2], #16 ; CHECK-NEXT: bne .LBB12_1 ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup @@ -648,16 +636,16 @@ ; CHECK-NEXT: cmp r3, #1 ; CHECK-NEXT: it lt ; CHECK-NEXT: bxlt lr -; CHECK-NEXT: vmov r12, s0 -; CHECK-NEXT: vdup.32 q0, r12 ; CHECK-NEXT: .LBB13_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vldrw.u32 q1, [r1], #16 -; CHECK-NEXT: vldrw.u32 q2, [r0], #16 +; CHECK-NEXT: vldrw.u32 q2, [r1], #16 +; CHECK-NEXT: vmov r12, s0 +; CHECK-NEXT: vldrw.u32 q3, [r0], #16 +; CHECK-NEXT: vdup.32 q1, r12 +; CHECK-NEXT: vneg.f32 q2, q2 ; CHECK-NEXT: subs r3, #4 -; CHECK-NEXT: vneg.f32 q1, q1 -; CHECK-NEXT: vfma.f32 q1, q0, q2 -; CHECK-NEXT: vstrb.8 q1, [r2], #16 +; CHECK-NEXT: vfma.f32 q2, q1, q3 +; CHECK-NEXT: vstrb.8 q2, [r2], #16 ; CHECK-NEXT: bne .LBB13_1 ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: bx lr @@ -784,83 +772,91 @@ define void @arm_fir_f32_1_4_mve(%struct.arm_fir_instance_f32* nocapture readonly %S, float* nocapture readonly %pSrc, float* %pDst, i32 %blockSize) { ; CHECK-LABEL: arm_fir_f32_1_4_mve: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} -; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr} -; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} -; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} -; CHECK-NEXT: ldrh.w r10, [r0] +; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; CHECK-NEXT: .pad #4 +; CHECK-NEXT: sub sp, #4 +; CHECK-NEXT: .vsave {d8, d9} +; CHECK-NEXT: vpush {d8, d9} +; CHECK-NEXT: .pad #16 +; CHECK-NEXT: sub sp, #16 +; CHECK-NEXT: ldrh r4, [r0] ; CHECK-NEXT: ldr.w r12, [r0, #4] -; CHECK-NEXT: sub.w r7, r10, #1 +; CHECK-NEXT: subs r7, r4, #1 ; CHECK-NEXT: cmp r7, #3 ; CHECK-NEXT: bhi .LBB15_6 ; CHECK-NEXT: @ %bb.1: @ %if.then ; CHECK-NEXT: ldr r6, [r0, #8] -; CHECK-NEXT: add.w r4, r12, r7, lsl #2 +; CHECK-NEXT: add.w r11, r12, r7, lsl #2 ; CHECK-NEXT: lsr.w lr, r3, #2 -; CHECK-NEXT: vldr s0, [r6, #12] +; CHECK-NEXT: vldr s0, [r6] +; CHECK-NEXT: vldr s2, [r6, #4] ; CHECK-NEXT: vldr s4, [r6, #8] -; CHECK-NEXT: vmov r7, s0 -; CHECK-NEXT: vldr s8, [r6, #4] -; CHECK-NEXT: vdup.32 q0, r7 -; CHECK-NEXT: vmov r7, s4 -; CHECK-NEXT: vldr s12, [r6] -; CHECK-NEXT: vdup.32 q1, r7 -; CHECK-NEXT: vmov r7, s8 -; CHECK-NEXT: vdup.32 q2, r7 -; CHECK-NEXT: vmov r7, s12 -; CHECK-NEXT: vdup.32 q3, r7 +; CHECK-NEXT: vldr s6, [r6, #12] ; CHECK-NEXT: wls lr, lr, .LBB15_5 ; CHECK-NEXT: @ %bb.2: @ %while.body.lr.ph -; CHECK-NEXT: bic r9, r3, #3 +; CHECK-NEXT: str r4, [sp, #12] @ 4-byte Spill +; CHECK-NEXT: bic r4, r3, #3 ; CHECK-NEXT: movs r6, #0 -; CHECK-NEXT: add.w r8, r2, r9, lsl #2 +; CHECK-NEXT: str r4, [sp, #4] @ 4-byte Spill +; CHECK-NEXT: add.w r4, r2, r4, lsl #2 +; CHECK-NEXT: str r4, [sp, #8] @ 4-byte Spill ; CHECK-NEXT: .LBB15_3: @ %while.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: adds r5, r1, r6 -; CHECK-NEXT: adds r7, r2, r6 -; CHECK-NEXT: vldrw.u32 q4, [r5] -; CHECK-NEXT: adds r5, r4, r6 -; CHECK-NEXT: vstrw.32 q4, [r5] +; CHECK-NEXT: adds r7, r1, r6 ; CHECK-NEXT: add.w r5, r12, r6 -; CHECK-NEXT: vldrw.u32 q4, [r5] -; CHECK-NEXT: vldrw.u32 q5, [r5, #4] -; CHECK-NEXT: vldrw.u32 q6, [r5, #12] +; CHECK-NEXT: vldrw.u32 q2, [r7] +; CHECK-NEXT: add.w r7, r11, r6 +; CHECK-NEXT: vmov r10, s0 +; CHECK-NEXT: vstrw.32 q2, [r7] +; CHECK-NEXT: vmov r9, s2 +; CHECK-NEXT: vldrw.u32 q2, [r5] +; CHECK-NEXT: vmov r4, s4 +; CHECK-NEXT: adds r7, r2, r6 ; CHECK-NEXT: adds r6, #16 -; CHECK-NEXT: vmul.f32 q4, q4, q3 -; CHECK-NEXT: vfma.f32 q4, q5, q2 -; CHECK-NEXT: vldrw.u32 q5, [r5, #8] -; CHECK-NEXT: vfma.f32 q4, q5, q1 -; CHECK-NEXT: vfma.f32 q4, q6, q0 -; CHECK-NEXT: vstrw.32 q4, [r7] +; CHECK-NEXT: vmul.f32 q2, q2, r10 +; CHECK-NEXT: vldrw.u32 q3, [r5, #4] +; CHECK-NEXT: vmov r8, s6 +; CHECK-NEXT: vfma.f32 q2, q3, r9 +; CHECK-NEXT: vldrw.u32 q3, [r5, #8] +; CHECK-NEXT: vldrw.u32 q4, [r5, #12] +; CHECK-NEXT: vfma.f32 q2, q3, r4 +; CHECK-NEXT: vfma.f32 q2, q4, r8 +; CHECK-NEXT: vstrw.32 q2, [r7] ; CHECK-NEXT: le lr, .LBB15_3 ; CHECK-NEXT: @ %bb.4: @ %while.end.loopexit -; CHECK-NEXT: add r4, r6 -; CHECK-NEXT: add.w r12, r12, r9, lsl #2 -; CHECK-NEXT: add.w r1, r1, r9, lsl #2 -; CHECK-NEXT: mov r2, r8 +; CHECK-NEXT: ldr r2, [sp, #4] @ 4-byte Reload +; CHECK-NEXT: add r11, r6 +; CHECK-NEXT: add.w r12, r12, r2, lsl #2 +; CHECK-NEXT: add.w r1, r1, r2, lsl #2 +; CHECK-NEXT: ldrd r2, r4, [sp, #8] @ 8-byte Folded Reload ; CHECK-NEXT: .LBB15_5: @ %while.end ; CHECK-NEXT: and r7, r3, #3 -; CHECK-NEXT: vldrw.u32 q4, [r1] +; CHECK-NEXT: vldrw.u32 q2, [r1] ; CHECK-NEXT: vctp.32 r7 ; CHECK-NEXT: vpst -; CHECK-NEXT: vstrwt.32 q4, [r4] -; CHECK-NEXT: vldrw.u32 q4, [r12] -; CHECK-NEXT: vmul.f32 q3, q4, q3 -; CHECK-NEXT: vldrw.u32 q4, [r12, #4] -; CHECK-NEXT: vfma.f32 q3, q4, q2 -; CHECK-NEXT: vldrw.u32 q2, [r12, #8] -; CHECK-NEXT: vfma.f32 q3, q2, q1 +; CHECK-NEXT: vstrwt.32 q2, [r11] +; CHECK-NEXT: vmov r6, s2 +; CHECK-NEXT: vmov r5, s0 +; CHECK-NEXT: vldrw.u32 q0, [r12] +; CHECK-NEXT: vmov r1, s6 +; CHECK-NEXT: vmov r7, s4 +; CHECK-NEXT: vmul.f32 q0, q0, r5 +; CHECK-NEXT: vldrw.u32 q1, [r12, #4] +; CHECK-NEXT: vfma.f32 q0, q1, r6 +; CHECK-NEXT: vldrw.u32 q1, [r12, #8] +; CHECK-NEXT: vfma.f32 q0, q1, r7 ; CHECK-NEXT: vldrw.u32 q1, [r12, #12] -; CHECK-NEXT: vfma.f32 q3, q1, q0 +; CHECK-NEXT: vfma.f32 q0, q1, r1 ; CHECK-NEXT: vpst -; CHECK-NEXT: vstrwt.32 q3, [r2] +; CHECK-NEXT: vstrwt.32 q0, [r2] ; CHECK-NEXT: ldr.w r12, [r0, #4] ; CHECK-NEXT: .LBB15_6: @ %if.end ; CHECK-NEXT: add.w r0, r12, r3, lsl #2 -; CHECK-NEXT: lsr.w lr, r10, #2 +; CHECK-NEXT: lsr.w lr, r4, #2 ; CHECK-NEXT: wls lr, lr, .LBB15_10 ; CHECK-NEXT: @ %bb.7: @ %while.body51.preheader -; CHECK-NEXT: bic r2, r10, #3 +; CHECK-NEXT: bic r2, r4, #3 ; CHECK-NEXT: adds r1, r2, r3 ; CHECK-NEXT: mov r3, r12 ; CHECK-NEXT: add.w r1, r12, r1, lsl #2 @@ -873,7 +869,7 @@ ; CHECK-NEXT: add.w r12, r12, r2, lsl #2 ; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: .LBB15_10: @ %while.end55 -; CHECK-NEXT: ands r1, r10, #3 +; CHECK-NEXT: ands r1, r4, #3 ; CHECK-NEXT: beq .LBB15_12 ; CHECK-NEXT: @ %bb.11: @ %if.then59 ; CHECK-NEXT: vldrw.u32 q0, [r0] @@ -881,8 +877,10 @@ ; CHECK-NEXT: vpst ; CHECK-NEXT: vstrwt.32 q0, [r12] ; CHECK-NEXT: .LBB15_12: @ %if.end61 -; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} -; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc} +; CHECK-NEXT: add sp, #16 +; CHECK-NEXT: vpop {d8, d9} +; CHECK-NEXT: add sp, #4 +; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} entry: %pState1 = getelementptr inbounds %struct.arm_fir_instance_f32, %struct.arm_fir_instance_f32* %S, i32 0, i32 1 %0 = load float*, float** %pState1, align 4 Index: llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll +++ llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll @@ -183,25 +183,24 @@ ; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: it eq ; CHECK-NEXT: popeq {r7, pc} -; CHECK-NEXT: vneg.f32 s4, s0 +; CHECK-NEXT: vneg.f32 s2, s0 ; CHECK-NEXT: mvn r2, #3 ; CHECK-NEXT: add.w r1, r2, r1, lsl #2 ; CHECK-NEXT: movs r2, #1 -; CHECK-NEXT: vmov.i32 q2, #0x0 +; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: add.w lr, r2, r1, lsr #2 -; CHECK-NEXT: vmov r1, s0 -; CHECK-NEXT: vdup.32 q0, r1 ; CHECK-NEXT: dls lr, lr -; CHECK-NEXT: vmov r1, s4 -; CHECK-NEXT: vdup.32 q1, r1 ; CHECK-NEXT: .LBB3_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vldrw.u32 q3, [r0] -; CHECK-NEXT: vpt.f32 le, q0, q3 -; CHECK-NEXT: vcmpt.f32 le, q3, q1 +; CHECK-NEXT: vldrw.u32 q2, [r0] +; CHECK-NEXT: vmov r1, s0 +; CHECK-NEXT: vcmp.f32 ge, q2, r1 +; CHECK-NEXT: vmov r1, s2 +; CHECK-NEXT: vpst +; CHECK-NEXT: vcmpt.f32 le, q2, r1 ; CHECK-NEXT: vpnot ; CHECK-NEXT: vpst -; CHECK-NEXT: vstrwt.32 q2, [r0], #16 +; CHECK-NEXT: vstrwt.32 q1, [r0], #16 ; CHECK-NEXT: le lr, .LBB3_1 ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: pop {r7, pc} @@ -248,22 +247,20 @@ ; CHECK-NEXT: mvn r2, #7 ; CHECK-NEXT: add.w r1, r2, r1, lsl #3 ; CHECK-NEXT: movs r2, #1 -; CHECK-NEXT: vmov.i32 q2, #0x0 +; CHECK-NEXT: vneg.f16 s2, s0 ; CHECK-NEXT: add.w lr, r2, r1, lsr #3 -; CHECK-NEXT: vmov r1, s0 -; CHECK-NEXT: vneg.f16 s0, s0 -; CHECK-NEXT: vdup.16 q1, r1 -; CHECK-NEXT: vmov r2, s0 +; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: dls lr, lr -; CHECK-NEXT: vdup.16 q0, r2 ; CHECK-NEXT: .LBB4_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vldrh.u16 q3, [r0] -; CHECK-NEXT: vpt.f16 le, q1, q3 -; CHECK-NEXT: vcmpt.f16 le, q3, q0 +; CHECK-NEXT: vmov r1, s2 +; CHECK-NEXT: vldrh.u16 q2, [r0] +; CHECK-NEXT: vmov r2, s0 +; CHECK-NEXT: vpt.f16 ge, q2, r2 +; CHECK-NEXT: vcmpt.f16 le, q2, r1 ; CHECK-NEXT: vpnot ; CHECK-NEXT: vpst -; CHECK-NEXT: vstrht.16 q2, [r0], #16 +; CHECK-NEXT: vstrht.16 q1, [r0], #16 ; CHECK-NEXT: le lr, .LBB4_1 ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: pop {r7, pc} @@ -486,25 +483,24 @@ ; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: it eq ; CHECK-NEXT: popeq {r7, pc} -; CHECK-NEXT: vneg.f32 s4, s0 +; CHECK-NEXT: vneg.f32 s2, s0 ; CHECK-NEXT: mvn r2, #3 ; CHECK-NEXT: add.w r1, r2, r1, lsl #2 ; CHECK-NEXT: movs r2, #1 -; CHECK-NEXT: vmov.i32 q2, #0x0 +; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: add.w lr, r2, r1, lsr #2 -; CHECK-NEXT: vmov r1, s0 -; CHECK-NEXT: vdup.32 q0, r1 ; CHECK-NEXT: dls lr, lr -; CHECK-NEXT: vmov r1, s4 -; CHECK-NEXT: vdup.32 q1, r1 ; CHECK-NEXT: .LBB8_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vldrw.u32 q3, [r0] -; CHECK-NEXT: vpt.f32 le, q0, q3 -; CHECK-NEXT: vcmpt.f32 le, q3, q1 +; CHECK-NEXT: vldrw.u32 q2, [r0] +; CHECK-NEXT: vmov r1, s0 +; CHECK-NEXT: vcmp.f32 ge, q2, r1 +; CHECK-NEXT: vmov r1, s2 +; CHECK-NEXT: vpst +; CHECK-NEXT: vcmpt.f32 le, q2, r1 ; CHECK-NEXT: vpnot ; CHECK-NEXT: vpst -; CHECK-NEXT: vstrwt.32 q2, [r0], #16 +; CHECK-NEXT: vstrwt.32 q1, [r0], #16 ; CHECK-NEXT: le lr, .LBB8_1 ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: pop {r7, pc} @@ -551,22 +547,20 @@ ; CHECK-NEXT: mvn r2, #7 ; CHECK-NEXT: add.w r1, r2, r1, lsl #3 ; CHECK-NEXT: movs r2, #1 -; CHECK-NEXT: vmov.i32 q2, #0x0 +; CHECK-NEXT: vneg.f16 s2, s0 ; CHECK-NEXT: add.w lr, r2, r1, lsr #3 -; CHECK-NEXT: vmov r1, s0 -; CHECK-NEXT: vneg.f16 s0, s0 -; CHECK-NEXT: vdup.16 q1, r1 -; CHECK-NEXT: vmov r2, s0 +; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: dls lr, lr -; CHECK-NEXT: vdup.16 q0, r2 ; CHECK-NEXT: .LBB9_1: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vldrh.u16 q3, [r0] -; CHECK-NEXT: vpt.f16 le, q1, q3 -; CHECK-NEXT: vcmpt.f16 le, q3, q0 +; CHECK-NEXT: vmov r1, s2 +; CHECK-NEXT: vldrh.u16 q2, [r0] +; CHECK-NEXT: vmov r2, s0 +; CHECK-NEXT: vpt.f16 ge, q2, r2 +; CHECK-NEXT: vcmpt.f16 le, q2, r1 ; CHECK-NEXT: vpnot ; CHECK-NEXT: vpst -; CHECK-NEXT: vstrht.16 q2, [r0], #16 +; CHECK-NEXT: vstrht.16 q1, [r0], #16 ; CHECK-NEXT: le lr, .LBB9_1 ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: pop {r7, pc}