diff --git a/llvm/test/MC/RISCV/attribute-with-option.s b/llvm/test/MC/RISCV/attribute-with-option.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/attribute-with-option.s @@ -0,0 +1,19 @@ +## When user specifies conflicting architecture extension with arch attributes, +## we use the arch attributes instead of command line options. +## +## This test uses option '-mattr=+e' to specify e-extension. However, there is +## an arch attribute in the file to specify rv32i. So, we will use rv32i to +## assemble the file instead of rv32e. + +# RUN: llvm-mc %s -triple=riscv32 -mattr=+e -filetype=obj -o - \ +# RUN: | llvm-readobj -A - | FileCheck %s + +.attribute arch, "rv32i2p0" +## Invalid operand for RV32E. x16 is an invalid register for RV32E. +## Use RV32I to assemble. So, it will not trigger an assembly error. +lui x16, 1 + +## Check the arch attribute is not overrided by command line options. +# CHECK: Tag: 5 +# CHECK-NEXT: TagName: arch +# CHECK-NEXT: Value: rv32i2p0 diff --git a/llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s b/llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s new file mode 100644 --- /dev/null +++ b/llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s @@ -0,0 +1,44 @@ +## Test llvm-readobj & llvm-readelf can decode RISC-V attributes correctly. + +# RUN: llvm-mc -triple riscv32 -filetype obj -o %t.rv32.o %s +# RUN: llvm-mc -triple riscv64 -filetype obj -o %t.rv64.o %s +# RUN: llvm-readobj --arch-specific %t.rv32.o \ +# RUN: | FileCheck %s --check-prefix=CHECK-OBJ +# RUN: llvm-readelf -A %t.rv32.o \ +# RUN: | FileCheck %s --check-prefix=CHECK-OBJ +# RUN: llvm-readobj --arch-specific %t.rv64.o \ +# RUN: | FileCheck %s --check-prefix=CHECK-OBJ +# RUN: llvm-readelf -A %t.rv64.o \ +# RUN: | FileCheck %s --check-prefix=CHECK-OBJ + +.attribute Tag_stack_align, 16 +# CHECK-OBJ: Tag: 4 +# CHECK-OBJ-NEXT: Value: 16 +# CHECK-OBJ-NEXT: TagName: stack_align +# CHECK-OBJ-NEXT: Description: Stack alignment is 16-bytes + +.attribute Tag_arch, "rv32i2p0_m2p0_a2p0_c2p0" +# CHECK-OBJ: Tag: 5 +# CHECK-OBJ-NEXT: TagName: arch +# CHECK-OBJ-NEXT: Value: rv32i2p0_m2p0_a2p0_c2p0 + +.attribute Tag_unaligned_access, 0 +# CHECK-OBJ: Tag: 6 +# CHECK-OBJ-NEXT: Value: 0 +# CHECK-OBJ-NEXT: TagName: unaligned_access +# CHECK-OBJ-NEXT: Description: No unaligned access + +.attribute Tag_priv_spec, 2 +# CHECK-OBJ: Tag: 8 +# CHECK-OBJ-NEXT: TagName: priv_spec +# CHECK-OBJ-NEXT: Value: 2 + +.attribute Tag_priv_spec_minor, 0 +# CHECK-OBJ: Tag: 10 +# CHECK-OBJ-NEXT: TagName: priv_spec_minor +# CHECK-OBJ-NEXT: Value: 0 + +.attribute Tag_priv_spec_revision, 0 +# CHECK-OBJ: Tag: 12 +# CHECK-OBJ-NEXT: TagName: priv_spec_revision +# CHECK-OBJ-NEXT: Value: 0 diff --git a/llvm/test/tools/llvm-readobj/ELF/RISCV/lit.local.cfg b/llvm/test/tools/llvm-readobj/ELF/RISCV/lit.local.cfg new file mode 100644 --- /dev/null +++ b/llvm/test/tools/llvm-readobj/ELF/RISCV/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'RISCV' in config.root.targets: + config.unsupported = True diff --git a/llvm/test/tools/llvm-readobj/ELF/RISCV/section-types.test b/llvm/test/tools/llvm-readobj/ELF/RISCV/section-types.test new file mode 100644 --- /dev/null +++ b/llvm/test/tools/llvm-readobj/ELF/RISCV/section-types.test @@ -0,0 +1,21 @@ +## Show that all RISCV specific section types are properly printed for both +## LLVM and GNU styles. + +# RUN: yaml2obj %s -o %t-riscv.o +# RUN: llvm-readobj --section-headers %t-riscv.o | FileCheck %s --check-prefix=LLVM +# RUN: llvm-readelf --section-headers %t-riscv.o | FileCheck %s --check-prefix=GNU + +# LLVM: Name: .riscv.attributes (1) +# LLVM-NEXT: Type: SHT_RISCV_ATTRIBUTES (0x70000003) + +# GNU: [ 1] .riscv.attributes RISCV_ATTRIBUTES + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_REL + Machine: EM_RISCV +Sections: + - Name: .riscv.attributes + Type: SHT_RISCV_ATTRIBUTES diff --git a/llvm/tools/llvm-readobj/ELFDumper.cpp b/llvm/tools/llvm-readobj/ELFDumper.cpp --- a/llvm/tools/llvm-readobj/ELFDumper.cpp +++ b/llvm/tools/llvm-readobj/ELFDumper.cpp @@ -52,6 +52,8 @@ #include "llvm/Support/LEB128.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/MipsABIFlags.h" +#include "llvm/Support/RISCVAttributeParser.h" +#include "llvm/Support/RISCVAttributes.h" #include "llvm/Support/ScopedPrinter.h" #include "llvm/Support/raw_ostream.h" #include @@ -2639,6 +2641,7 @@ const ELFFile *Obj = ObjF->getELFFile(); switch (Obj->getHeader()->e_machine) { case EM_ARM: + case EM_RISCV: printAttributes(); break; case EM_MIPS: { @@ -2659,23 +2662,25 @@ } } -template void ELFDumper::printAttributes() { - W.startLine() << "Attributes not implemented.\n"; -} - namespace { -template <> void ELFDumper::printAttributes() { - const ELFFile *Obj = ObjF->getELFFile(); - if (Obj->getHeader()->e_machine != EM_ARM) { +template void ELFDumper::printAttributes() { + const ELFFile *Obj = ObjF->getELFFile(); + if (!Obj->isLE()) { + W.startLine() << "Attributes not implemented.\n"; + return; + } + + if (Obj->getHeader()->e_machine != EM_ARM && + Obj->getHeader()->e_machine != EM_RISCV) { W.startLine() << "Attributes not implemented.\n"; return; } DictScope BA(W, "BuildAttributes"); - for (const ELFO::Elf_Shdr &Sec : - unwrapOrError(ObjF->getFileName(), Obj->sections())) { - if (Sec.sh_type != ELF::SHT_ARM_ATTRIBUTES) + for (const auto &Sec : unwrapOrError(ObjF->getFileName(), Obj->sections())) { + if (Sec.sh_type != ELF::SHT_ARM_ATTRIBUTES && + Sec.sh_type != ELF::SHT_RISCV_ATTRIBUTES) continue; ArrayRef Contents = @@ -2685,14 +2690,18 @@ << Twine::utohexstr(Contents[0]) << '\n'; continue; } - W.printHex("FormatVersion", Contents[0]); if (Contents.size() == 1) continue; // TODO: Print error and delete the redundant FormatVersion check above. - if (Error E = ARMAttributeParser(&W).parse(Contents, support::little)) - consumeError(std::move(E)); + if (Obj->getHeader()->e_machine == EM_ARM) { + if (Error E = ARMAttributeParser(&W).parse(Contents, support::little)) + consumeError(std::move(E)); + } else if (Obj->getHeader()->e_machine == EM_RISCV) { + if (Error E = RISCVAttributeParser(&W).parse(Contents, support::little)) + consumeError(std::move(E)); + } } } @@ -3530,6 +3539,11 @@ return "MIPS_ABIFLAGS"; } break; + case EM_RISCV: + switch (Type) { + case SHT_RISCV_ATTRIBUTES: + return "RISCV_ATTRIBUTES"; + } } switch (Type) { case SHT_NULL: