diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -8116,8 +8116,9 @@
                                  SINT, DAG.getConstant(53, dl, MVT::i32));
       Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
                          Cond, DAG.getConstant(1, dl, MVT::i64));
-      Cond = DAG.getSetCC(dl, MVT::i32,
-                          Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT);
+      Cond = DAG.getSetCC(
+          dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), OutVT),
+          Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT);
 
       SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
     }
diff --git a/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll b/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
@@ -0,0 +1,24 @@
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN: -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s
+
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN: -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
+
+; When we convert an `i64` to `f32` on 32-bit PPC target, a `setcc` will be
+; generated. And this testcase verifies that the operand expansion of `setcc`
+; will not crash.
+
+%struct.A = type { float }
+
+@ll = external local_unnamed_addr global i64
+@a = external local_unnamed_addr global %struct.A
+
+define void @foo() local_unnamed_addr {
+entry:
+  %0 = load i64, i64* @ll
+  %conv = sitofp i64 %0 to float
+  store float %conv, float* getelementptr inbounds (%struct.A, %struct.A* @a, i32 0, i32 0)
+  ret void
+}
+
+; CHECK-NOT: Unexpected setcc expansion!