Index: llvm/lib/Target/ARM/ARMInstrInfo.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrInfo.td
+++ llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -2982,6 +2982,16 @@
   : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
                  (outs GPR:$Rt)>;
 
+def LDRSBT
+  : ARMAsmPseudo<"ldrsbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
+                 (outs GPR:$Rt)>;
+def LDRHT
+  : ARMAsmPseudo<"ldrht${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
+                 (outs GPR:$Rt)>;
+def LDRSHT
+  : ARMAsmPseudo<"ldrsht${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
+                 (outs GPR:$Rt)>;
+
 // Pseudo instruction ldr Rt, =immediate
 def LDRConstPool
   : ARMAsmPseudo<"ldr${q} $Rt, $immediate",
Index: llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
===================================================================
--- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -8531,6 +8531,26 @@
     Inst = TmpInst;
     return true;
   }
+  // Alias for 'ldr{sb,h,sh}t Rt, [Rn] {, #imm}' for ommitted immediate.
+  case ARM::LDRSBT:
+  case ARM::LDRHT:
+  case ARM::LDRSHT: {
+    MCInst TmpInst;
+
+    if (Inst.getOpcode() == ARM::LDRSBT)
+      TmpInst.setOpcode(ARM::LDRSBTi);
+    else if (Inst.getOpcode() == ARM::LDRHT)
+      TmpInst.setOpcode(ARM::LDRHTi);
+    else if (Inst.getOpcode() == ARM::LDRSHT)
+      TmpInst.setOpcode(ARM::LDRSHTi);
+    TmpInst.addOperand(Inst.getOperand(0));
+    TmpInst.addOperand(Inst.getOperand(1));
+    TmpInst.addOperand(Inst.getOperand(1));
+    TmpInst.addOperand(MCOperand::createImm(0));
+    TmpInst.addOperand(Inst.getOperand(2));
+    Inst = TmpInst;
+    return true;
+  }
   // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
   case ARM::STRT_POST:
   case ARM::STRBT_POST: {
Index: llvm/test/MC/ARM/arm-memory-instructions.s
===================================================================
--- llvm/test/MC/ARM/arm-memory-instructions.s
+++ llvm/test/MC/ARM/arm-memory-instructions.s
@@ -194,11 +194,13 @@
 @------------------------------------------------------------------------------
         ldrht r9, [r7], #128
         ldrht r4, [r3], #-75
+        ldrht r4, [r3]
         ldrht r9, [r7], r2
         ldrht r4, [r3], -r2
 
 @ CHECK: ldrht	r9, [r7], #128          @ encoding: [0xb0,0x98,0xf7,0xe0]
 @ CHECK: ldrht	r4, [r3], #-75          @ encoding: [0xbb,0x44,0x73,0xe0]
+@ CHECK: ldrht	r4, [r3], #-0           @ encoding: [0xb0,0x40,0x73,0xe0]
 @ CHECK: ldrht	r9, [r7], r2            @ encoding: [0xb2,0x90,0xb7,0xe0]
 @ CHECK: ldrht	r4, [r3], -r2           @ encoding: [0xb2,0x40,0x33,0xe0]
 
@@ -244,11 +246,13 @@
 @------------------------------------------------------------------------------
         ldrsbt r5, [r6], #1
         ldrsbt r3, [r8], #-12
+        ldrsbt r5, [r6]
         ldrsbt r8, [r9], r5
         ldrsbt r2, [r1], -r4
 
 @ CHECK: ldrsbt	r5, [r6], #1            @ encoding: [0xd1,0x50,0xf6,0xe0]
 @ CHECK: ldrsbt	r3, [r8], #-12          @ encoding: [0xdc,0x30,0x78,0xe0]
+@ CHECK: ldrsbt	r5, [r6], #-0           @ encoding: [0xd0,0x50,0x76,0xe0]
 @ CHECK: ldrsbt	r8, [r9], r5            @ encoding: [0xd5,0x80,0xb9,0xe0]
 @ CHECK: ldrsbt	r2, [r1], -r4           @ encoding: [0xd4,0x20,0x31,0xe0]
 
@@ -293,11 +297,13 @@
 @------------------------------------------------------------------------------
         ldrsht r5, [r6], #1
         ldrsht r3, [r8], #-12
+        ldrsht r5, [r6]
         ldrsht r8, [r9], r5
         ldrsht r2, [r1], -r4
 
 @ CHECK: ldrsht	r5, [r6], #1            @ encoding: [0xf1,0x50,0xf6,0xe0]
 @ CHECK: ldrsht	r3, [r8], #-12          @ encoding: [0xfc,0x30,0x78,0xe0]
+@ CHECK: ldrsht	r5, [r6], #-0           @ encoding: [0xf0,0x50,0x76,0xe0]
 @ CHECK: ldrsht	r8, [r9], r5            @ encoding: [0xf5,0x80,0xb9,0xe0]
 @ CHECK: ldrsht	r2, [r1], -r4           @ encoding: [0xf4,0x20,0x31,0xe0]