Index: llvm/lib/Target/SystemZ/SystemZISelLowering.h
===================================================================
--- llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -441,11 +441,7 @@
   bool isTruncateFree(EVT, EVT) const override;
 
   bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
-                            bool MathUsed) const override {
-    // Using overflow ops for overflow checks only should beneficial on
-    // SystemZ.
-    return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
-  }
+                            bool MathUsed) const override;
 
   const char *getTargetNodeName(unsigned Opcode) const override;
   std::pair<unsigned, const TargetRegisterClass *>
Index: llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
===================================================================
--- llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -981,6 +981,13 @@
   return FromBits > ToBits;
 }
 
+bool SystemZTargetLowering::shouldFormOverflowOp(unsigned Opcode, EVT VT,
+                                                 bool MathUsed) const {
+  // Form add and sub with overflow intrinsics regardless of any extra users
+  // of the math result.
+  return VT == MVT::i32 || VT == MVT::i64;
+}
+
 //===----------------------------------------------------------------------===//
 // Inline asm support
 //===----------------------------------------------------------------------===//
Index: llvm/test/CodeGen/SystemZ/codegenprepare-form-OF-ops.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/SystemZ/codegenprepare-form-OF-ops.ll
@@ -0,0 +1,54 @@
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -O3 | FileCheck %s
+;
+; Check that CodeGenPrepare transforms these functions to use
+; uadd.with.overflow / usub.with.overflow intrinsics so that the compare
+; instruction is eliminated.
+
+define i32 @uaddo_32(i32 %arg)  {
+; CHECK-LABEL: uaddo_32:
+; CHECK: alhsik	 %r0, %r2, -1
+; CHECK: locrnle %r2, %r0
+; CHECK: br      %r14
+
+bb:
+  %tmp10 = icmp ne i32 %arg, 0
+  %tmp11 = add nsw i32 %arg, -1
+  %tmp12 = select i1 %tmp10, i32 %tmp11, i32 %arg
+  ret i32 %tmp12
+}
+
+define i64 @uaddo_64(i64 %arg)  {
+; CHECK-LABEL: uaddo_64:
+; CHECK: alghsik  %r0, %r2, -1
+; CHECK: locgrnle %r2, %r0
+; CHECK: br       %r14
+bb:
+  %tmp10 = icmp ne i64 %arg, 0
+  %tmp11 = add nsw i64 %arg, -1
+  %tmp12 = select i1 %tmp10, i64 %tmp11, i64 %arg
+  ret i64 %tmp12
+}
+
+define i32 @usubo_32(i32 %arg)  {
+; CHECK-LABEL: usubo_32:
+; CHECK: alhsik %r0, %r2, -1
+; CHECK: locrle %r2, %r0
+; CHECK: br     %r14
+bb:
+  %tmp10 = icmp eq i32 %arg, 0
+  %tmp11 = sub nsw i32 %arg, 1
+  %tmp12 = select i1 %tmp10, i32 %tmp11, i32 %arg
+  ret i32 %tmp12
+}
+
+define i64 @usubo_64(i64 %arg)  {
+; CHECK-LABEL: usubo_64:
+; CHECK: alghsik %r0, %r2, -1
+; CHECK: locgrle %r2, %r0
+; CHECK: br      %r14
+bb:
+  %tmp10 = icmp eq i64 %arg, 0
+  %tmp11 = sub nsw i64 %arg, 1
+  %tmp12 = select i1 %tmp10, i64 %tmp11, i64 %arg
+  ret i64 %tmp12
+}