diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
@@ -21,6 +21,7 @@
   CalleeSaveStackSlotSize = 2;
   CommentString = ";";
   PrivateGlobalPrefix = ".L";
+  PrivateLabelPrefix = ".L";
   UsesELFSectionDirectiveForBSS = true;
   UseIntegratedAssembler = true;
   SupportsDebugInformation = true;
diff --git a/llvm/test/CodeGen/AVR/branch-relaxation-long.ll b/llvm/test/CodeGen/AVR/branch-relaxation-long.ll
--- a/llvm/test/CodeGen/AVR/branch-relaxation-long.ll
+++ b/llvm/test/CodeGen/AVR/branch-relaxation-long.ll
@@ -2,8 +2,8 @@
 
 ; CHECK-LABEL: relax_to_jmp:
 ; CHECK: cpi     r{{[0-9]+}}, 0
-; CHECK: brne    [[BB1:LBB[0-9]+_[0-9]+]]
-; CHECK: jmp     [[BB2:LBB[0-9]+_[0-9]+]]
+; CHECK: brne    [[BB1:.LBB[0-9]+_[0-9]+]]
+; CHECK: jmp     [[BB2:.LBB[0-9]+_[0-9]+]]
 ; CHECK: [[BB1]]:
 ; CHECK: nop
 ; CHECK: [[BB2]]:
@@ -2069,10 +2069,10 @@
 }
 
 ; CHECK-LABEL: relax_to_jmp_backwards:
-; CHECK: [[BB1:LBB[0-9]+_[0-9]+]]
+; CHECK: [[BB1:.LBB[0-9]+_[0-9]+]]
 ; CHECK: nop
 ; CHECK: cpi     r{{[0-9]+}}, 0
-; CHECK: breq    [[BB2:LBB[0-9]+_[0-9]+]]
+; CHECK: breq    [[BB2:.LBB[0-9]+_[0-9]+]]
 ; CHECK: jmp     [[BB1]]
 ; CHECK: [[BB2]]:
 define i8 @relax_to_jmp_backwards(i1 %a) {
diff --git a/llvm/test/CodeGen/AVR/branch-relaxation.ll b/llvm/test/CodeGen/AVR/branch-relaxation.ll
--- a/llvm/test/CodeGen/AVR/branch-relaxation.ll
+++ b/llvm/test/CodeGen/AVR/branch-relaxation.ll
@@ -2,9 +2,9 @@
 
 ; CHECK-LABEL: relax_breq
 ; CHECK: cpi     r{{[0-9]+}}, 0
-; CHECK: brne    LBB0_1
-; CHECK: rjmp    LBB0_2
-; LBB0_1:
+; CHECK: brne    .LBB0_1
+; CHECK: rjmp    .LBB0_2
+; .LBB0_1:
 
 define i8 @relax_breq(i1 %a) {
 entry-block:
@@ -68,10 +68,10 @@
 
 ; CHECK-LABEL: no_relax_breq
 ; CHECK: cpi     r{{[0-9]+}}, 0
-; CHECK: breq    [[END_BB:LBB[0-9]+_[0-9]+]]
+; CHECK: breq    [[END_BB:.LBB[0-9]+_[0-9]+]]
 ; CHECK: nop
 ; ...
-; LBB0_1:
+; .LBB0_1:
 define i8 @no_relax_breq(i1 %a) {
 entry-block:
   br i1 %a, label %hello, label %finished
diff --git a/llvm/test/CodeGen/AVR/ctlz.ll b/llvm/test/CodeGen/AVR/ctlz.ll
--- a/llvm/test/CodeGen/AVR/ctlz.ll
+++ b/llvm/test/CodeGen/AVR/ctlz.ll
@@ -10,8 +10,8 @@
 
 ; CHECK-LABEL: count_leading_zeros:
 ; CHECK: cpi    [[RESULT:r[0-9]+]], 0
-; CHECK: brne   LBB0_1
-; CHECK: rjmp   LBB0_2
+; CHECK: brne   .LBB0_1
+; CHECK: rjmp   .LBB0_2
 ; CHECK: mov    [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
 ; CHECK: lsr    {{.*}}[[SCRATCH]]
 ; CHECK: or     {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
diff --git a/llvm/test/CodeGen/AVR/cttz.ll b/llvm/test/CodeGen/AVR/cttz.ll
--- a/llvm/test/CodeGen/AVR/cttz.ll
+++ b/llvm/test/CodeGen/AVR/cttz.ll
@@ -10,7 +10,7 @@
 
 ; CHECK-LABEL: count_trailing_zeros:
 ; CHECK: cpi    [[RESULT:r[0-9]+]], 0
-; CHECK: breq   [[END_BB:LBB[0-9]+_[0-9]+]]
+; CHECK: breq   [[END_BB:.LBB[0-9]+_[0-9]+]]
 ; CHECK: mov    [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
 ; CHECK: dec    {{.*}}[[SCRATCH]]
 ; CHECK: com    {{.*}}[[RESULT]]
diff --git a/llvm/test/CodeGen/AVR/integration/blink.ll b/llvm/test/CodeGen/AVR/integration/blink.ll
--- a/llvm/test/CodeGen/AVR/integration/blink.ll
+++ b/llvm/test/CodeGen/AVR/integration/blink.ll
@@ -89,7 +89,7 @@
 
   br label %while.body
 
-; CHECK-LABEL: LBB3_1
+; CHECK-LABEL: .LBB3_1
 while.body:
 
   ; CHECK: call turn_on
@@ -98,6 +98,6 @@
   ; CHECK-NEXT: call turn_off
   call void @turn_off()
 
-  ; CHECK-NEXT: rjmp LBB3_1
+  ; CHECK-NEXT: rjmp .LBB3_1
   br label %while.body
 }
diff --git a/llvm/test/CodeGen/AVR/rot.ll b/llvm/test/CodeGen/AVR/rot.ll
--- a/llvm/test/CodeGen/AVR/rot.ll
+++ b/llvm/test/CodeGen/AVR/rot.ll
@@ -7,15 +7,15 @@
   ; CHECK:      andi r22, 7
 
   ; CHECK-NEXT: cpi r22, 0
-  ; CHECK-NEXT: breq LBB0_2
+  ; CHECK-NEXT: breq .LBB0_2
 
-; CHECK-NEXT: LBB0_1:
+; CHECK-NEXT: .LBB0_1:
   ; CHECK-NEXT: lsl r24
   ; CHECK-NEXT: adc r24, r1
   ; CHECK-NEXT: subi r22, 1
-  ; CHECK-NEXT: brne LBB0_1
+  ; CHECK-NEXT: brne .LBB0_1
 
-; CHECK-NEXT:LBB0_2:
+; CHECK-NEXT: .LBB0_2:
   ; CHECK-NEXT: ret
   %mod = urem i8 %amt, 8
 
@@ -34,17 +34,17 @@
   ; CHECK:      andi r22, 7
 
   ; CHECK-NEXT: cpi r22, 0
-  ; CHECK-NEXT: breq LBB1_2
+  ; CHECK-NEXT: breq .LBB1_2
 
-; CHECK-NEXT: LBB1_1:
+; CHECK-NEXT: .LBB1_1:
   ; CHECK-NEXT: lsr r24
   ; CHECK-NEXT: ldi r0, 0
   ; CHECK-NEXT: ror r0
   ; CHECK-NEXT: or r24, r0
   ; CHECK-NEXT: subi r22, 1
-  ; CHECK-NEXT: brne LBB1_1
+  ; CHECK-NEXT: brne .LBB1_1
 
-; CHECK-NEXT:LBB1_2:
+; CHECK-NEXT: .LBB1_2:
   ; CHECK-NEXT: ret
   %mod = urem i8 %amt, 8
 
diff --git a/llvm/test/CodeGen/AVR/smul-with-overflow.ll b/llvm/test/CodeGen/AVR/smul-with-overflow.ll
--- a/llvm/test/CodeGen/AVR/smul-with-overflow.ll
+++ b/llvm/test/CodeGen/AVR/smul-with-overflow.ll
@@ -22,7 +22,7 @@
 ; CHECK: asr    {{.*}}[[LOW]]
 ; CHECK: ldi    [[RET:r[0-9]+]], 1
 ; CHECK: cp     {{.*}}[[HIGH]], {{.*}}[[LOW]]
-; CHECK: brne   [[LABEL:LBB[_0-9]+]]
+; CHECK: brne   [[LABEL:.LBB[_0-9]+]]
 ; CHECK: ldi    {{.*}}[[RET]], 0
 ; CHECK: {{.*}}[[LABEL]]
 ; CHECK: ret
diff --git a/llvm/test/CodeGen/AVR/umul-with-overflow.ll b/llvm/test/CodeGen/AVR/umul-with-overflow.ll
--- a/llvm/test/CodeGen/AVR/umul-with-overflow.ll
+++ b/llvm/test/CodeGen/AVR/umul-with-overflow.ll
@@ -13,7 +13,7 @@
 ; CHECK: mov    [[HIGH:r[0-9]+]], r1
 ; CHECK: ldi    [[RET:r[0-9]+]], 1
 ; CHECK: cpi    {{.*}}[[HIGH]], 0
-; CHECK: brne   [[LABEL:LBB[_0-9]+]]
+; CHECK: brne   [[LABEL:.LBB[_0-9]+]]
 ; CHECK: ldi    {{.*}}[[RET]], 0
 ; CHECK: {{.*}}[[LABEL]]
 ; CHECK: ret