diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -262,153 +262,11 @@ return AIXOffsets32; } -/// RemoveVRSaveCode - We have found that this function does not need any code -/// to manipulate the VRSAVE register, even though it uses vector registers. -/// This can happen when the only registers used are known to be live in or out -/// of the function. Remove all of the VRSAVE related code from the function. -/// FIXME: The removal of the code results in a compile failure at -O0 when the -/// function contains a function call, as the GPR containing original VRSAVE -/// contents is spilled and reloaded around the call. Without the prolog code, -/// the spill instruction refers to an undefined register. This code needs -/// to account for all uses of that GPR. -static void RemoveVRSaveCode(MachineInstr &MI) { - MachineBasicBlock *Entry = MI.getParent(); - MachineFunction *MF = Entry->getParent(); - - // We know that the MTVRSAVE instruction immediately follows MI. Remove it. - MachineBasicBlock::iterator MBBI = MI; - ++MBBI; - assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); - MBBI->eraseFromParent(); - - bool RemovedAllMTVRSAVEs = true; - // See if we can find and remove the MTVRSAVE instruction from all of the - // epilog blocks. - for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { - // If last instruction is a return instruction, add an epilogue - if (I->isReturnBlock()) { - bool FoundIt = false; - for (MBBI = I->end(); MBBI != I->begin(); ) { - --MBBI; - if (MBBI->getOpcode() == PPC::MTVRSAVE) { - MBBI->eraseFromParent(); // remove it. - FoundIt = true; - break; - } - } - RemovedAllMTVRSAVEs &= FoundIt; - } - } - - // If we found and removed all MTVRSAVE instructions, remove the read of - // VRSAVE as well. - if (RemovedAllMTVRSAVEs) { - MBBI = MI; - assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); - --MBBI; - assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); - MBBI->eraseFromParent(); - } - - // Finally, nuke the UPDATE_VRSAVE. - MI.eraseFromParent(); -} - -// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the -// instruction selector. Based on the vector registers that have been used, -// transform this into the appropriate ORI instruction. -static void HandleVRSaveUpdate(MachineInstr &MI, const TargetInstrInfo &TII) { - MachineFunction *MF = MI.getParent()->getParent(); - const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); - DebugLoc dl = MI.getDebugLoc(); - - const MachineRegisterInfo &MRI = MF->getRegInfo(); - unsigned UsedRegMask = 0; - for (unsigned i = 0; i != 32; ++i) - if (MRI.isPhysRegModified(VRRegNo[i])) - UsedRegMask |= 1 << (31-i); - - // Live in and live out values already must be in the mask, so don't bother - // marking them. - for (std::pair LI : MF->getRegInfo().liveins()) { - unsigned RegNo = TRI->getEncodingValue(LI.first); - if (VRRegNo[RegNo] == LI.first) // If this really is a vector reg. - UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. - } - - // Live out registers appear as use operands on return instructions. - for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end(); - UsedRegMask != 0 && BI != BE; ++BI) { - const MachineBasicBlock &MBB = *BI; - if (!MBB.isReturnBlock()) - continue; - const MachineInstr &Ret = MBB.back(); - for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) { - const MachineOperand &MO = Ret.getOperand(I); - if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg())) - continue; - unsigned RegNo = TRI->getEncodingValue(MO.getReg()); - UsedRegMask &= ~(1 << (31-RegNo)); - } - } - - // If no registers are used, turn this into a copy. - if (UsedRegMask == 0) { - // Remove all VRSAVE code. - RemoveVRSaveCode(MI); - return; - } - - Register SrcReg = MI.getOperand(1).getReg(); - Register DstReg = MI.getOperand(0).getReg(); - - if ((UsedRegMask & 0xFFFF) == UsedRegMask) { - if (DstReg != SrcReg) - BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg) - .addReg(SrcReg) - .addImm(UsedRegMask); - else - BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg) - .addReg(SrcReg, RegState::Kill) - .addImm(UsedRegMask); - } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { - if (DstReg != SrcReg) - BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) - .addReg(SrcReg) - .addImm(UsedRegMask >> 16); - else - BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) - .addReg(SrcReg, RegState::Kill) - .addImm(UsedRegMask >> 16); - } else { - if (DstReg != SrcReg) - BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) - .addReg(SrcReg) - .addImm(UsedRegMask >> 16); - else - BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) - .addReg(SrcReg, RegState::Kill) - .addImm(UsedRegMask >> 16); - - BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg) - .addReg(DstReg, RegState::Kill) - .addImm(UsedRegMask & 0xFFFF); - } - - // Remove the old UPDATE_VRSAVE instruction. - MI.eraseFromParent(); -} - static bool spillsCR(const MachineFunction &MF) { const PPCFunctionInfo *FuncInfo = MF.getInfo(); return FuncInfo->isCRSpilled(); } -static bool spillsVRSAVE(const MachineFunction &MF) { - const PPCFunctionInfo *FuncInfo = MF.getInfo(); - return FuncInfo->isVRSAVESpilled(); -} - static bool hasSpills(const MachineFunction &MF) { const PPCFunctionInfo *FuncInfo = MF.getInfo(); return FuncInfo->hasSpills(); @@ -474,7 +332,7 @@ !FI->mustSaveTOC() && // No need to save TOC. !RegInfo->hasBasePointer(MF); // No special alignment. - // Note: for PPC32 SVR4ABI (Non-DarwinABI), we can still generate stackless + // Note: for PPC32 SVR4ABI, we can still generate stackless // code if all local vars are reg-allocated. bool FitsInRedZone = FrameSize <= Subtarget.getRedZoneSize(); @@ -775,21 +633,6 @@ bool isELFv2ABI = Subtarget.isELFv2ABI(); assert((isSVR4ABI || isAIXABI) && "Unsupported PPC ABI."); - // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, - // process it. - if (!isSVR4ABI) - for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { - if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { - if (isAIXABI) - report_fatal_error("UPDATE_VRSAVE is unexpected on AIX."); - HandleVRSaveUpdate(*MBBI, TII); - break; - } - } - - // Move MBBI back to the beginning of the prologue block. - MBBI = MBB.begin(); - // Work out frame sizes. unsigned FrameSize = determineFrameLayoutAndUpdate(MF); int NegFrameSize = -FrameSize; @@ -2035,7 +1878,6 @@ bool HasGPSaveArea = false; bool HasG8SaveArea = false; bool HasFPSaveArea = false; - bool HasVRSAVESaveArea = false; bool HasVRSaveArea = false; SmallVector GPRegs; @@ -2075,8 +1917,6 @@ } else if (PPC::CRBITRCRegClass.contains(Reg) || PPC::CRRCRegClass.contains(Reg)) { ; // do nothing, as we already know whether CRs are spilled - } else if (PPC::VRSAVERCRegClass.contains(Reg)) { - HasVRSAVESaveArea = true; } else if (PPC::VRRCRegClass.contains(Reg) || PPC::SPERCRegClass.contains(Reg)) { // Altivec and SPE are mutually exclusive, but have the same stack @@ -2199,23 +2039,6 @@ LowerBound -= 4; // The CR save area is always 4 bytes long. } - if (HasVRSAVESaveArea) { - // FIXME SVR4: Is it actually possible to have multiple elements in CSI - // which have the VRSAVE register class? - // Adjust the frame index of the VRSAVE spill slot. - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - - if (PPC::VRSAVERCRegClass.contains(Reg)) { - int FI = CSI[i].getFrameIdx(); - - MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI)); - } - } - - LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. - } - // Both Altivec and SPE have the same alignment and padding requirements // within the stack frame. if (HasVRSaveArea) { @@ -2255,8 +2078,8 @@ // needed alignment padding. unsigned StackSize = determineFrameLayout(MF, true); MachineFrameInfo &MFI = MF.getFrameInfo(); - if (MFI.hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) || - hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) { + if (MFI.hasVarSizedObjects() || spillsCR(MF) || hasNonRISpills(MF) || + (hasSpills(MF) && !isInt<16>(StackSize))) { const TargetRegisterClass &GPRC = PPC::GPRCRegClass; const TargetRegisterClass &G8RC = PPC::G8RCRegClass; const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC; @@ -2270,7 +2093,7 @@ MFI.hasVarSizedObjects() && MFI.getMaxAlign() > getStackAlign(); // These kinds of spills might need two registers. - if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars) + if (spillsCR(MF) || HasAlVars) RS->addScavengingFrameIndex( MFI.CreateStackObject(Size, Alignment, false)); } @@ -2347,9 +2170,6 @@ for (unsigned i = 0, e = CSI.size(); i != e; ++i) { unsigned Reg = CSI[i].getReg(); - // VRSAVE can appear here if, for example, @llvm.eh.unwind.init() is used. - if (Reg == PPC::VRSAVE) - continue; // CR2 through CR4 are the nonvolatile CR fields. bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; @@ -2514,10 +2334,6 @@ for (unsigned i = 0, e = CSI.size(); i != e; ++i) { unsigned Reg = CSI[i].getReg(); - // VRSAVE can appear here if, for example, @llvm.eh.unwind.init() is used. - if (Reg == PPC::VRSAVE) - continue; - if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC) continue; diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -156,9 +156,6 @@ PPCLowering = Subtarget->getTargetLowering(); SelectionDAGISel::runOnMachineFunction(MF); - if (!Subtarget->isSVR4ABI()) - InsertVRSaveCode(MF); - return true; } @@ -341,8 +338,6 @@ return true; } - void InsertVRSaveCode(MachineFunction &MF); - StringRef getPassName() const override { return "PowerPC DAG->DAG Pattern Instruction Selection"; } @@ -376,70 +371,6 @@ } // end anonymous namespace -/// InsertVRSaveCode - Once the entire function has been instruction selected, -/// all virtual registers are created and all machine instructions are built, -/// check to see if we need to save/restore VRSAVE. If so, do it. -void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) { - // Check to see if this function uses vector registers, which means we have to - // save and restore the VRSAVE register and update it with the regs we use. - // - // In this case, there will be virtual registers of vector type created - // by the scheduler. Detect them now. - bool HasVectorVReg = false; - for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) { - unsigned Reg = Register::index2VirtReg(i); - if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) { - HasVectorVReg = true; - break; - } - } - if (!HasVectorVReg) return; // nothing to do. - - // If we have a vector register, we want to emit code into the entry and exit - // blocks to save and restore the VRSAVE register. We do this here (instead - // of marking all vector instructions as clobbering VRSAVE) for two reasons: - // - // 1. This (trivially) reduces the load on the register allocator, by not - // having to represent the live range of the VRSAVE register. - // 2. This (more significantly) allows us to create a temporary virtual - // register to hold the saved VRSAVE value, allowing this temporary to be - // register allocated, instead of forcing it to be spilled to the stack. - - // Create two vregs - one to hold the VRSAVE register that is live-in to the - // function and one for the value after having bits or'd into it. - Register InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); - Register UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); - - const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); - MachineBasicBlock &EntryBB = *Fn.begin(); - DebugLoc dl; - // Emit the following code into the entry block: - // InVRSAVE = MFVRSAVE - // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE - // MTVRSAVE UpdatedVRSAVE - MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point - BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE); - BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE), - UpdatedVRSAVE).addReg(InVRSAVE); - BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); - - // Find all return blocks, outputting a restore in each epilog. - for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { - if (BB->isReturnBlock()) { - IP = BB->end(); --IP; - - // Skip over all terminator instructions, which are part of the return - // sequence. - MachineBasicBlock::iterator I2 = IP; - while (I2 != BB->begin() && (--I2)->isTerminator()) - IP = I2; - - // Emit: MTVRSAVE InVRSave - BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); - } - } -} - /// getGlobalBaseReg - Output the instructions required to put the /// base address to use for accessing globals into a register. /// diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -7644,6 +7644,10 @@ SDValue Arg = OutVals[RealResIdx]; + if (Subtarget.isAIXABI() && + (VA.getLocVT().isVector() || VA.getValVT().isVector())) + report_fatal_error("Returning vector types not yet supported on AIX."); + switch (VA.getLocInfo()) { default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h @@ -122,7 +122,6 @@ SOK_VSXVectorSpill, SOK_VectorFloat8Spill, SOK_VectorFloat4Spill, - SOK_VRSaveSpill, SOK_SpillToVSR, SOK_SPESpill, SOK_LastOpcodeSpill // This must be last on the enum. @@ -133,20 +132,20 @@ { \ PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \ - PPC::RESTORE_VRSAVE, PPC::SPILLTOVSR_LD, PPC::EVLDD \ + PPC::SPILLTOVSR_LD, PPC::EVLDD \ } #define Pwr9LoadOpcodes \ { \ PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \ - PPC::DFLOADf32, PPC::RESTORE_VRSAVE, PPC::SPILLTOVSR_LD \ + PPC::DFLOADf32, PPC::SPILLTOVSR_LD \ } #define Pwr8StoreOpcodes \ { \ PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ - PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, PPC::SPILL_VRSAVE, \ + PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, \ PPC::SPILLTOVSR_ST, PPC::EVSTDD \ } @@ -154,7 +153,7 @@ { \ PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \ - PPC::SPILL_VRSAVE, PPC::SPILLTOVSR_ST \ + PPC::SPILLTOVSR_ST \ } // Initialize arrays for load and store spill opcodes on supported subtargets. diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -1374,8 +1374,6 @@ OpcodeIndex = SOK_VectorFloat8Spill; } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) { OpcodeIndex = SOK_VectorFloat4Spill; - } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) { - OpcodeIndex = SOK_VRSaveSpill; } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) { OpcodeIndex = SOK_SpillToVSR; } else { @@ -1414,9 +1412,6 @@ PPC::CRBITRCRegClass.hasSubClassEq(RC)) FuncInfo->setSpillsCR(); - if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) - FuncInfo->setSpillsVRSAVE(); - if (isXFormMemOp(Opcode)) FuncInfo->setHasNonRISpills(); } @@ -1472,9 +1467,6 @@ PPC::CRBITRCRegClass.hasSubClassEq(RC)) FuncInfo->setSpillsCR(); - if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) - FuncInfo->setSpillsVRSAVE(); - if (isXFormMemOp(Opcode)) FuncInfo->setHasNonRISpills(); } diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -1439,10 +1439,7 @@ "#ADJCALLSTACKUP $amt1 $amt2", [(callseq_end timm:$amt1, timm:$amt2)]>; } - -def UPDATE_VRSAVE : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$rS), - "UPDATE_VRSAVE $rD, $rS", []>; -} +} // hasCtrlDep let Defs = [R1], Uses = [R1] in def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", @@ -2919,18 +2916,6 @@ def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>; def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>; -// SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register, -// so we'll need to scavenge a register for it. -let mayStore = 1 in -def SPILL_VRSAVE : PPCEmitTimePseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F), - "#SPILL_VRSAVE", []>; - -// RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously -// spilled), so we'll need to scavenge a register for it. -let mayLoad = 1 in -def RESTORE_VRSAVE : PPCEmitTimePseudo<(outs VRSAVERC:$vrsave), (ins memri:$F), - "#RESTORE_VRSAVE", []>; - let hasSideEffects = 0 in { // mtocrf's input needs to be prepared by shifting by an amount dependent // on the cr register selected. Thus, post-ra anti-dep breaking must not diff --git a/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h b/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h --- a/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h +++ b/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h @@ -69,9 +69,6 @@ /// disabled. bool DisableNonVolatileCR = false; - /// Indicates whether VRSAVE is spilled in the current function. - bool SpillsVRSAVE = false; - /// LRStoreRequired - The bool indicates whether there is some explicit use of /// the LR/LR8 stack slot that is not obvious from scanning the code. This /// requires that the code generator produce a store of LR to the stack on @@ -175,9 +172,6 @@ void setDisableNonVolatileCR() { DisableNonVolatileCR = true; } bool isNonVolatileCRDisabled() const { return DisableNonVolatileCR; } - void setSpillsVRSAVE() { SpillsVRSAVE = true; } - bool isVRSAVESpilled() const { return SpillsVRSAVE; } - void setLRStoreRequired() { LRStoreRequired = true; } bool isLRStoreRequired() const { return LRStoreRequired; } diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h @@ -119,10 +119,6 @@ unsigned FrameIndex) const; void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const; - void lowerVRSAVESpilling(MachineBasicBlock::iterator II, - unsigned FrameIndex) const; - void lowerVRSAVERestore(MachineBasicBlock::iterator II, - unsigned FrameIndex) const; bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const override; diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -926,59 +926,6 @@ MBB.erase(II); } -void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, - unsigned FrameIndex) const { - // Get the instruction. - MachineInstr &MI = *II; // ; SPILL_VRSAVE , - // Get the instruction's basic block. - MachineBasicBlock &MBB = *MI.getParent(); - MachineFunction &MF = *MBB.getParent(); - const PPCSubtarget &Subtarget = MF.getSubtarget(); - const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); - DebugLoc dl = MI.getDebugLoc(); - - const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; - Register Reg = MF.getRegInfo().createVirtualRegister(GPRC); - Register SrcReg = MI.getOperand(0).getReg(); - - BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) - .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); - - addFrameReference( - BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill), - FrameIndex); - - // Discard the pseudo instruction. - MBB.erase(II); -} - -void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, - unsigned FrameIndex) const { - // Get the instruction. - MachineInstr &MI = *II; // ; = RESTORE_VRSAVE - // Get the instruction's basic block. - MachineBasicBlock &MBB = *MI.getParent(); - MachineFunction &MF = *MBB.getParent(); - const PPCSubtarget &Subtarget = MF.getSubtarget(); - const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); - DebugLoc dl = MI.getDebugLoc(); - - const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; - Register Reg = MF.getRegInfo().createVirtualRegister(GPRC); - Register DestReg = MI.getOperand(0).getReg(); - assert(MI.definesRegister(DestReg) && - "RESTORE_VRSAVE does not define its destination"); - - addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), - Reg), FrameIndex); - - BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) - .addReg(Reg, RegState::Kill); - - // Discard the pseudo instruction. - MBB.erase(II); -} - bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const { // For the nonvolatile condition registers (CR2, CR3, CR4) return true to @@ -1110,12 +1057,6 @@ } else if (OpC == PPC::RESTORE_CRBIT) { lowerCRBitRestore(II, FrameIndex); return; - } else if (OpC == PPC::SPILL_VRSAVE) { - lowerVRSAVESpilling(II, FrameIndex); - return; - } else if (OpC == PPC::RESTORE_VRSAVE) { - lowerVRSAVERestore(II, FrameIndex); - return; } // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). diff --git a/llvm/lib/Target/PowerPC/README_ALTIVEC.txt b/llvm/lib/Target/PowerPC/README_ALTIVEC.txt --- a/llvm/lib/Target/PowerPC/README_ALTIVEC.txt +++ b/llvm/lib/Target/PowerPC/README_ALTIVEC.txt @@ -39,11 +39,6 @@ //===----------------------------------------------------------------------===// -For functions that use altivec AND have calls, we are VRSAVE'ing all call -clobbered regs. - -//===----------------------------------------------------------------------===// - Implement passing vectors by value into calls and receiving them as arguments. //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/PowerPC/aix-vector-return.ll b/llvm/test/CodeGen/PowerPC/aix-vector-return.ll --- a/llvm/test/CodeGen/PowerPC/aix-vector-return.ll +++ b/llvm/test/CodeGen/PowerPC/aix-vector-return.ll @@ -4,7 +4,7 @@ ; RUN: not --crash llc --verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -mattr=+altivec 2>&1 < %s | FileCheck %s -; CHECK: LLVM ERROR: UPDATE_VRSAVE is unexpected on AIX. +; CHECK: LLVM ERROR: Returning vector types not yet supported on AIX. define dso_local <4 x i32> @test() local_unnamed_addr #0 { entry: