Index: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -2983,6 +2983,28 @@
   const MachineFunction &MF = *MI.getParent()->getParent();
   const MachineRegisterInfo &MRI = MF.getRegInfo();
 
+  if (MI.isCopy()) {
+    // The default logic bothers to analyze impossible alternative mappings. We
+    // want the most straightforward mapping, so just directly handle this.
+    const RegisterBank *DstBank = getRegBank(MI.getOperand(0).getReg(), MRI,
+                                             *TRI);
+    const RegisterBank *SrcBank = getRegBank(MI.getOperand(1).getReg(), MRI,
+                                             *TRI);
+    if (!SrcBank) // FIXME: Why would we see this?
+      SrcBank = &AMDGPU::VGPRRegBank;
+    if (!DstBank)
+      DstBank = SrcBank;
+
+    unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
+    if (cannotCopy(*DstBank, *SrcBank, Size))
+      return getInvalidInstructionMapping();
+
+    const ValueMapping &ValMap = getValueMapping(0, Size, *DstBank);
+    return getInstructionMapping(
+        1, /*Cost*/ 1,
+        /*OperandsMapping*/ getOperandsMapping({&ValMap}), 1);
+  }
+
   if (MI.isRegSequence()) {
     // If any input is a VGPR, the result must be a VGPR. The default handling
     // assumes any copy between banks is legal.
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
@@ -0,0 +1,181 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: copy_s32_vgpr_to_vgpr
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: copy_s32_vgpr_to_vgpr
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+    %0:_(s32) = COPY $vgpr0
+    $vgpr0 = COPY %0
+
+...
+
+---
+name: copy_s32_sgpr_to_sgpr
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: copy_s32_sgpr_to_sgpr
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK: $sgpr0 = COPY [[COPY]](s32)
+    %0:_(s32) = COPY $sgpr0
+    $sgpr0 = COPY %0
+
+...
+
+---
+name: copy_s32_sgpr_to_vgpr
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: copy_s32_sgpr_to_vgpr
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+    %0:_(s32) = COPY $sgpr0
+    $vgpr0 = COPY %0
+
+...
+
+---
+name: copy_s32_vgpr_to_agpr
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: copy_s32_vgpr_to_agpr
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK: $agpr0 = COPY [[COPY]](s32)
+    %0:_(s32) = COPY $vgpr0
+    $agpr0 = COPY %0
+
+...
+
+---
+name: copy_s32_sgpr_to_agpr
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: copy_s32_sgpr_to_agpr
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK: $agpr0 = COPY [[COPY]](s32)
+    %0:_(s32) = COPY $sgpr0
+    $agpr0 = COPY %0
+
+...
+
+---
+name: copy_s32_agpr_to_vgpr
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $agpr0
+    ; CHECK-LABEL: name: copy_s32_agpr_to_vgpr
+    ; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
+    ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+    %0:_(s32) = COPY $agpr0
+    $vgpr0 = COPY %0
+
+...
+
+---
+name: copy_s32_agpr_to_agpr
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $agpr0
+    ; CHECK-LABEL: name: copy_s32_agpr_to_agpr
+    ; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
+    ; CHECK: $agpr0 = COPY [[COPY]](s32)
+    %0:_(s32) = COPY $agpr0
+    $agpr0 = COPY %0
+
+...
+
+---
+name: copy_s1_sgpr_to_vcc_preassigned
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: copy_s1_sgpr_to_vcc_preassigned
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
+    ; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; CHECK: S_ENDPGM 0, implicit [[COPY1]](s1)
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s1) = G_TRUNC %0
+    %2:vcc(s1) = COPY %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+name: copy_s1_vgpr_to_vcc_preassigned
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: copy_s1_vgpr_to_vcc_preassigned
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
+    ; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; CHECK: S_ENDPGM 0, implicit [[COPY1]](s1)
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s1) = G_TRUNC %0
+    %2:vcc(s1) = COPY %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+name: copy_s1_sgpr_to_vcc
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: copy_s1_sgpr_to_vcc
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
+    ; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; CHECK: S_ENDPGM 0, implicit [[COPY1]](s1)
+    %0:_(s32) = COPY $sgpr0
+    %1:_(s1) = G_TRUNC %0
+    %2:vcc(s1) = COPY %1
+    S_ENDPGM 0, implicit %2
+...
+
+
+---
+name: copy_s1_vgpr_to_vcc
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: copy_s1_vgpr_to_vcc
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
+    ; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; CHECK: S_ENDPGM 0, implicit [[COPY1]](s1)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s1) = G_TRUNC %0
+    %2:vcc(s1) = COPY %1
+    S_ENDPGM 0, implicit %2
+...