diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp @@ -245,6 +245,9 @@ case MCCFIInstruction::OpRestore: OutStreamer->emitCFIRestore(Inst.getRegister()); break; + case MCCFIInstruction::OpUndefined: + OutStreamer->emitCFIUndefined(Inst.getRegister()); + break; } } diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp --- a/llvm/lib/MC/MCAsmStreamer.cpp +++ b/llvm/lib/MC/MCAsmStreamer.cpp @@ -1682,13 +1682,17 @@ void MCAsmStreamer::emitCFIUndefined(int64_t Register) { MCStreamer::emitCFIUndefined(Register); - OS << "\t.cfi_undefined " << Register; + OS << "\t.cfi_undefined "; + EmitRegisterName(Register); EmitEOL(); } void MCAsmStreamer::emitCFIRegister(int64_t Register1, int64_t Register2) { MCStreamer::emitCFIRegister(Register1, Register2); - OS << "\t.cfi_register " << Register1 << ", " << Register2; + OS << "\t.cfi_register "; + EmitRegisterName(Register1); + OS << ", "; + EmitRegisterName(Register2); EmitEOL(); } @@ -1706,7 +1710,8 @@ void MCAsmStreamer::emitCFIReturnColumn(int64_t Register) { MCStreamer::emitCFIReturnColumn(Register); - OS << "\t.cfi_return_column " << Register; + OS << "\t.cfi_return_column "; + EmitRegisterName(Register); EmitEOL(); } diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h @@ -23,6 +23,7 @@ : MCInstPrinter(MAI, MII, MRI) {} //Autogenerated by tblgen + void printRegName(raw_ostream &OS, unsigned RegNo) const override; void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -26,6 +26,10 @@ using namespace llvm; using namespace llvm::AMDGPU; +void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { + OS << getRegisterName(RegNo); +} + void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS) { diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp @@ -61,7 +61,7 @@ if (TT.getArch() == Triple::r600) InitR600MCRegisterInfo(X, 0); else - InitAMDGPUMCRegisterInfo(X, 0); + InitAMDGPUMCRegisterInfo(X, AMDGPU::PC_REG); return X; } diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -84,8 +84,7 @@ // Declarations that describe the SI registers //===----------------------------------------------------------------------===// class SIReg regIdx = 0> : - Register, - DwarfRegNum<[!cast(HWEncoding)]> { + Register { let Namespace = "AMDGPU"; // This is the not yet the complete register encoding. An additional @@ -103,20 +102,20 @@ def FP_REG : SIReg<"fp", 0>; def SP_REG : SIReg<"sp", 0>; def SCRATCH_WAVE_OFFSET_REG : SIReg<"scratch_wave_offset", 0>; +// Pseudo-register to represent the program-counter DWARF register. +def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16]>; // VCC for 64-bit instructions -def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]>, - DwarfRegAlias { +def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> { let Namespace = "AMDGPU"; let SubRegIndices = [sub0, sub1]; let HWEncoding = 106; } -def EXEC_LO : SIReg<"exec_lo", 126>; +def EXEC_LO : SIReg<"exec_lo", 126>, DwarfRegNum<[1]>; def EXEC_HI : SIReg<"exec_hi", 127>; -def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, - DwarfRegAlias { +def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17]> { let Namespace = "AMDGPU"; let SubRegIndices = [sub0, sub1]; let HWEncoding = 126; @@ -151,8 +150,8 @@ def XNACK_MASK_LO : SIReg<"xnack_mask_lo", 104>; def XNACK_MASK_HI : SIReg<"xnack_mask_hi", 105>; -def XNACK_MASK : RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]>, - DwarfRegAlias { +def XNACK_MASK : + RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]> { let Namespace = "AMDGPU"; let SubRegIndices = [sub0, sub1]; let HWEncoding = 104; @@ -162,8 +161,7 @@ def TBA_LO : SIReg<"tba_lo", 108>; def TBA_HI : SIReg<"tba_hi", 109>; -def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]>, - DwarfRegAlias { +def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]> { let Namespace = "AMDGPU"; let SubRegIndices = [sub0, sub1]; let HWEncoding = 108; @@ -172,8 +170,7 @@ def TMA_LO : SIReg<"tma_lo", 110>; def TMA_HI : SIReg<"tma_hi", 111>; -def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]>, - DwarfRegAlias { +def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]> { let Namespace = "AMDGPU"; let SubRegIndices = [sub0, sub1]; let HWEncoding = 110; @@ -192,8 +189,7 @@ } class FlatReg encoding> : - RegisterWithSubRegs<"flat_scratch", [lo, hi]>, - DwarfRegAlias { + RegisterWithSubRegs<"flat_scratch", [lo, hi]> { let Namespace = "AMDGPU"; let SubRegIndices = [sub0, sub1]; let HWEncoding = encoding; @@ -208,19 +204,25 @@ // SGPR registers foreach Index = 0-105 in { - def SGPR#Index : SIReg <"s"#Index, Index>; + def SGPR#Index : + SIReg <"s"#Index, Index>, + DwarfRegNum<[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>; } // VGPR registers foreach Index = 0-255 in { - def VGPR#Index : SIReg <"v"#Index, Index> { + def VGPR#Index : + SIReg <"v"#Index, Index>, + DwarfRegNum<[!add(Index, 2560)]> { let HWEncoding{8} = 1; } } // AccVGPR registers foreach Index = 0-255 in { - def AGPR#Index : SIReg <"a"#Index, Index> { + def AGPR#Index : + SIReg <"a"#Index, Index>, + DwarfRegNum<[!add(Index, 3072)]> { let HWEncoding{8} = 1; } } diff --git a/llvm/test/CodeGen/SPARC/2013-05-17-CallFrame.ll b/llvm/test/CodeGen/SPARC/2013-05-17-CallFrame.ll --- a/llvm/test/CodeGen/SPARC/2013-05-17-CallFrame.ll +++ b/llvm/test/CodeGen/SPARC/2013-05-17-CallFrame.ll @@ -12,7 +12,7 @@ ; V8-NEXT: save %sp, -96, %sp ; V8-NEXT: .cfi_def_cfa_register %fp ; V8-NEXT: .cfi_window_save -; V8-NEXT: .cfi_register 15, 31 +; V8-NEXT: .cfi_register %o7, %i7 ; V8-NEXT: add %i0, 7, %i0 ; V8-NEXT: and %i0, -8, %i0 ; V8-NEXT: sub %sp, %i0, %i0 @@ -39,7 +39,7 @@ ; SPARC64-NEXT: save %sp, -128, %sp ; SPARC64-NEXT: .cfi_def_cfa_register %fp ; SPARC64-NEXT: .cfi_window_save -; SPARC64-NEXT: .cfi_register 15, 31 +; SPARC64-NEXT: .cfi_register %o7, %i7 ; SPARC64-NEXT: srl %i0, 0, %i0 ; SPARC64-NEXT: add %i0, 15, %i0 ; SPARC64-NEXT: sethi 4194303, %i1 diff --git a/llvm/test/CodeGen/SPARC/exception.ll b/llvm/test/CodeGen/SPARC/exception.ll --- a/llvm/test/CodeGen/SPARC/exception.ll +++ b/llvm/test/CodeGen/SPARC/exception.ll @@ -18,7 +18,7 @@ ; V8ABS: .cfi_lsda 0, ; V8ABS: .cfi_def_cfa_register {{30|%fp}} ; V8ABS: .cfi_window_save -; V8ABS: .cfi_register 15, 31 +; V8ABS: .cfi_register %o7, %i7 ; V8ABS: call __cxa_throw ; V8ABS: call __cxa_throw @@ -37,7 +37,7 @@ ; V8PIC: .cfi_lsda 27, ; V8PIC: .cfi_def_cfa_register {{30|%fp}} ; V8PIC: .cfi_window_save -; V8PIC: .cfi_register 15, 31 +; V8PIC: .cfi_register %o7, %i7 ; V8PIC: .section .gcc_except_table ; V8PIC-NOT: .section ; V8PIC: .word %r_disp32(.L_ZTIi.DW.stub) @@ -52,7 +52,7 @@ ; V9ABS: .cfi_lsda 27, ; V9ABS: .cfi_def_cfa_register {{30|%fp}} ; V9ABS: .cfi_window_save -; V9ABS: .cfi_register 15, 31 +; V9ABS: .cfi_register %o7, %i7 ; V9ABS: .section .gcc_except_table ; V9ABS-NOT: .section ; V9ABS: .xword _ZTIi @@ -63,7 +63,7 @@ ; V9PIC: .cfi_lsda 27, ; V9PIC: .cfi_def_cfa_register {{30|%fp}} ; V9PIC: .cfi_window_save -; V9PIC: .cfi_register 15, 31 +; V9PIC: .cfi_register %o7, %i7 ; V9PIC: .section .gcc_except_table ; V9PIC-NOT: .section ; V9PIC: .word %r_disp32(.L_ZTIi.DW.stub) diff --git a/llvm/test/CodeGen/SPARC/reserved-regs.ll b/llvm/test/CodeGen/SPARC/reserved-regs.ll --- a/llvm/test/CodeGen/SPARC/reserved-regs.ll +++ b/llvm/test/CodeGen/SPARC/reserved-regs.ll @@ -7,6 +7,7 @@ ; CHECK-LABEL: use_all_i32_regs: ; CHECK: save %sp +; CHECK: .cfi_register %o7, %i7 ; CHECK-NOT: %g0 ; CHECK-NOT: %g1 ; CHECK-NOT: %g5 @@ -88,6 +89,7 @@ ; CHECK-LABEL: use_all_i64_regs: ; CHECK: save %sp +; CHECK: .cfi_register %o7, %i7 ; CHECK-NOT: %g0 ; CHECK-NOT: %g1 ; CHECK-NOT: %g4 diff --git a/llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll b/llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll --- a/llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll +++ b/llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll @@ -9,7 +9,7 @@ ; SPARC-NEXT: save %sp, -128, %sp ; SPARC-NEXT: .cfi_def_cfa_register %fp ; SPARC-NEXT: .cfi_window_save -; SPARC-NEXT: .cfi_register 15, 31 +; SPARC-NEXT: .cfi_register %o7, %i7 ; SPARC-NEXT: ld [%fp+92], %l3 ; SPARC-NEXT: ld [%fp+96], %g2 ; SPARC-NEXT: umul %i2, %i5, %g3 @@ -195,7 +195,7 @@ ; SPARC64-NEXT: save %sp, -176, %sp ; SPARC64-NEXT: .cfi_def_cfa_register %fp ; SPARC64-NEXT: .cfi_window_save -; SPARC64-NEXT: .cfi_register 15, 31 +; SPARC64-NEXT: .cfi_register %o7, %i7 ; SPARC64-NEXT: srax %i2, 63, %o0 ; SPARC64-NEXT: srax %i1, 63, %o2 ; SPARC64-NEXT: mov %i2, %o1 diff --git a/llvm/test/DebugInfo/AMDGPU/print-reg-name.s b/llvm/test/DebugInfo/AMDGPU/print-reg-name.s new file mode 100644 --- /dev/null +++ b/llvm/test/DebugInfo/AMDGPU/print-reg-name.s @@ -0,0 +1,10 @@ +; RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=asm %s | FileCheck %s + +; Check that we can print symbolic register operands in CFI instructions. + +.text +f: +.cfi_startproc +; CHECK: .cfi_undefined s0 +.cfi_undefined s0 +.cfi_endproc diff --git a/llvm/test/DebugInfo/AMDGPU/register-mapping.s b/llvm/test/DebugInfo/AMDGPU/register-mapping.s new file mode 100644 --- /dev/null +++ b/llvm/test/DebugInfo/AMDGPU/register-mapping.s @@ -0,0 +1,35 @@ +; RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1010 -filetype=obj %s | llvm-dwarfdump -debug-frame - | FileCheck %s + +; Check that we implement the DWARF register mapping. + +.text +f: +.cfi_startproc +; CHECK: CIE +; CHECK: Return address column: 16 + +; CHECK: FDE +; CHECK: DW_CFA_undefined: reg17 +.cfi_undefined exec + +; CHECK: DW_CFA_undefined: reg32 +.cfi_undefined s0 +; CHECK: DW_CFA_undefined: reg95 +.cfi_undefined s63 + +; CHECK: DW_CFA_undefined: reg1088 +.cfi_undefined s64 +; CHECK: DW_CFA_undefined: reg1129 +.cfi_undefined s105 + +; CHECK: DW_CFA_undefined: reg2560 +.cfi_undefined v0 +; CHECK: DW_CFA_undefined: reg2815 +.cfi_undefined v255 + +; CHECK: DW_CFA_undefined: reg3072 +.cfi_undefined a0 +; CHECK: DW_CFA_undefined: reg3327 +.cfi_undefined a255 + +.cfi_endproc diff --git a/llvm/test/DebugInfo/AMDGPU/variable-locations.ll b/llvm/test/DebugInfo/AMDGPU/variable-locations.ll --- a/llvm/test/DebugInfo/AMDGPU/variable-locations.ll +++ b/llvm/test/DebugInfo/AMDGPU/variable-locations.ll @@ -32,7 +32,7 @@ @GlobB = common addrspace(1) global i32 0, align 4, !dbg !6 ; CHECK: {{.*}}DW_TAG_subprogram -; CHECK: DW_AT_frame_base [DW_FORM_block1] (DW_OP_reg9 SGPR9) +; CHECK: DW_AT_frame_base [DW_FORM_block1] (DW_OP_reg{{.*}} SGPR9) define amdgpu_kernel void @kernel1( ; CHECK: {{.*}}DW_TAG_formal_parameter diff --git a/llvm/test/MC/X86/return-column.s b/llvm/test/MC/X86/return-column.s --- a/llvm/test/MC/X86/return-column.s +++ b/llvm/test/MC/X86/return-column.s @@ -30,7 +30,7 @@ // CHECK-ASM-ROUNDTRIP-LABEL: f: // CHECK-ASM-ROUNDTRIP: .cfi_startproc -// CHECK-ASM-ROUNDTRIP-NEXT: .cfi_return_column 0 +// CHECK-ASM-ROUNDTRIP-NEXT: .cfi_return_column %eax // CHECK-ASM-ROUNDTRIP: .cfi_endproc // CHECK-EH_FRAME: 00000000 00000014 00000000 CIE