diff --git a/llvm/test/tools/llvm-objdump/X86/demangle.s b/llvm/test/tools/llvm-objdump/X86/demangle.s --- a/llvm/test/tools/llvm-objdump/X86/demangle.s +++ b/llvm/test/tools/llvm-objdump/X86/demangle.s @@ -11,7 +11,7 @@ ## Check the case when relocations are inlined into disassembly. # RUN: llvm-objdump -d -r --demangle %t | FileCheck %s --check-prefix=INLINE # INLINE: foo(): -# INLINE-NEXT: 0: {{.*}} callq 0 <_Z3foov+0x5> +# INLINE-NEXT: 0: {{.*}} callq 0 <_Z3foov> # INLINE-NEXT: 0000000000000001: R_X86_64_PLT32 foo()-0x4 .text diff --git a/llvm/test/tools/llvm-objdump/X86/elf-disassemble-relocs.test b/llvm/test/tools/llvm-objdump/X86/elf-disassemble-relocs.test --- a/llvm/test/tools/llvm-objdump/X86/elf-disassemble-relocs.test +++ b/llvm/test/tools/llvm-objdump/X86/elf-disassemble-relocs.test @@ -4,11 +4,11 @@ # RUN: yaml2obj %s --docnum=1 -o %t1.o # RUN: llvm-objdump %t1.o -d -r | FileCheck %s --implicit-check-not="RELOCATION RECORDS" -# CHECK: 0: e8 00 00 00 00 callq 0 <.text+0x5> +# CHECK: 0: e8 00 00 00 00 callq 0 # CHECK-NEXT: 0000000000000001: R_X86_64_PC32 foo-0x4 # CHECK-NEXT: 0000000000000002: R_X86_64_NONE bar+0x8 -# CHECK-NEXT: 5: e8 00 00 00 00 callq 0 <.text+0xa> -# CHECK-NEXT: 0000000000000006: R_X86_64_PLT32 foo+0x1 +# CHECK-NEXT: 5: e8 00 00 00 00 callq 0 +# CHECK-NEXT: 0000000000000006: R_X86_64_PLT32 whiz+0x1 --- !ELF FileHeader: @@ -34,12 +34,13 @@ Type: R_X86_64_NONE Addend: 8 - Offset: 6 - Symbol: foo + Symbol: whiz Type: R_X86_64_PLT32 Addend: 1 Symbols: - Name: foo - Name: bar + - Name: whiz ## Check we report an error if the relocated section identified by the ## sh_info field of a relocation section is invalid. diff --git a/llvm/test/tools/llvm-objdump/X86/elf-disassemble-symbol-references.yaml b/llvm/test/tools/llvm-objdump/X86/elf-disassemble-symbol-references.yaml --- a/llvm/test/tools/llvm-objdump/X86/elf-disassemble-symbol-references.yaml +++ b/llvm/test/tools/llvm-objdump/X86/elf-disassemble-symbol-references.yaml @@ -48,7 +48,7 @@ # REL: Disassembly of section .text1: # REL-EMPTY: # REL-NEXT: 0000000000000000 .text1: -# REL-NEXT: 0: e8 00 00 00 00 callq 0 <.text1+0x5> +# REL-NEXT: 0: e8 00 00 00 00 callq 0 # REL-EMPTY: # REL-NEXT: Disassembly of section .text2: # REL-EMPTY: diff --git a/llvm/test/tools/llvm-objdump/X86/section-filter-relocs.test b/llvm/test/tools/llvm-objdump/X86/section-filter-relocs.test --- a/llvm/test/tools/llvm-objdump/X86/section-filter-relocs.test +++ b/llvm/test/tools/llvm-objdump/X86/section-filter-relocs.test @@ -10,7 +10,7 @@ # DISASM: Disassembly of section .text: # DISASM-EMPTY: # DISASM-NEXT: 0000000000000400 .text: -# DISASM-NEXT: 400: e8 00 00 00 00 callq 0 <.text+0x5> +# DISASM-NEXT: 400: e8 00 00 00 00 callq 0 # RELOC-NEXT: 00000401: R_X86_64_PC32 foo+0x1 # RELOC-NEXT: 00000401: R_X86_64_GOT32 foo # DISASM: Disassembly of section .rodata: diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp --- a/llvm/tools/llvm-objdump/llvm-objdump.cpp +++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp @@ -669,6 +669,13 @@ return isArmElf(Obj) || isAArch64Elf(Obj); } +static void printBranchTarget(StringRef TargetName, uint64_t Displacement) { + outs() << " <" << TargetName; + if (Displacement) + outs() << "+0x" << Twine::utohexstr(Displacement); + outs() << '>'; +} + static void printRelocation(StringRef FileName, const RelocationRef &Rel, uint64_t Address, bool Is64Bits) { StringRef Fmt = Is64Bits ? "\t\t%016" PRIx64 ": " : "\t\t\t%08" PRIx64 ": "; @@ -1124,8 +1131,7 @@ PrimaryIsThumb = STI->checkFeatures("+thumb-mode"); std::map> RelocMap; - if (InlineRelocs) - RelocMap = getRelocsMap(*Obj); + RelocMap = getRelocsMap(*Obj); bool Is64Bits = Obj->getBytesInAddress() > 4; // Create a mapping from virtual address to symbol name. This is used to @@ -1394,7 +1400,7 @@ uint64_t MaxOffset = End - Index; // For -reloc: print zero blocks patched by relocations, so that // relocations can be shown in the dump. - if (RelCur != RelEnd) + if (InlineRelocs && RelCur != RelEnd) MaxOffset = RelCur->getOffset() - Index; if (size_t N = @@ -1438,12 +1444,25 @@ continue; } + // Find the next relocation + while (RelCur != RelEnd && + (getHidden(*RelCur) || + SectionAddr + RelCur->getOffset() < StartAddress)) { + ++RelCur; + } + // Try to resolve the target of a call, tail call, etc. to a specific // symbol. if (MIA && (MIA->isCall(Inst) || MIA->isUnconditionalBranch(Inst) || MIA->isConditionalBranch(Inst))) { uint64_t Target; - if (MIA->evaluateBranch(Inst, SectionAddr + Index, Size, Target)) { + if (RelCur != RelEnd) { + auto const Sym = RelCur->getSymbol(); + auto Name = Sym->getName(); + if (Name) + printBranchTarget(*Name, 0 /* would expect this to be symbol addend? */); + } + else if (MIA->evaluateBranch(Inst, SectionAddr + Index, Size, Target)) { // In a relocatable object, the target's section must reside in // the same section as the call instruction or it is accessed // through a relocation. @@ -1465,7 +1484,6 @@ TargetSectionSymbols = &AbsoluteSymbols; } } - // Find the last symbol in the section whose offset is less than // or equal to the target. If there isn't a section that contains // the target, find the nearest preceding absolute symbol. @@ -1486,18 +1504,14 @@ --TargetSym; uint64_t TargetAddress = TargetSym->Addr; StringRef TargetName = TargetSym->Name; - outs() << " <" << TargetName; - uint64_t Disp = Target - TargetAddress; - if (Disp) - outs() << "+0x" << Twine::utohexstr(Disp); - outs() << '>'; + printBranchTarget (TargetName, Target - TargetAddress); } } } outs() << "\n"; // Hexagon does this in pretty printer - if (Obj->getArch() != Triple::hexagon) { + if (InlineRelocs && Obj->getArch() != Triple::hexagon) { // Print relocation for instruction. while (RelCur != RelEnd) { uint64_t Offset = RelCur->getOffset();