Index: llvm/lib/Target/AMDGPU/AMDGPU.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPU.h +++ llvm/lib/Target/AMDGPU/AMDGPU.h @@ -30,6 +30,8 @@ // GlobalISel passes void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &); FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone); +void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &); +FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone); // R600 Passes FunctionPass *createR600VectorRegMerger(); Index: llvm/lib/Target/AMDGPU/AMDGPUCombine.td =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUCombine.td +++ llvm/lib/Target/AMDGPU/AMDGPUCombine.td @@ -26,7 +26,12 @@ def AMDGPUPreLegalizerCombinerHelper: GICombinerHelper< "AMDGPUGenPreLegalizerCombinerHelper", [all_combines, - elide_br_by_inverting_cond, - gfx6gfx7_combines]> { + elide_br_by_inverting_cond]> { let DisableRuleOption = "amdgpuprelegalizercombiner-disable-rule"; } + +def AMDGPUPostLegalizerCombinerHelper: GICombinerHelper< + "AMDGPUGenPostLegalizerCombinerHelper", [all_combines, + gfx6gfx7_combines]> { + let DisableRuleOption = "amdgpupostlegalizercombiner-disable-rule"; +} Index: llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp =================================================================== --- /dev/null +++ llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp @@ -0,0 +1,261 @@ +//=== lib/CodeGen/GlobalISel/AMDGPUPostLegalizerCombiner.cpp ---------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This pass does combining of machine instructions at the generic MI level, +// after the legalizer. +// +//===----------------------------------------------------------------------===// + +#include "AMDGPUTargetMachine.h" +#include "AMDGPULegalizerInfo.h" +#include "llvm/CodeGen/GlobalISel/Combiner.h" +#include "llvm/CodeGen/GlobalISel/CombinerHelper.h" +#include "llvm/CodeGen/GlobalISel/CombinerInfo.h" +#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h" +#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" +#include "llvm/CodeGen/MachineDominators.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/Support/Debug.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" + +#define DEBUG_TYPE "amdgpu-postlegalizer-combiner" + +using namespace llvm; +using namespace MIPatternMatch; + +struct FMinFMaxLegacyInfo { + Register LHS; + Register RHS; + Register True; + Register False; + CmpInst::Predicate Pred; +}; + +// TODO: Make sure fmin_legacy/fmax_legacy don't canonicalize +static bool matchFMinFMaxLegacy(MachineInstr &MI, MachineRegisterInfo &MRI, + MachineFunction &MF, FMinFMaxLegacyInfo &Info) { + // FIXME: Combines should have subtarget predicates, and we shouldn't need + // this here. + if (!MF.getSubtarget().hasFminFmaxLegacy()) + return false; + + // FIXME: Type predicate on pattern + if (MRI.getType(MI.getOperand(0).getReg()) != LLT::scalar(32)) + return false; + + Register Cond = MI.getOperand(1).getReg(); + if (!MRI.hasOneNonDBGUse(Cond) || + !mi_match(Cond, MRI, + m_GFCmp(m_Pred(Info.Pred), m_Reg(Info.LHS), m_Reg(Info.RHS)))) + return false; + + Info.True = MI.getOperand(2).getReg(); + Info.False = MI.getOperand(3).getReg(); + + if (!(Info.LHS == Info.True && Info.RHS == Info.False) && + !(Info.LHS == Info.False && Info.RHS == Info.True)) + return false; + + switch (Info.Pred) { + case CmpInst::FCMP_FALSE: + case CmpInst::FCMP_OEQ: + case CmpInst::FCMP_ONE: + case CmpInst::FCMP_ORD: + case CmpInst::FCMP_UNO: + case CmpInst::FCMP_UEQ: + case CmpInst::FCMP_UNE: + case CmpInst::FCMP_TRUE: + return false; + default: + return true; + } +} + +static void applySelectFCmpToFMinToFMaxLegacy(MachineInstr &MI, + const FMinFMaxLegacyInfo &Info) { + + auto buildNewInst = [&MI](unsigned Opc, Register X, Register Y) { + MachineIRBuilder MIB(MI); + MIB.buildInstr(Opc, {MI.getOperand(0)}, {X, Y}, MI.getFlags()); + }; + + switch (Info.Pred) { + case CmpInst::FCMP_ULT: + case CmpInst::FCMP_ULE: + if (Info.LHS == Info.True) + buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.RHS, Info.LHS); + else + buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.LHS, Info.RHS); + break; + case CmpInst::FCMP_OLE: + case CmpInst::FCMP_OLT: { + // We need to permute the operands to get the correct NaN behavior. The + // selected operand is the second one based on the failing compare with NaN, + // so permute it based on the compare type the hardware uses. + if (Info.LHS == Info.True) + buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.LHS, Info.RHS); + else + buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.RHS, Info.LHS); + break; + } + case CmpInst::FCMP_UGE: + case CmpInst::FCMP_UGT: { + if (Info.LHS == Info.True) + buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.RHS, Info.LHS); + else + buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.LHS, Info.RHS); + break; + } + case CmpInst::FCMP_OGT: + case CmpInst::FCMP_OGE: { + if (Info.LHS == Info.True) + buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.LHS, Info.RHS); + else + buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.RHS, Info.LHS); + break; + } + default: + llvm_unreachable("predicate should not have matched"); + } + + MI.eraseFromParent(); +} + + +#define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS +#include "AMDGPUGenPostLegalizeGICombiner.inc" +#undef AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS + +namespace { +#define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H +#include "AMDGPUGenPostLegalizeGICombiner.inc" +#undef AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H + +class AMDGPUPostLegalizerCombinerInfo : public CombinerInfo { + GISelKnownBits *KB; + MachineDominatorTree *MDT; + +public: + AMDGPUGenPostLegalizerCombinerHelper Generated; + + AMDGPUPostLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize, + const AMDGPULegalizerInfo *LI, + GISelKnownBits *KB, MachineDominatorTree *MDT) + : CombinerInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true, + /*LegalizerInfo*/ LI, EnableOpt, OptSize, MinSize), + KB(KB), MDT(MDT) { + if (!Generated.parseCommandLineOption()) + report_fatal_error("Invalid rule identifier"); + } + + virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI, + MachineIRBuilder &B) const override; +}; + +bool AMDGPUPostLegalizerCombinerInfo::combine(GISelChangeObserver &Observer, + MachineInstr &MI, + MachineIRBuilder &B) const { + CombinerHelper Helper(Observer, B, KB, MDT); + + if (Generated.tryCombineAll(Observer, MI, B, Helper)) + return true; + + switch (MI.getOpcode()) { + case TargetOpcode::G_SHL: + case TargetOpcode::G_LSHR: + case TargetOpcode::G_ASHR: + // On some subtargets, 64-bit shift is a quarter rate instruction. In the + // common case, splitting this into a move and a 32-bit shift is faster and + // the same code size. + return Helper.tryCombineShiftToUnmerge(MI, 32); + } + + return false; +} + +#define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP +#include "AMDGPUGenPostLegalizeGICombiner.inc" +#undef AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP + +// Pass boilerplate +// ================ + +class AMDGPUPostLegalizerCombiner : public MachineFunctionPass { +public: + static char ID; + + AMDGPUPostLegalizerCombiner(bool IsOptNone = false); + + StringRef getPassName() const override { + return "AMDGPUPostLegalizerCombiner"; + } + + bool runOnMachineFunction(MachineFunction &MF) override; + + void getAnalysisUsage(AnalysisUsage &AU) const override; +private: + bool IsOptNone; +}; +} // end anonymous namespace + +void AMDGPUPostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(); + AU.setPreservesCFG(); + getSelectionDAGFallbackAnalysisUsage(AU); + AU.addRequired(); + AU.addPreserved(); + if (!IsOptNone) { + AU.addRequired(); + AU.addPreserved(); + } + MachineFunctionPass::getAnalysisUsage(AU); +} + +AMDGPUPostLegalizerCombiner::AMDGPUPostLegalizerCombiner(bool IsOptNone) + : MachineFunctionPass(ID), IsOptNone(IsOptNone) { + initializeAMDGPUPostLegalizerCombinerPass(*PassRegistry::getPassRegistry()); +} + +bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { + if (MF.getProperties().hasProperty( + MachineFunctionProperties::Property::FailedISel)) + return false; + auto *TPC = &getAnalysis(); + const Function &F = MF.getFunction(); + bool EnableOpt = + MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F); + + const GCNSubtarget &ST = MF.getSubtarget(); + const AMDGPULegalizerInfo *LI + = static_cast(ST.getLegalizerInfo()); + + GISelKnownBits *KB = &getAnalysis().get(MF); + MachineDominatorTree *MDT = + IsOptNone ? nullptr : &getAnalysis(); + AMDGPUPostLegalizerCombinerInfo PCInfo(EnableOpt, F.hasOptSize(), + F.hasMinSize(), LI, KB, MDT); + Combiner C(PCInfo, TPC); + return C.combineMachineInstrs(MF, /*CSEInfo*/ nullptr); +} + +char AMDGPUPostLegalizerCombiner::ID = 0; +INITIALIZE_PASS_BEGIN(AMDGPUPostLegalizerCombiner, DEBUG_TYPE, + "Combine AMDGPU machine instrs after legalization", + false, false) +INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) +INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis) +INITIALIZE_PASS_END(AMDGPUPostLegalizerCombiner, DEBUG_TYPE, + "Combine AMDGPU machine instrs after legalization", false, + false) + +namespace llvm { +FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone) { + return new AMDGPUPostLegalizerCombiner(IsOptNone); +} +} // end namespace llvm Index: llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp @@ -28,112 +28,13 @@ using namespace llvm; using namespace MIPatternMatch; -struct FMinFMaxLegacyInfo { - Register LHS; - Register RHS; - Register True; - Register False; - CmpInst::Predicate Pred; -}; - -// TODO: Make sure fmin_legacy/fmax_legacy don't canonicalize -static bool matchFMinFMaxLegacy(MachineInstr &MI, MachineRegisterInfo &MRI, - MachineFunction &MF, FMinFMaxLegacyInfo &Info) { - // FIXME: Combines should have subtarget predicates, and we shouldn't need - // this here. - if (!MF.getSubtarget().hasFminFmaxLegacy()) - return false; - - // FIXME: Type predicate on pattern - if (MRI.getType(MI.getOperand(0).getReg()) != LLT::scalar(32)) - return false; - - Register Cond = MI.getOperand(1).getReg(); - if (!MRI.hasOneNonDBGUse(Cond) || - !mi_match(Cond, MRI, - m_GFCmp(m_Pred(Info.Pred), m_Reg(Info.LHS), m_Reg(Info.RHS)))) - return false; - - Info.True = MI.getOperand(2).getReg(); - Info.False = MI.getOperand(3).getReg(); - - if (!(Info.LHS == Info.True && Info.RHS == Info.False) && - !(Info.LHS == Info.False && Info.RHS == Info.True)) - return false; - - switch (Info.Pred) { - case CmpInst::FCMP_FALSE: - case CmpInst::FCMP_OEQ: - case CmpInst::FCMP_ONE: - case CmpInst::FCMP_ORD: - case CmpInst::FCMP_UNO: - case CmpInst::FCMP_UEQ: - case CmpInst::FCMP_UNE: - case CmpInst::FCMP_TRUE: - return false; - default: - return true; - } -} - -static void applySelectFCmpToFMinToFMaxLegacy(MachineInstr &MI, - const FMinFMaxLegacyInfo &Info) { - - auto buildNewInst = [&MI](unsigned Opc, Register X, Register Y) { - MachineIRBuilder MIB(MI); - MIB.buildInstr(Opc, {MI.getOperand(0)}, {X, Y}, MI.getFlags()); - }; - - switch (Info.Pred) { - case CmpInst::FCMP_ULT: - case CmpInst::FCMP_ULE: - if (Info.LHS == Info.True) - buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.RHS, Info.LHS); - else - buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.LHS, Info.RHS); - break; - case CmpInst::FCMP_OLE: - case CmpInst::FCMP_OLT: { - // We need to permute the operands to get the correct NaN behavior. The - // selected operand is the second one based on the failing compare with NaN, - // so permute it based on the compare type the hardware uses. - if (Info.LHS == Info.True) - buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.LHS, Info.RHS); - else - buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.RHS, Info.LHS); - break; - } - case CmpInst::FCMP_UGE: - case CmpInst::FCMP_UGT: { - if (Info.LHS == Info.True) - buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.RHS, Info.LHS); - else - buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.LHS, Info.RHS); - break; - } - case CmpInst::FCMP_OGT: - case CmpInst::FCMP_OGE: { - if (Info.LHS == Info.True) - buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.LHS, Info.RHS); - else - buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.RHS, Info.LHS); - break; - } - default: - llvm_unreachable("predicate should not have matched"); - } - - MI.eraseFromParent(); -} - - #define AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS -#include "AMDGPUGenGICombiner.inc" +#include "AMDGPUGenPreLegalizeGICombiner.inc" #undef AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS namespace { #define AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H -#include "AMDGPUGenGICombiner.inc" +#include "AMDGPUGenPreLegalizeGICombiner.inc" #undef AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H class AMDGPUPreLegalizerCombinerInfo : public CombinerInfo { @@ -165,13 +66,6 @@ return true; switch (MI.getOpcode()) { - case TargetOpcode::G_SHL: - case TargetOpcode::G_LSHR: - case TargetOpcode::G_ASHR: - // On some subtargets, 64-bit shift is a quarter rate instruction. In the - // common case, splitting this into a move and a 32-bit shift is faster and - // the same code size. - return Helper.tryCombineShiftToUnmerge(MI, 32); case TargetOpcode::G_CONCAT_VECTORS: return Helper.tryCombineConcatVectors(MI); case TargetOpcode::G_SHUFFLE_VECTOR: @@ -182,7 +76,7 @@ } #define AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP -#include "AMDGPUGenGICombiner.inc" +#include "AMDGPUGenPreLegalizeGICombiner.inc" #undef AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP // Pass boilerplate @@ -194,7 +88,9 @@ AMDGPUPreLegalizerCombiner(bool IsOptNone = false); - StringRef getPassName() const override { return "AMDGPUPreLegalizerCombiner"; } + StringRef getPassName() const override { + return "AMDGPUPreLegalizerCombiner"; + } bool runOnMachineFunction(MachineFunction &MF) override; Index: llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -218,6 +218,7 @@ initializeAMDGPULowerKernelAttributesPass(*PR); initializeAMDGPULowerIntrinsicsPass(*PR); initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR); + initializeAMDGPUPostLegalizerCombinerPass(*PR); initializeAMDGPUPreLegalizerCombinerPass(*PR); initializeAMDGPUPromoteAllocaPass(*PR); initializeAMDGPUCodeGenPreparePass(*PR); @@ -624,6 +625,7 @@ void addPreLegalizeMachineIR() override; bool addLegalizeMachineIR() override; bool addRegBankSelect() override; + void addPreRegBankSelect() override; void addPreGlobalInstructionSelect() override; bool addGlobalInstructionSelect() override; void addFastRegAlloc() override; @@ -911,6 +913,11 @@ return false; } +void GCNPassConfig::addPreRegBankSelect() { + bool IsOptNone = getOptLevel() == CodeGenOpt::None; + addPass(createAMDGPUPostLegalizeCombiner(IsOptNone)); +} + bool GCNPassConfig::addRegBankSelect() { addPass(new RegBankSelect()); return false; Index: llvm/lib/Target/AMDGPU/CMakeLists.txt =================================================================== --- llvm/lib/Target/AMDGPU/CMakeLists.txt +++ llvm/lib/Target/AMDGPU/CMakeLists.txt @@ -15,8 +15,10 @@ set(LLVM_TARGET_DEFINITIONS AMDGPUGISel.td) tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel) -tablegen(LLVM AMDGPUGenGICombiner.inc -gen-global-isel-combiner +tablegen(LLVM AMDGPUGenPreLegalizeGICombiner.inc -gen-global-isel-combiner -combiners="AMDGPUPreLegalizerCombinerHelper") +tablegen(LLVM AMDGPUGenPostLegalizeGICombiner.inc -gen-global-isel-combiner + -combiners="AMDGPUPostLegalizerCombinerHelper") set(LLVM_TARGET_DEFINITIONS R600.td) tablegen(LLVM R600GenAsmWriter.inc -gen-asm-writer) @@ -60,6 +62,7 @@ AMDGPUMacroFusion.cpp AMDGPUMCInstLower.cpp AMDGPUOpenCLEnqueuedBlockLowering.cpp + AMDGPUPostLegalizerCombiner.cpp AMDGPUPreLegalizerCombiner.cpp AMDGPUPromoteAlloca.cpp AMDGPUPropagateAttributes.cpp Index: llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: narrow_ashr_s64_32_s64amt Index: llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: narrow_lshr_s64_32_s64amt Index: llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- Index: llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll @@ -253,3 +253,24 @@ %val = select i1 %cmp, double %b, double %a ret double %val } + +define <2 x float> @v_test_fmax_legacy_ogt_v2f32(<2 x float> %a, <2 x float> %b) { +; GFX6-LABEL: v_test_fmax_legacy_ogt_v2f32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_max_legacy_f32_e32 v0, v0, v2 +; GFX6-NEXT: v_max_legacy_f32_e32 v1, v1, v3 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_test_fmax_legacy_ogt_v2f32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v1, v3 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; GFX8-NEXT: s_setpc_b64 s[30:31] + %cmp = fcmp ogt <2 x float> %a, %b + %val = select <2 x i1> %cmp, <2 x float> %a, <2 x float> %b + ret <2 x float> %val +} Index: llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll @@ -382,3 +382,24 @@ %val = select i1 %cmp, float %a, float %b ret float %val } + +define <2 x float> @v_test_fmin_legacy_ole_v2f32(<2 x float> %a, <2 x float> %b) { +; GFX6-LABEL: v_test_fmin_legacy_ole_v2f32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_min_legacy_f32_e32 v0, v0, v2 +; GFX6-NEXT: v_min_legacy_f32_e32 v1, v1, v3 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_test_fmin_legacy_ole_v2f32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_cmp_le_f32_e32 vcc, v0, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_cmp_le_f32_e32 vcc, v1, v3 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; GFX8-NEXT: s_setpc_b64 s[30:31] + %cmp = fcmp ole <2 x float> %a, %b + %val = select <2 x i1> %cmp, <2 x float> %a, <2 x float> %b + ret <2 x float> %val +} Index: llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll @@ -26,9 +26,7 @@ ; 10 + 9 (36 prepended implicit bytes) + 2(out pointer) = 21 = 0x15 -; OS-UNKNOWN: s_add_u32 s[[LO:[0-9]+]], s0, 44 -; OS-UNKNOWN-NEXT: s_addc_u32 s[[HI:[0-9]+]], s1, 0 -; OS-UNKNOWN-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[LO]]:[[HI]]{{\]}}, 0xa +; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x15 define amdgpu_kernel void @test_implicit(i32 addrspace(1)* %out) #1 { %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() %header.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*